Update JobSet

This commit was merged in pull request #64.
This commit is contained in:
2025-10-21 18:04:10 +08:00
parent 0aa374e65f
commit eef64d6338
9 changed files with 3075 additions and 2782 deletions

View File

@@ -26,8 +26,10 @@
"output_filename": "kirdy_fp_fiber_optic_adapter_mounting_plate_type_1.step",
"overwrite": false,
"subst_models": true,
"use_defined_origin": false,
"use_drill_origin": false,
"use_grid_origin": false,
"use_pcb_center_origin": false,
"user_origin.x": 145.1,
"user_origin.y": 99.8,
"vrml_model_dir": "",
@@ -45,7 +47,7 @@
"crossout_dnp_footprints_on_fab_layers": true,
"description": "",
"drawing_sheet": "",
"drill_shape": 2,
"drill_shape": "none",
"front_fp_property_popups": true,
"hide_dnp_footprints_on_fab_layers": false,
"layers": [
@@ -112,7 +114,7 @@
"description": "",
"disable_aperture_macros": false,
"drawing_sheet": "",
"drill_shape": 2,
"drill_shape": "none",
"hide_dnp_footprints_on_fab_layers": false,
"include_netlist_attributes": true,
"layers": [
@@ -190,6 +192,18 @@
"zero_format": "decimal"
},
"type": "pcb_export_drill"
},
{
"description": "",
"id": "4e207456-e91d-4367-af1b-e2858095fa20",
"settings": {
"command": "mv ${JOBSET_OUTPUT_WORK_PATH}kirdy_fp_fiber_optic_adapter_mounting_plate_type_1-F_Fab.pdf ${JOBSET_OUTPUT_WORK_PATH}kirdy_fp_fiber_optic_adapter_mounting_plate_type_1_Mechanical_Drawings.pdf",
"description": "",
"ignore_exit_code": false,
"output_filename": "",
"record_output": false
},
"type": "special_execute"
}
],
"meta": {

View File

@@ -26,8 +26,10 @@
"output_filename": "kirdy_fp_fiber_optic_adapter_mounting_plate_type_2.step",
"overwrite": false,
"subst_models": true,
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"user_origin.y": 100.0,
"vrml_model_dir": "",
@@ -45,7 +47,7 @@
"crossout_dnp_footprints_on_fab_layers": true,
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"drawing_sheet": "",
"drill_shape": 2,
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"front_fp_property_popups": true,
"hide_dnp_footprints_on_fab_layers": false,
"layers": [
@@ -113,7 +115,7 @@
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"drill_shape": 2,
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"include_netlist_attributes": true,
"layers": [
@@ -191,6 +193,18 @@
"zero_format": "decimal"
},
"type": "pcb_export_drill"
},
{
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"id": "561df446-ee69-4969-82f0-8e6482595655",
"settings": {
"command": "mv ${JOBSET_OUTPUT_WORK_PATH}kirdy_fp_fiber_optic_adapter_mounting_plate_type_2-F_Fab.pdf ${JOBSET_OUTPUT_WORK_PATH}kirdy_fp_fiber_optic_adapter_mounting_plate_type_2_Mechanical_Drawings.pdf",
"description": "",
"ignore_exit_code": false,
"output_filename": "",
"record_output": false
},
"type": "special_execute"
}
],
"meta": {

View File

@@ -4,6 +4,7 @@
"description": "",
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"bg_style": "default",
"description": "",
"floor": false,
@@ -30,21 +31,25 @@
0.0,
0.0
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"output_filename": "kirdy_front_panel.png",
"output_filename": "kirdy_front_panel_text_markings_illustration.png",
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"pan_y": 0.0,
"pan_z": 0.0,
"perspective": true,
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"zoom": 1.0
"zoom": 1.75
},
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},
@@ -74,9 +79,11 @@
"output_filename": "kirdy_front_panel.step",
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"vrml_model_dir": "",
"vrml_relative_paths": false
@@ -84,14 +91,26 @@
"type": "pcb_export_3d"
},
{
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"description": "Rename 3D Model File",
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"description": "",
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"output_filename": "9f2d2a63-fb10-47ea-8cbb-e9d6eea7764c.log",
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{
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@@ -125,7 +144,9 @@
"In3.Cu",
"F.SilkS"
],
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],
"mirror": false,
"negative": false,
"output_filename": "",
@@ -143,6 +164,92 @@
},
"type": "pcb_export_dxf"
},
{
"description": "Rename DXF Contours File",
"id": "4f6762f7-d0cd-42f4-92dd-e295d0b5aa16",
"settings": {
"command": "mv ${JOBSET_OUTPUT_WORK_PATH}kirdy_front_panel-F_Silkscreen.dxf ${JOBSET_OUTPUT_WORK_PATH}kirdy_front_panel_text_markings_contour.dxf",
"description": "",
"ignore_exit_code": false,
"output_filename": "4f6762f7-d0cd-42f4-92dd-e295d0b5aa16.log",
"record_output": false
},
"type": "special_execute"
},
{
"description": "Export DXF Concrete Lines",
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"settings": {
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"crossout_dnp_footprints_on_fab_layers": true,
"description": "",
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"drill_shape": "none",
"gen_mode": "multi",
"hide_dnp_footprints_on_fab_layers": false,
"layers": [
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"In22.Cu",
"In21.Cu",
"In20.Cu",
"In19.Cu",
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"In17.Cu",
"In16.Cu",
"In15.Cu",
"In14.Cu",
"In13.Cu",
"In12.Cu",
"In11.Cu",
"In10.Cu",
"In9.Cu",
"In8.Cu",
"In7.Cu",
"In6.Cu",
"In5.Cu",
"In4.Cu",
"In3.Cu",
"F.SilkS"
],
"layers_to_include_on_all_layers": [
"Edge.Cuts"
],
"mirror": false,
"negative": false,
"output_filename": "",
"plot_drawing_sheet": false,
"plot_footprint_values": true,
"plot_graphic_items_using_contours": false,
"plot_pad_numbers": false,
"plot_ref_des": true,
"polygon_mode": false,
"sketch_dnp_footprints_on_fab_layers": true,
"sketch_pads_on_fab_layers": false,
"subtract_solder_mask_from_silk": false,
"units": "in",
"use_drill_origin": false
},
"type": "pcb_export_dxf"
},
{
"description": "Rename DXF Concrete Lines File",
"id": "b3962897-98f7-4d09-8dbf-277f6eff47a1",
"settings": {
"command": "mv ${JOBSET_OUTPUT_WORK_PATH}kirdy_front_panel-F_Silkscreen.dxf ${JOBSET_OUTPUT_WORK_PATH}kirdy_front_panel_text_markings_concrete_lines.dxf ",
"description": "",
"ignore_exit_code": false,
"output_filename": "b3962897-98f7-4d09-8dbf-277f6eff47a1.log",
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},
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{
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"id": "0eddc15d-7225-4742-9c0b-905af192770e",
@@ -153,7 +260,7 @@
"crossout_dnp_footprints_on_fab_layers": true,
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"drawing_sheet": "",
"drill_shape": 2,
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"hide_dnp_footprints_on_fab_layers": false,
"layers": [
@@ -187,7 +294,10 @@
"In3.Cu",
"F.SilkS"
],
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"layers_to_include_on_all_layers": [
"User.2",
"Edge.Cuts"
],
"mirror": false,
"negative": false,
"output_filename": "",
@@ -204,6 +314,30 @@
"use_drill_origin": false
},
"type": "pcb_export_pdf"
},
{
"description": "Rename PDF File",
"id": "6eae10b1-cba9-45db-999f-17f430dd19d5",
"settings": {
"command": "mv ${JOBSET_OUTPUT_WORK_PATH}kirdy_front_panel-F_Silkscreen.pdf ${JOBSET_OUTPUT_WORK_PATH}kirdy_front_panel_mechanical_drawings.pdf",
"description": "",
"ignore_exit_code": false,
"output_filename": "6eae10b1-cba9-45db-999f-17f430dd19d5.log",
"record_output": false
},
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},
{
"description": "",
"id": "f6e70ce7-92c7-43a0-bb4e-1797db250419",
"settings": {
"command": "echo test",
"description": "",
"ignore_exit_code": false,
"output_filename": "",
"record_output": false
},
"type": "special_execute"
}
],
"meta": {

File diff suppressed because it is too large Load Diff

View File

@@ -487,10 +487,10 @@
"gencad": "",
"idf": "",
"netlist": "",
"plot": "../Panel_Production_Files/",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "../Freecad/kirdy_front_panel_markings_v1_0_updated.step",
"step": "kirdy_front_panel_full_assembly.step",
"svg": "",
"vrml": ""
},

View File

@@ -6607,6 +6607,82 @@
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@@ -6911,44 +6987,6 @@
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@@ -8276,44 +8314,6 @@
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View File

@@ -26,8 +26,10 @@
"output_filename": "kirdy.step",
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"use_pcb_center_origin": false,
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"user_origin.y": 50.0,
"vrml_model_dir": "",
@@ -45,7 +47,7 @@
"description": "",
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"drill_shape": 2,
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"hide_dnp_footprints_on_fab_layers": false,
"include_netlist_attributes": true,
"layers": [
@@ -254,6 +256,112 @@
"zero_copies_error": false
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{
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@@ -261,9 +369,18 @@
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@@ -495,6 +495,7 @@
"single_global_label": "ignore",
"unannotated": "error",
"unconnected_wire_endpoint": "warning",
"undefined_netclass": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"