From dfeb1ec6a8d9e7b97e6bcb1849e4cbaf684b8d8b Mon Sep 17 00:00:00 2001 From: linuswck Date: Tue, 24 Oct 2023 10:37:36 +0800 Subject: [PATCH] sch: LD DAC add parallel Cap to output resistor - Increase the Mod_In Signal Bandwidth - See Issue #22 --- driveStage.kicad_sch | 71 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 69 insertions(+), 2 deletions(-) diff --git a/driveStage.kicad_sch b/driveStage.kicad_sch index 1796372..bb713bd 100644 --- a/driveStage.kicad_sch +++ b/driveStage.kicad_sch @@ -1642,6 +1642,9 @@ (junction (at 210.185 219.71) (diameter 0) (color 0 0 0 0) (uuid 89e7290a-3c37-46d9-9957-5b8c62570383) ) + (junction (at 246.38 110.49) (diameter 0) (color 0 0 0 0) + (uuid 8b5dec63-829c-4b3f-965d-9ff3a0dd656a) + ) (junction (at 246.38 92.71) (diameter 0) (color 0 0 0 0) (uuid 8df0d125-520a-48d3-a32f-5bab0e098d4c) ) @@ -1678,6 +1681,9 @@ (junction (at 336.55 59.69) (diameter 0) (color 0 0 0 0) (uuid b7a0d8ed-3c9d-42c3-b5b1-7c959c0404cb) ) + (junction (at 246.38 97.155) (diameter 0) (color 0 0 0 0) + (uuid b8e221d1-38cc-4e0c-9be4-7b5e7a9ef37f) + ) (junction (at 344.17 39.37) (diameter 0) (color 0 0 0 0) (uuid ba37a5c7-31f6-4ab6-9803-c0390d5bc3f0) ) @@ -1767,6 +1773,10 @@ (stroke (width 0) (type default)) (uuid 0e7134f0-7790-400c-8b38-98343ab19bdd) ) + (wire (pts (xy 237.49 107.315) (xy 237.49 110.49)) + (stroke (width 0) (type default)) + (uuid 0efb2d7c-19e9-4d72-a402-3a1cc12fd03b) + ) (wire (pts (xy 318.77 59.69) (xy 336.55 59.69)) (stroke (width 0) (type default)) (uuid 0f0141fa-6db6-457f-b106-77adb89c3dd9) @@ -1843,6 +1853,10 @@ (stroke (width 0) (type default)) (uuid 283aa5a9-3cc2-4e9c-979f-9a0c5857e0d4) ) + (wire (pts (xy 246.38 107.95) (xy 246.38 110.49)) + (stroke (width 0) (type default)) + (uuid 2aefd853-a243-46ae-9f24-bccb1f407b06) + ) (wire (pts (xy 367.03 114.3) (xy 367.03 115.57)) (stroke (width 0) (type default)) (uuid 2b7e28cc-40fb-4836-a61c-27ec24c6ab39) @@ -1864,6 +1878,10 @@ (stroke (width 0) (type default)) (uuid 318c085c-127e-41b8-99c0-6ded63699fca) ) + (wire (pts (xy 237.49 110.49) (xy 246.38 110.49)) + (stroke (width 0) (type default)) + (uuid 32f3c287-3c32-43a6-9a79-405b5e3f56ca) + ) (wire (pts (xy 252.73 200.66) (xy 252.73 210.185)) (stroke (width 0) (type default)) (uuid 33ceb95e-eba0-4aa8-a751-2b7b0fad8ee1) @@ -1876,6 +1894,10 @@ (stroke (width 0) (type default)) (uuid 3c8b01cc-e836-4ddd-b110-ba8ac9076af2) ) + (wire (pts (xy 237.49 97.155) (xy 246.38 97.155)) + (stroke (width 0) (type default)) + (uuid 3d71ad0b-9dc5-40b6-bc3e-5ca2d8d5b748) + ) (polyline (pts (xy 322.58 106.68) (xy 340.36 106.68)) (stroke (width 0) (type default)) (uuid 3ed2e1e9-b9b2-429f-a86d-4e4b387d443f) @@ -2058,7 +2080,7 @@ (stroke (width 0) (type default)) (uuid 79168543-81f6-485c-83eb-0ce9cf4a40bc) ) - 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