From 20198f5eaba55a557c39045736dcf4d46e7a1d0e Mon Sep 17 00:00:00 2001
From: linuswck <linuswck@m-labs.hk>
Date: Mon, 20 Nov 2023 11:09:48 +0800
Subject: [PATCH] drc: Check PWR nets clearance on pri and sec sides - Pri: PoE
 PWR nets - Sec: PWR nets like GND, 3V3 etc

---
 kirdy.kicad_dru | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 kirdy.kicad_dru

diff --git a/kirdy.kicad_dru b/kirdy.kicad_dru
new file mode 100644
index 0000000..c889518
--- /dev/null
+++ b/kirdy.kicad_dru
@@ -0,0 +1,5 @@
+(version 1)
+
+(rule "PoE PWR Clearance Between GND and PoE AC Input"
+	(constraint clearance (min 1.0mm))
+	(condition " A.NetClass != B.NetClass && A.NetClass == 'PWR'  && B.NetClass == 'POE_PWR' " ))