sinara-hw
/
datasheets
7
1
Fork 3
Code Issues 8 Pull Requests Projects Releases Wiki Activity
datasheets/2118-2128.tex

607 lines
29 KiB
TeX
Raw Blame History

\include{preamble.tex}
\graphicspath{{images}}
\title{2118 BNC-TTL / 2128 SMA-TTL}
\author{M-Labs Limited}
\date{January 2022}
\revision{Revision 2}
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
\begin{document}
\maketitle
\section{Features}
\begin{itemize}
\item{8 channels.}
\item{Input and output capable.}
\item{Galvanically isolated.}
\item{3ns minimum pulse width.}
\item{BNC or SMA connectors.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Photon counting.}
\item{External equipment trigger.}
\item{Optical shutter control.}
\end{itemize}
\section{General Description}
The 2118 BNC-TTL card is a 8hp EEM module, while the 2128 SMA-TTL card is a 4hp EEM module.
Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides two banks of four digital channels each, with BNC (2118) or SMA (2128) connectors.
Each bank has individual ground isolation.
The direction (input or output) of each bank can be selected using DIP switches.
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
Outputs tolerate short circuits indefinitely.
The card support a minimum pulse width of 3ns.
% Switch to next column
\vfill\break
\begin{figure}[h]
\centering
\scalebox{0.88}{
\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
\begin{scope}[yshift=1.3cm]
\draw[color=white, text=black] (-0.1,0) node[twoportshape,t={IO 0}, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (io0) {};
\draw[color=white, text=black] (-0.1,-0.7) node[twoportshape,t={IO 1}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io1) {};
\draw[color=white, text=black] (-0.1,-1.4) node[twoportshape,t={IO 2}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io2) {};
\draw[color=white, text=black] (-0.1,-2.1) node[twoportshape,t={IO 3}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io3) {};
\node [label={[xshift=-0.18cm, yshift=-0.305cm]\tiny{IO 0}}] {};
\node [label={[xshift=-0.18cm, yshift=-0.97cm]\tiny{IO 1}}] {};
\node [label={[xshift=-0.18cm, yshift=-1.64cm]\tiny{IO 2}}] {};
\node [label={[xshift=-0.18cm, yshift=-2.302cm]\tiny{IO 3}}] {};
% draw female SMA_0,1,2,3
\begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=-90, xshift=10cm, yshift=2cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=-90, xshift=20cm, yshift=2cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=-90, xshift=30cm, yshift=2cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus1) {};
\draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso1) {};
\draw (3.05,-0.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso2) {};
\draw (3.05,-1.4) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso3) {};
\draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso4) {};
\draw (3.05,-2.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso1) {};
\draw (4.5,-1.15) node[twoportshape,t=\fourcm{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds1) {};
\draw (6.8,-0.9) -- ++(0.00001,0) node[twoportshape, anchor=left, t={EEM port}, circuitikz/bipoles/twoport/width=6, scale=0.6, rotate=-90] (kasli) {} ;
\draw (0.8,-3.5) node[twoportshape,t=\fourcm{Per-bank \phantom{spac} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
\draw (3.05,-3.5) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
\draw (5.68,-2.3) node[twoportshape,t=EEPROM, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom) {};
\draw (0.8,-2.7) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
% Termination Switch 1,2,3,4
\begin{scope}[xshift=0.9cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.2cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\end{scope}
% I/O Switch 1, 2
\begin{scope}[xshift=1.2cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.32cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\draw (0.8,-3.05) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
% Termination Switch 5,6,7,8
\begin{scope}[xshift=0.9cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.2cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
% channel 5,6,7,8
\begin{scope}[yshift=-3.6cm]
\draw[color=white, text=black] (-0.1,0) node[twoportshape,t={IO 4}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io4) {};
\draw[color=white, text=black] (-0.1,-0.7) node[twoportshape,t={IO 5}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io5) {};
\draw[color=white, text=black] (-0.1,-1.4) node[twoportshape,t={IO 6}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io6) {};
\draw[color=white, text=black] (-0.1,-2.1) node[twoportshape,t={IO 7}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io7) {};
\node [label={[xshift=-0.18cm, yshift=-0.305cm]\tiny{IO 4}}] {};
\node [label={[xshift=-0.18cm, yshift=-0.97cm]\tiny{IO 5}}] {};
\node [label={[xshift=-0.18cm, yshift=-1.64cm]\tiny{IO 6}}] {};
\node [label={[xshift=-0.18cm, yshift=-2.302cm]\tiny{IO 7}}] {};
% draw female SMA 4,5,6,7
\begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=-90, xshift=10cm, yshift=2cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=-90, xshift=20cm, yshift=2cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=-90, xshift=30cm, yshift=2cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus2) {};
\draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso5) {};
\draw (3.05,-0.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso6) {};
\draw (3.05,-1.4) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso7) {};
\draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso8) {};
\draw (3.05,0.6) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso2) {};
\draw (4.5,-1.05) node[twoportshape,t=\fourcm{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds2) {};
\end{scope}
% Drawing Connections
\draw [latexslim-latexslim] (io0.east) -- ++(1,0);
\draw [latexslim-latexslim] (io1.east) -- ++(1,0);
\draw [latexslim-latexslim] (io2.east) -- ++(1,0);
\draw [latexslim-latexslim] (io3.east) -- ++(1,0);
\draw [latexslim-latexslim] (io4.east) -- ++(1,0);
\draw [latexslim-latexslim] (io5.east) -- ++(1,0);
\draw [latexslim-latexslim] (io6.east) -- ++(1,0);
\draw [latexslim-latexslim] (io7.east) -- ++(1,0);
\draw [latexslim-latexslim] (iso1.west) -- ++(-0.72,0) ;
\draw [latexslim-latexslim] (iso2.west) -- ++(-0.72,0) ;
\draw [latexslim-latexslim] (iso3.west) -- ++(-0.72,0) ;
\draw [latexslim-latexslim] (iso4.west) -- ++(-0.72,0) ;
\draw [latexslim-latexslim] (iso1.east) -- ++(0.69,0);
\draw [latexslim-latexslim] (iso2.east) -- ++(0.69,0);
\draw [latexslim-latexslim] (iso3.east) -- ++(0.69,0);
\draw [latexslim-latexslim] (iso4.east) -- ++(0.69,0);
\draw [latexslim-latexslim] (iso5.west) -- ++(-0.72,0) ;
\draw [latexslim-latexslim] (iso6.west) -- ++(-0.72,0) ;
\draw [latexslim-latexslim] (iso7.west) -- ++(-0.72,0) ;
\draw [latexslim-latexslim] (iso8.west) -- ++(-0.72,0) ;
\draw [latexslim-latexslim] (iso5.east) -- ++(0.7,0);
\draw [latexslim-latexslim] (iso6.east) -- ++(0.7,0);
\draw [latexslim-latexslim] (iso7.east) -- ++(0.7,0);
\draw [latexslim-latexslim] (iso8.east) -- ++(0.7,0);
\draw [latexslim-] (eeprom.south) -- ++(0,-0.95);
\draw [latexslim-latexslim] (lvds1.north) -- ++(1.61,0);
\draw [latexslim-latexslim] (lvds2.north) -- ++(1.62,0);
\draw [latexslim-latexslim] (i2c.east) -- ++(2.77,0);
\draw [latexslim-] (i2c.west) -- (ioswitch.east) ;
\draw [-latexslim] (i2c.north east) -- (lvds1.south east);
\draw [-latexslim] (i2c.south east) -- (lvds2.south west);
\draw [-latexslim] (i2ciso1.west) -- (bus1.north east);
\draw [thin] [-latexslim] (i2c.north) -- (i2ciso1.south);
\draw [-latexslim] (i2ciso2.west) -- (bus2.north west);
\draw [thin] [-latexslim] (i2c.south) -- (i2ciso2.north);
% termination switch connection
\draw (0.65,-1.18) -- ++(0,2.47) ;
\draw (0.75,-1.18) -- ++(0,1.77) ;
\draw (0.85,-1.18) -- ++(0,1.07) ;
\draw (0.95,-1.18) -- ++(0,0.37) ;
\draw (0.65,-3.25) -- ++(0,-2.45) ;
\draw (0.75,-3.25) -- ++(0,-1.75) ;
\draw (0.85,-3.25) -- ++(0,-1.05) ;
\draw (0.95,-3.25) -- ++(0,-0.35) ;
\node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(io0) (i2ciso1.south west)] (box1) {};
\node[fill=white, rotate=-90] at (box1.west) {GND BANK 1};
\node[fill=white,above] at (box1.north) {\tiny{Either all 4 channels are inputs or all 4 channels are outputs }};
\node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(io4)(termswitch2) (iso8.south west)] (box2) {};
\node[fill=white, rotate=-90] at (box2.west) {GND BANK 2};
\node[fill=white,below] at (box2.south) {\tiny{Either all 4 channels are inputs or all 4 channels are outputs }};
\end{circuitikz}
}
\caption{Simplified Block Diagram}
\end{figure}
\begin{figure}[hbt!]
\centering
\subfloat[\centering BNC-TTL]{{
\includegraphics[height=1.8in]{2118-2128/DIO_BNC_FP.jpg}
\includegraphics[height=1.8in]{2118-2128/photo2118.jpg}
}}%
\subfloat[\centering SMA-TTL]{{
\includegraphics[height=1.8in]{2118-2128/DIO_SMA_FP.jpg}
\includegraphics[height=1.8in]{2118-2128/photo2128.jpg}
}}%
\caption{BNC-TTL/SMA-TTL Card photos}%
\label{fig:example}%
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\section{Electrical Specifications}
All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
Specifications are based on the bus transceivers IC (SN74BCT25245DW\footnote{\label{transceiver}https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf})
and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}).
The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}https://github.com/sinara-hw/sinara/issues/187}.
\begin{table}[h]
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
High-level input voltage\repeatfootnote{transceiver} & $V_{IH}$ & 2 & & 5.5* & V & \\
\hline
Low-level input voltage\repeatfootnote{transceiver} & $V_{IL}$ & -0.5 & & 0.8 & V & \\
\hline
Input clamp current\repeatfootnote{transceiver} & $I_{OH}$ & & & -18 & mA & termination disabled \\
\hline
High-level output current\repeatfootnote{transceiver} & $I_{OH}$ & & & -160 & mA & \\
\hline
Low-level output current\repeatfootnote{transceiver} & $I_{OL}$ & & & 376 & mA & \\
\thickhline
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\end{tabularx}
\end{threeparttable}
\end{table}
\begin{table}[h]
\begin{threeparttable}
\caption{Electrical Characteristics}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
High-level output voltage\repeatfootnote{transceiver} & $V_{OH}$ & 2 & & & V & $I_{OH}$=-160mA \\
& & 2.7 & & & V & $I_{OH}$=-6mA \\
\hline
Low-level output voltage\repeatfootnote{transceiver} & $V_{OL}$ & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
& & & & 0.7 & V & $I_{OL}$=376mA \\
\hline
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & & 3 & 5 & ns & \\
\hline
Pulse width distortion\repeatfootnote{isolator} & $PWD$ & & 0.2 & 4.5 & ns & \\
\hline
Peak jitter\repeatfootnote{isolator} & $T_{JIT(PK)}$ & & 350 & & ps & \\
\hline
Data rate\repeatfootnote{isolator} & & 0 & & 150 & Mbps & \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
\newpage
Minimum pulse width was measured\repeatfootnote{sinara187}.
Pulses were generated from a DDS generator as an input of a BNC-TTL card.
The input BNC-TTL card is connected to another BNC-TTL card as an output.
The output signal is measured and shown.
\begin{figure}[h]
\centering
\includegraphics[height=3in]{2118-2128/bnc_ttl_min_pulse_width.png}
\caption{Minimum pulse width required for BNC-TTL card}
\end{figure}
The red trace refers to the input pulses from the DDS generator, while the blue trace is the measured signal from the output BNC-TTL card.
Note that the first input (red) pulse could not propagate through the signal chain.
The first output (blue) pulse is the result of the second input (red, 3ns width) pulse.
\newpage
\section{Front Panel Drawings}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=2.8in]{2118-2128/bnc_ttl_drawings.pdf}
\captionof{figure}{2118 BNC-TTL front panel drawings}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=2.8in]{2118-2128/bnc_ttl_assembly.pdf}
\captionof{figure}{2118 BNC-TTL front panel assembly}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\captionof{table}{Bill of Material (2118 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90560220 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\captionof{table}{Bill of Material (2118 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90457987 & 4 & CSCR M2.5*12.3 PAN PHL SS \\ \hline
2 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
3 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
4 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
5 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
6 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
7 & 3207076 & 0.01 & SCR M2.5*16 PAN 100 21101-222 \\ \hline
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
9 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
10 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT(100PCS) \\ \hline
11 & 90560220 & 1 & FP-LYKJ 3U8HP PANEL \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=3in]{2118-2128/sma_ttl_drawings.pdf}
\captionof{figure}{2128 SMA-TTL front panel drawings}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=3in]{2118-2128/sma_ttl_assembly.pdf}
\captionof{figure}{2128 SMA-TTL front panel assembly}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\captionof{table}{Bill of Material (2128 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90531967 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\captionof{table}{Bill of Material (2128 Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90531967 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3001012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
6 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
7 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
8 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\section{Configuring IO Direction \& Termination}
The termination and IO direction can be configured by switches.
The per-channel termination and per-bank IO direction switches are found at the middle-left and middle-right of both cards respectively.
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
IO direction switches partly decides the IO direction of each bank.
\begin{itemize}
\itemsep0em
\item Closed switch (ON) \\
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
\item Opened switch (OFF) \\
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
\end{itemize}
\begin{figure}[hbt!]
\centering
\subfloat[\centering BNC-TTL]{{
\includegraphics[height=1.5in]{2118-2128/bnc_ttl_switches.jpg}
}}%
\subfloat[\centering SMA-TTL]{{
\includegraphics[height=1.5in]{2118-2128/sma_ttl_switches.jpg}
}}%
\caption{Position of switches}%
\end{figure}
\newpage
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 2118 BNC-TTL/2128 SMA-TTL card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
\subsection{One pulse per second}
The channel should be configured as output in both the gateware and hardware.
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
\subsection{Morse code}
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
\newpage
\subsection{Sub-coarse-RTIO-cycle pulse}
With the use of the ARTIQ RTIO, only 1 event can be enqueued per coarse RTIO cycle, which is typically 8ns.
Therefore, to emit a pulse that is less than 8ns, additional delay is needed such that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted at different coarse RTIO cycles.
The TTL pulse must satisfy the minimum pulse width stated in the electircal specifications.
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
\subsection{Edge counting in a 1ms window}
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
The channel should be configured as input in both the gateware and hardware. Invoke one of the 3 methods to start edge detection.
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
The RTIO system can report at most 1 edge detection event for every coarse RTIO cycle.
For example, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is 1 coarse RTIO cycle (typically 8 ns) with consideration of the RTIO specification alone.
However, both the electircal specifications and the possibility of triggering \texttt{RTIOOverflow} should be considered.
\newpage
\subsection{Edge counting using \texttt{EdgeCounter}}
This example code uses the gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second.
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle.
Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
\subsection{Responding to an external trigger}
One channel needs to be configured as input, and the other as output.
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
\subsection{62.5 MHz clock signal generation}
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal.
Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle.
Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2. \\
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
\newpage
\subsection{Minimum Sustained Event Separation}
The minimum sustained event separation is the least amount of time separation between input gated events, in which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions.
The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
\begin{center}
\begin{table}[H]
\captionof{table}{Minimum sustained event separation of different carrier}
\centering
\begin{tabular}{|c|c|c|}
\hline
Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
Duration & 650 ns & 600 ns \\ \hline
\end{tabular}
\end{table}
\end{center}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\end{document}
Reference in New Issue View Git Blame Copy Permalink