from artiq.experiment import * class SineWave(EnvExperiment): def build(self): self.setattr_device("core") self.shuttler0_leds = ( [ self.get_device("shuttler0_led{}".format(i)) for i in range(2) ] ) self.setattr_device("shuttler0_config") self.setattr_device("shuttler0_trigger") self.shuttler0_dcbias = ( [ self.get_device("shuttler0_dcbias{}".format(i)) for i in range(16) ] ) self.shuttler0_dds = ( [ self.get_device("shuttler0_dds{}".format(i)) for i in range(16) ] ) self.setattr_device("shuttler0_relay") self.setattr_device("shuttler0_adc") @kernel def relay_init(self): self.shuttler0_relay.init() self.shuttler0_relay.enable(0x0000) @kernel def adc_init(self): delay_mu(int64(self.core.ref_multiplier)) self.shuttler0_adc.power_up() delay_mu(int64(self.core.ref_multiplier)) assert self.shuttler0_adc.read_id() >> 4 == 0x038d delay_mu(int64(self.core.ref_multiplier)) # The actual output voltage is limited by the hardware, # the calculated calibration gain and offset. # For example, if the system has a calibration gain of # 1.06, then the max output voltage = 10 / 1.06 = 9.43V. # Setting a value larger than 9.43V will result in overflow. self.shuttler0_adc.calibrate( self.shuttler0_dcbias, self.shuttler0_trigger, self.shuttler0_config) @kernel def shuttler_channel_reset(self, ch): self.shuttler0_dcbias[ch].set_waveform( a0=0, a1=0, a2=0, a3=0, ) self.shuttler0_dds[ch].set_waveform( b0=0, b1=0, b2=0, b3=0, c0=0, c1=0, c2=0, ) self.shuttler0_trigger.trigger(1 << ch) @kernel def run(self): self.core.reset() self.core.break_realtime() self.relay_init() self.adc_init() for i in range(16): self.shuttler_channel_reset(i) # To avoid RTIO Underflow delay(50*us) @kernel def sine(self): for i in range(2): self.shuttler0_dcbias[i].set_waveform( a0=0, a1=0, a2=0, a3=0, ) self.shuttler0_dds[i].set_waveform( b0=0x0FFF, b1=0, b2=0, b3=0, c0=0, c1=0x147AE148, # Frequency = 10MHz c2=0, ) self.shuttler0_trigger.trigger(0xFFFF)