\input{preamble.tex}
\graphicspath{{images/5432}{images}}

\title{5432 DAC Zotino}
\author{M-Labs Limited}
\date{January 2022}
\revision{Revision 2}
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

\begin{document}
\maketitle

\section{Features}

\begin{itemize}
\item{32-channel DAC}
\item{16-bits resolution}
\item{1 MSPS shared between all channels}
\item{Output voltage $\pm$10V}
\item{HD68 connector}
\item{Can be broken out to BNC/SMA/MCX}
\end{itemize}

\section{Applications}

\begin{itemize}
\item{Controlling setpoints of PID controllers for laser power stabilization}
\item{Low-frequency arbitrary waveform generation}
\item{Driving DC electrodes in ion traps}
\end{itemize}

\section{General Description}
The 5432 Zotino is a 4hp EEM module and part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.

It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.

% Switch to next column
\vfill\break

\begin{figure}[h]
    \centering
    \scalebox{0.88}{
    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]

        % HD68 Connector
        \draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};

        % IDC Connectors to IDC cards
        \draw (2.2, 1.2) node[twoportshape, t={\twocm{IDC}{DAC 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) {};
        \draw (1.4, 1.2) node[twoportshape, t={\twocm{IDC}{DAC 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) {};
        \draw (2.2, -1.2) node[twoportshape, t={\twocm{IDC}{DAC 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) {};
        \draw (1.4, -1.2) node[twoportshape, t={\twocm{IDC}{DAC 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) {};

        % Op-amp x32
        \draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};

        % DAC AD5372
        \draw (4.6, 0.2) node[twoportshape, t=\twocm{32-CH}{DAC}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (dac) {};

        % LVDS Transceivers
        \draw (6.6, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
        \draw (6.6, -1.6) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};

        % Aesthetic EEPROM
        \draw (6.6, 1.6) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eeprom) {};

        % EEMs from core device / controllers
        \draw (8.2, 0.0) node[twoportshape, t={EEM Port}, circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem_in) {};

        % Connect EEM IN to LVDS & EEMPROM
        \draw [latexslim-latexslim] (eeprom.north) -- (7.85, 1.6);
        \draw [latexslim-latexslim] (lvds0.north) -- (7.85, 0);
        \draw [latexslim-latexslim] (lvds1.north) -- (7.85, -1.6);

        % Connect LVDS to DAC
        \draw [latexslim-latexslim] (lvds0.south) -- (5.2, 0);
        \draw [latexslim-latexslim] (lvds1.south) -- (4.6, -1.6) -- (dac.south);

        % Connect DAC to Op-amp, label op-amp width x32
        \draw [-latexslim] (4, 0) -- (amp.west);
        \node [label=below:\tiny{Op-amp x32}] at (3.2, -0.2) {};
        \node [label=below:\tiny{1 per ch.}] at (3.2, -0.45) {};

        % Connect Op-amp to EEM OUT and HD68
        \draw [-latexslim] (amp.east) -- (hd68.east);
        \draw [-latexslim] (2.2, 0) -- (eem2.east);
        \draw [-latexslim] (1.4, 0) -- (eem3.east);
        \draw [-latexslim] (2.2, 0) -- (eem1.west);
        \draw [-latexslim] (1.4, 0) -- (eem0.west);

        % TEC Cooler on top of the DAC
        % To make it more obvious that it is cooling the DAC
        \draw (4.6, 1.45) node[twoportshape, t=\fourcm{TEC}{Cooler}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (tec_cooler) {};

        % TEC Controller lined up with EEM IN
        \draw (8.2, 3.5) node[twoportshape, t=\fourcm{TEC Controller}{Connector}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (tec_conn) {};

        % Thermistor for TEC controller
        \draw (6.6, 3.3) node[thermistorshape, scale=0.7, rotate=-90] (thermistor) {};
        \draw [latexslim-] (7.85, 3.3) -- (6.75, 3.3);

        % Connect the controller to the cooler
        \draw [-latexslim] (7.85, 4.2) -- (4.6, 4.2) -- (tec_cooler.north);

        % Thermal connection between DAC and thermistor
        \draw [densely dotted] (thermistor.south) -- (5.6, 3.3) -- (5.6, 0.5) -- (5.2, 0.5);

    \end{circuitikz}
    }

    \caption{Simplified Block Diagram}
\end{figure}


\begin{figure}[hbt!]
    \centering
    \includegraphics[height=2in]{photo5432.jpg}
    \caption{Zotino card photograph}
\end{figure}


\begin{figure}[hbt!]
    \centering
    \includegraphics[height=2.3in, angle=90]{Zotino_FP.jpg}
    \caption{Zotino front panel}
\end{figure}

% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn

\sourcesection{5432 DAC Zotino}{https://github.com/sinara-hw/Zotino/}

\section{Electrical Specifications}

% \hypersetup{hidelinks}
% \urlstyle{same}
These specifications are based on the datasheet of the DAC IC
(AD5372BCPZ\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}}),
and various information from the Sinara wiki\footnote{\label{zotino_wiki}\url{https://github.com/sinara-hw/Zotino/wiki}}.

\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Output Specifications}
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
    \thickhline
    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
    \textbf{Unit} & \textbf{Conditions} \\
    \hline
    Output voltage & -10 & & 10 & V & \\
    \hline
    Output impedance\repeatfootnote{zotino_wiki} & \multicolumn{4}{c|}{470 $\Omega$ $||$ 2.2nF} & \\
    \hline
    Resolution\repeatfootnote{dac} & & 16 & & bits & \\
    \hline
    3dB bandwidth\repeatfootnote{zotino_wiki} & & 75 & & kHz & \\
    \hline
    Power consumption\repeatfootnote{zotino_wiki} & 3 & & 8.7 & W & \\
    \thickhline
\end{tabularx}
\end{threeparttable}
\end{table}

The following table records the cross-talk and transient behavior of Zotino\footnote{\label{zotino21}\url{https://github.com/sinara-hw/Zotino/issues/21}}. In terms of output noise, measurements were made after a 15-cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF\footnote{\label{zotino27}\url{https://github.com/sinara-hw/Zotino/issues/27}}. DAC output during noise measurement was 3.5 V.

\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Electrical Characteristics}
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
    \thickhline
    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
    \textbf{Unit} & \textbf{Conditions / Comments} \\
    \hline
    DC cross-talk\repeatfootnote{zotino21}  & & -116 & & dB & \\
    \hline
    Fall-time\repeatfootnote{zotino21}  & & 18.5 & & $\mu$s & 10\% to 90\% fall-time \\
    & & 25 & & $\mu$s & 1\% to 99\% fall-time \\
    \hline
    Negative overshoot\repeatfootnote{zotino21}  & & 0.5\% & & - & \\
    \hline
    Rise-time\repeatfootnote{zotino21}  & & 30 & & $\mu$s & 1\% to 99\% rise-time \\
    \hline
    Positive overshoot\repeatfootnote{zotino21} & & 0.65\% & & - & \\
    \hline
    Output noise\repeatfootnote{zotino27} & & & & & \\
    \hspace{18mm} @ 100 Hz & & 500 & & nV/rtHz & 6.9 Hz bandwidth \\
    \hspace{18mm} @ 300 Hz & & 300 & & nV/rtHz & 6.9 Hz bandwidth \\
    \hspace{18mm} @ 50 kHz & & 210 & & nV/rtHz & 6.9 kHz bandwidth \\
    \hspace{18mm} @ 1 MHz & & 4.6 & & nV/rtHz & 6.9 kHz bandwidth \\
    \hspace{18mm} $>$ 4 MHz & & & 1 & nV/rtHz & 6.9 kHz bandwidth \\
    \thickhline
\end{tabularx}
\end{threeparttable}
\end{table}

\newpage

Step response was found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observing the waveform\repeatfootnote{zotino21}.

\begin{figure}[hbt!]
    \centering
    \subfloat[\centering Switching from -10V to +10V]{{
        \includegraphics[height=1.8in]{zotino_step_response_rising.png}
    }}%
    \subfloat[\centering Switching from +10V to -10V]{{
        \includegraphics[height=1.8in]{zotino_step_response_falling.png}
    }}%
    \caption{Step response}%
\end{figure}

Far-end crosstalk was measured using the following setup\repeatfootnote{zotino21}:

\begin{enumerate}
    \item CH1 as aggressor, CH0 as victim
    \item CH0, 2-7 terminated, CH 8-31 open
    \item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables and connectors.
\end{enumerate}

\begin{figure}[hbt!]
    \centering
    \includegraphics[width=3.3in]{zotino_fext.png}
    \caption{Step crosstalk}
\end{figure}

\newpage

\codesection{5432 DAC Zotino}

\subsection{Setting output voltage}
The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channels 0, 1, 2, and 3 respectively. Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.

\inputcolorboxminted{firstline=11,lastline=22}{examples/zotino.py}

\newpage

\subsection{Triangular wave}
Generates a triangular waveform at 10 Hz, 16 V peak-to-peak. Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.

Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.

\inputcolorboxminted{firstline=30,lastline=49}{examples/zotino.py}

\ordersection{5432 DAC Zotino}

\finalfootnote

\end{document}