WIP: 1125 Kasli-SoC #70
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Create 1125 Kasli-SoC datasheet, images directory, consolidate a large amount of shared core device sections into new
coredevice.txt
in ashared
folder. Adds 'System Description Entry' section to 1124 as well, otherwise changes to 1124 are minimal even though the diff is almost unreadable. PDFs attached.Only sections missing from 1125 are block diagram and electrical specifications, feedback is appreciated.
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Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
4 SFP 6Gb/s slots are provided. These can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the \mbox{DRTIO} master.
Kasli 1.0/1.1 is also supported.
I'd put it as
e.g. Kasli or another Kasli-SoC
(technically it's also compatible with kc705/zc706 but most users will not even see these boards)distributing commands
sounds a bit weird tooI assume that's for RTIO - that is, controlling the peripherals - and it's the primary function that should be put first.
and of course yes, it can distribute them (to further satellites) but it also adheres to the commands, but this time I don't know how to put it better
The idea was distributing commands [to the peripherals] as opposed to controlling them directly. Better like so?
'to the peripherals' clears it up nicely I think.
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\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
\cline{2-6}
% 100R termination & 100/350/600 mV differential input after the transformer.
& \multicolumn{3} {c|}{10/100/125} & MHz & RTIO clock synthesized from input \\
80MHz is also supported
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\section{Electrical Specifications}
% DATASHEET: https://docs.amd.com/v/u/en-US/ds190-Zynq-7000-Overview
Looking at Kasli 2.0's specs, they're the same for Kasli-SoC.
The kasli used the "DC and AC Switching Characteristics" instead of product overview datasheet, here's the Zynq-7000 version for that DS191
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\end{threeparttable}
\end{table}
Power is to be supplied through the barrel connector in the front panel, size 5.5 mm OD, 2.5 mm ID, and is passed on to daughtercards through the EEM connections. Locking barrel connectors are supported.
Alternatively, there's a Molex connector on the back of the card, to be used with the 1106 EEM AC Power Module. (also applies to Kasli 2.0)
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\cline{2-6}
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
\hline
Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
Power bricks we sell are 12V 5.43A already. And even that can be not enough if there's enough power hungry peripherals... that figure probably should be revisited at some point.
I.e. "12V, 5.43A" better here ...?
Actual value would be the theoretical maximum supported by the PCB (with maximum power draw from all the peripherals), and we haven't really calculated it. Nor that it matters.
I think it's OK to leave it as-is.
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\end{itemize}
\subsection{Downstream connection}
Kasli-SoC supports up to 4 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be freely used. On a master device, \texttt{SFP0} can also be used for a downstream connection, though some care is required with the enusing DRTIO destination numbers.
though some care is required with the enusing DRTIO destination numbers.
ensuring?
Not much care by default, I'd say - default routing table goes dest 1 - sfp0, dest 2 - sfp1 etc.;
"ensuing". but nvm, I entirely misread what I thought I was referencing.
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\item \textbf{Standalone/Master} \\
A network-connected Ethernet cable should be attached the front panel Ethernet port to enable communication with a host machine.
\item \textbf{Satellite} \\
Satellites must acquire an upstream connection to another satellite or the master. The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable connection with SFP transceivers.
cable (direct attach cable) or fiber connection
Only for SoC or in both sheets?
both
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\section{User LEDs}
Kasli-SoC designates two user LEDs for debugging purposes. Both are located on the PCB. The first, labeled \texttt{USER0}, can be found at the very bottom left of the PCB, below the SFP cage. The second, labeled \texttt{LD1}, can be found at the top left, roughly behind the micro-USB port.
is
LD1
available for the kernels anyway?A second LED is. I'm not 100% that this is LD1 but I thought that's what I remembered it being.
LD1 is a visual Loss of Lock indicator for Si5324:
The second USER LED is visible on the front panel, below the Ethernet port.
Oops. Got it. (That isn't marked on the FP diagram used in the shop, though.)
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\begin{itemize}
\item{RJ45 10/100/1000T Ethernet connector}
\item{4 SFP 6Gb/s slots for DRTIO}
The 6Gb/s bugs me even on the kasli datasheet, as the kasli fpga GTP transceiver max speed is around 6Gb/s but the DRTIO are running at 2.5Gb/s with 8b10b encoding. So if we are running this logic of using the max speed of the transceivers, the kasli-soc should be 12.5Gb/s. Though, I am not sure any SFP module support that kind of speed. (see https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/high-speed-serial.html for the MGT linerate)
Is having both numbers (current revision) better?
Yes.
Also the CoaXpress adapter will use the SFPs at maximum speed on SoC.
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\item{RJ45 10/100/1000T Ethernet connector}
\item{4 SFP 6Gb/s slots for DRTIO}
\item{12 EEM ports for daughtercards}
\item{Xilinx Zynq-7 SoC with Kintex-7 FPGA}
The product stack is called "Zynq 7000 Soc" (see https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-7000.html)
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\section{SoC}
Kasli-SoC features a XC7Z030 Xilinx Zynq-7000 System-on-Chip with a Kintex-7 FGPA and an Cortex-A9 dual-core processor to facilitate high-speed real-time control of inputs and outputs. The use of the SoC allows for more complex computations at higher speed than Kasli 2.0's purely on-FPGA CPU. Usually, the SoC is flashed with firmware and gateware binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with the ability to control other Sinara EEMs and run ARTIQ experiment kernels.
FYI the exact part number is XC7Z030-3FFG676E
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\section{Communication Interfaces}
Communication between core devices is implemented with 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on 1125 Kasli-SoC. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
I don't think we support SFP -> RJ45 on soc, maybe I am wrong
we don't
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\section{General Description}
The 1125 Kasli-SoC Carrier card is an 8hp EEM module, designed to run ARTIQ-Zynq kernels sent over the network from a host machine. Kasli-SoC is built around a Xilinx Zynq-7 SoC, allowing it to run more complex computations at high speed than its sister card 1124 Kasli 2.0. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections for comunications with other carriers. A dedicated Ethernet port is used for communications with the host.
Zynq-7000
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100 MHz & \texttt{int\char`_100} & internal crystal oscillator using PLL, 100 MHz output \\ \hline
\multirow{4}{*}{125 MHz} & \texttt{int\char`_125} & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_10to125} & external 10 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
ext0_synth0_80to125 is missing
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& \texttt{ext0\char`_synth0\char`_10to125} & external 10 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_125to125} & external 125 MHz reference using PLL, 125 MHz output \\ \hline
150 MHz & \texttt{int\char`_150} & internal crystal oscillator using PLL, 150 MHz output \\ \hline
150MHz was deprecated too
The jumper block isn't only for POR, there's a second jumper for sRST. Both need to be installed to use the builtin JTAG.
Should this also be noted when we suggest pulsing POR in the manual? Or am I misunderstanding?
518d38da65
to3bcff89526
On Kasli-SoC POR (and the built-in JTAG) will not work unless these jumpers are installed.
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