2245.tex

@@ -1,4 +1,4 @@
-\include{preamble.tex}
+\input{preamble.tex}
 \graphicspath{{images/2245}{images}}
 
 \usepackage{tikz-timing}
@@ -16,35 +16,28 @@
 \section{Features}
 
 \begin{itemize}
-\item{16 LVDS channels.}
-\item{Input and output capable.}
-\item{No galvanic isolation.}
-\item{High speed and low jitter.}
-\item{RJ45 connectors.}
+\item{16 LVDS-TTL channels.}
+\item{Input- and output-capable}
+\item{No galvanic isolation}
+\item{High speed and low jitter}
+\item{RJ45 connectors}
 \end{itemize}
 
 \section{Applications}
 
 \begin{itemize}
-\item{Photon counting.}
-\item{External equipment trigger.}
-\item{Optical shutter control.}
-\item{Serial communication to remote devices.}
+\item{Photon counting}
+\item{External equipment trigger}
+\item{Optical shutter control}
+\item{Serial communication with remote devices}
 \end{itemize}
 
 \section{General Description}
-The 2245 LVDS-TTL card is a 4hp EEM module.
-It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
 
-Each card provides sixteen digital channels each, controlled through 2 EEM connectors.
-Each EEM connector controls eight channels independently.
-Single EEM operation is possible.
-Each RJ45 connector exposes four digital channels in the LVDS format.
-The direction (input or output) of each channel can be selected using DIP switches.
-Outputs are intended to drive 100\textOmega~loads, inputs are 100\textOmega~terminated.
-This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
-Only shielded Ethernet Cat-6 cables should be connected.
+Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four digital channels in the LVDS format. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
 
+Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
 
 % Switch to next column
 \vfill\break
@@ -104,7 +97,7 @@ Only shielded Ethernet Cat-6 cables should be connected.
         \node at (1.8, -3.0)[circle,fill,inner sep=0.7pt]{};
 
         % Channel 15 repeaters
-        \draw (1.8, -3.4) node[twoportshape, t={\twocm{CH 15}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep15) {};     
+        \draw (1.8, -3.4) node[twoportshape, t={\twocm{CH 15}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep15) {};
 
         % Direction switches
         \draw (4.6, 0.4) node[twoportshape,t=\fourcm{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch0) {};
@@ -112,12 +105,12 @@ Only shielded Ethernet Cat-6 cables should be connected.
         \begin{scope}[xshift=5cm, yshift=0.65cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
             \draw (0.4, 0) to[short,-o](0.75, 0);
             \draw (0.78, 0)-- +(30: 0.46);
-            \draw (1.25, 0)to[short,o-](1.6, 0);   
+            \draw (1.25, 0)to[short,o-](1.6, 0);
         \end{scope}
         \begin{scope}[xshift=5cm, yshift=-0.15cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
             \draw (0.4, 0) to[short,-o](0.75, 0);
             \draw (0.78, 0)-- +(30: 0.46);
-            \draw (1.25, 0)to[short,o-](1.6, 0);   
+            \draw (1.25, 0)to[short,o-](1.6, 0);
         \end{scope}
 
         % I2C I/O expanders
@@ -303,9 +296,9 @@ Only shielded Ethernet Cat-6 cables should be connected.
 
 \begin{figure}[hbt!]
     \centering
-    \includegraphics[height=2.1in]{DIO_RJ45_FP.pdf}
-    \includegraphics[height=2.1in]{photo2245.jpg}
-    \caption{LVDS-TTL Card photo}
+    \includegraphics[angle=90, height=1.7in]{photo2245.jpg}
+    \includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
+    \caption{LVDS-TTL card and front panel}
 \end{figure}
 
 
@@ -313,9 +306,11 @@ Only shielded Ethernet Cat-6 cables should be connected.
 % page-by-page.
 \onecolumn
 
+\sourcesection{2245 LVDS-TTL}{https://github.com/sinara-hw/DIO_LVDS_RJ45/wiki}
+
 \section{Electrical Specifications}
 
-Information in this section is based on the datasheet of the repeaters IC (FIN1101K8X\footnote{\label{repeaters}https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}).
+All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
 
 \begin{table}[h]
 \begin{threeparttable}
@@ -336,9 +331,7 @@ Information in this section is based on the datasheet of the repeaters IC (FIN11
 \end{tabularx}
 \end{threeparttable}
 \end{table}
-The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
 
-All specifications are in the recommended operating temperature range unless otherwise noted.
 All typical values of DC specifications are at $T_A = 25\degree C$.
 
 \begin{table}[h]
@@ -349,7 +342,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
     \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
     \textbf{Unit} & \textbf{Conditions} \\
     \hline
-    Output differentiual Voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
+    Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
     \cline{0-5}
     $|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
     \cline{0-5}
@@ -359,7 +352,35 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
     \hline
     Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
     \hline
-    Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended Input Voltage \\
+    Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{AC Specifications}
+\begin{tabularx}{\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
+    (20\% to 80\%) & & & & &    \\
+    \cline{0-5}
+    Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
+    (80\% to 20\%) & & & & & \\
+    \cline{0-5}
+    Pulse width distortion & & 0.01 & 0.2 & ns & \\
+    \hline
+    LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
+    deterministic & & & & & 800 Mbps\\
+    \hline
+    LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
+    random (RMS) & & & & & \\
     \thickhline
 \end{tabularx}
 \end{threeparttable}
@@ -367,46 +388,18 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
 
 \newpage
 
-All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise specified.
-
-\begin{table}[h]
-\begin{threeparttable}
-\caption{AC Specifications}
-\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
-    \thickhline
-    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
-    \textbf{Unit} & \textbf{Conditions} \\
-    \hline
-    Differential Output Rise Time & \multirow{2}{*}{$t_{TLHD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & duty Cycle = 50\%.\\
-    (20\% to 80\%) & & & & & & \\
-    \cline{0-5}
-    Differential Output Fall Time & \multirow{2}{*}{$t_{THLD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
-    (80\% to 20\%) & & & & & & \\
-    \cline{0-5}
-    Pulse width distortion & $PWD$ & & 0.01 & 0.2 & ns & \\
-    \hline
-    LVDS data jitter, & \multirow{2}{*}{$t_{DJ}$} & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
-    deterministic & & & & & & 800 Mbps\\
-    \hline
-    LVDS clock jitter, & \multirow{2}{*}{$t_{RJ}$} & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
-    random (RMS) & & & & & & \\
-    \thickhline
-\end{tabularx}
-\end{threeparttable}
-\end{table}
-
 \section{Configuring IO Direction \& Termination}
-The IO direction can be configured by switches, which are found at the top of the card.
 \begin{multicols}{2}
-IO direction switches partly decides the IO direction of each bank.
+The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
 \begin{itemize}
     \itemsep0em
-    \item Closed switch (ON) \\
-          Fix the corresponding channel to output. The direction cannot be changed by I\textsuperscript{2}C.
-    \item Opened switch (OFF) \\
-          Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
+    \item IO direction switch closed (\texttt{ON}) \\
+          Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
+    \item IO direction switch open (OFF) \\
+          The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
 \end{itemize}
-\columnbreak
+
+\vspace*{\fill}\columnbreak
 \begin{center}
     \centering
     \includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
@@ -417,14 +410,12 @@ IO direction switches partly decides the IO direction of each bank.
 \newpage
 
 \section{Example ARTIQ code}
-The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
-They do not exhaustively demonstrate all the features of the ARTIQ system.
-The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
+\codesection{2245 LVDS-TTL card}
 
-Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
+Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
 
 \subsection{One pulse per second}
-The channel should be configured as output in both the gateware and hardware.
+The channel should be configured as output in both gateware and hardware.
 \inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
 
 \subsection{Morse code}
@@ -433,7 +424,7 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
 
 \newpage
 \subsection{Counting rising edges in a 1ms window}
-The channel should be configured as input in both the gateware and hardware.
+The channel should be configured as input in both gateware and hardware.
 \inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
 
 This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
@@ -459,8 +450,7 @@ One channel needs to be configured as input, and the other as output.
 
 \newpage
 \subsection{SPI Master Device}
-If a EEM port is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices.
-Invocation of an SPI transfer follows this pattern:
+If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
 \begin{enumerate}
     % The config register can be set using set_config.
     % However, the only difference between these 2 methods is that set_config accepts an arbitrary
@@ -493,7 +483,7 @@ The list of configurations supported in the gateware are listed as below:
     \end{tabular}
 \end{table}
 
-The following ARTIQ example demonstrates the flow of an SPI transcation with a typical SPI setup with 3 homogeneous slaves.
+The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves.
 The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
 \begin{center}
     \begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
@@ -572,19 +562,16 @@ The following examples will assume the SPI communication has the following prope
     \item Most significant bit (MSB) first
     \item Full duplex
 \end{itemize}
-The base line configuration for an \texttt{SPIMaster} instance can be defined as such:
+The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
 \inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
 The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
 
 \subsubsection{SPI frequency}
-Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor from [2, 257].
-In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
+Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
 \inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
 
 \subsubsection{SPI write}
-Typically, an SPI write operation involves sending an instruction and data to the SPI slaves.
-Suppose the instruction and data are 8 bits and 32 bits respectively.
-The timing diagram of such write operation is shown in the following.
+Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
 
 \begin{center}
 \begin{tikztimingtable}
@@ -605,11 +592,11 @@ The timing diagram of such write operation is shown in the following.
 \end{center}
 
 \newpage
-Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transcation can be performed by the following code.
+Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
 \inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
 
 \subsubsection{SPI read}
-A 32-bits read is represented by the following timing diagram.
+A 32-bit read is represented by the following timing diagram:
 
 \begin{center}
 \begin{tikztimingtable}
@@ -634,12 +621,8 @@ Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This S
 \inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
 
 \newpage
-\section{Ordering Information}
-To order, please visit \url{https://m-labs.hk} and select the 2245 LVDS-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
+\ordersection{2245 LVDS-TTL}
 
-\section*{}
-\vspace*{\fill}
-
-\input{footnote.tex}
+\finalfootnote
 
 \end{document}