1124 Carrier Kasli 2.0 update

@@ -228,0 +231,4 @@
+
+\section{FPGA}
+
+Kasli 2.0 features an XC7A100T-2FGG484I Xilink Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.

@@ -258,2 +271,2 @@
-An external reference can be supplied to synthesize the clock, which is supplied to the SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis.
-Kasli 2.0 supports a set of clock systhesizing options for the (D)RTIO system:
+\subsection{Standalone/Master}
+The RTIO clock is typically synthesized by the Si5324 clock multiplier and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors. Alternatively, an external reference can be supplied through the front panel SMA connector. It is then buffered in the PFGA and sent to the Si5324 for clock synthesis. Kasli 2.0 supports a set of RTIO clock options:

@@ -285,0 +299,4 @@
+
+\subsection{WRPLL}
+
+Kasli 2.0 can be configured to use WRPLL, a clock recovery method making use of White Rabbit's DDMTD (Digital Dual Mixer Time Difference) and the card's Si549 oscillator, both to lock the main RTIO clock and to lock satellite clocks to master.

@@ -228,0 +235,4 @@
+
+ARTIQ is open-source and can be found in the repository \url{https://github.com/m-labs/artiq}. Orders of Sinara hardware are normally accompanied with precompiled binaries. Long-term support for ARTIQ systems can also be purchased.
+
+A micro-USB located at the back of the Kasli 2.0 board is equipped for JTAG, I2C, and UART serial output.

@@ -285,0 +295,4 @@
+and rebooting.
+
+\subsection{Satellite}
+The RTIO clock is recovered from the SFP transceiver connected to the upstream device. The resulting signal is then cleaned by the Si5324 and routed to both the RTIO system and downstream satellites.

@@ -247,2 +261,2 @@
-    \item DRTIO Satellite \\
-    The \texttt{SFP0} port of DRTIO satellite should be connected to an appropriate SFP slot of the upstream core device (DRTIO master or satellite) with cable connection with SFP transceivers.
+    \item \textbf{Standalone/Master} \\
+    An Ethernet-capable SFP transceiver should be inserted into the \texttt{SFP0} slot. Typically, a 10000Base-X RJ45 SFP module is used, with an network-connected Ethernet cable attached to the module.

@@ -60,3 +56,1 @@
-Distributed Real Time Input/Output (DRTIO) system allows inclusion of
-additional core devices (e.g. Kasli 2.0) as DRTIO satellites,
-indirectly controlled by the DRTIO Master.
+4 SFP Gb/s slots are provided for Ethernet or DRTIO communications. Communication with a host machine is supported over Ethernet, while the Distributed Real-Time Input/Output (DRTIO) system allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the DRTIO master.

@@ -50,3 +51,2 @@
 \section{General Description}
-The 1124 Carrier Kasli 2.0 card is a 8hp EEM module.
-It controls the EEMs by running ARTIQ kernels sent from the host.
+The 1124 Kasli 2.0 Carrier card is an 8hp EEM module, designed to run ARTIQ kernels sent from a host machine over the network. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up to three SFP connections to satellite carriers.

@@ -234,2 +247,4 @@
+    Any other core devices in a DRTIO system are DRTIO satellites. They require an upstream connection to one other core device, master or satellite, through which communications will ultimately be chained to the master. They may make further downstream connections to other satellites. They may control RTIO channels through subkernels or simply pass on communications from the master.
 \end{enumerate}
 
+When run in a non-distributed ARTIQ configuration, with a single central core device but no satellites, that core device is instead known as \textbf{standalone.}

@@ -47,1 +46,3 @@
-\item{Communication with the host.}
+\item{Run ARTIQ kernels}
+\item{Communicate with the host}
+\item{Control other Sinara EEM cards}

@@ -199,0 +203,4 @@
+
+\section{FPGA}
+
+Kasli 2.0 features an XC7A100T-3FGG484E Xilink Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.

@@ -289,3 +308,2 @@
 \section{Ordering Information}
-To order, please visit \url{https://m-labs.hk} and select the 1124 Carrier Kasli 2.0 in the ARTIQ Sinara crate configuration tool.
-The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
+To order, please visit \url{https://m-labs.hk} and select 1124 Carrier Kasli 2.0 in the ARTIQ/Sinara crate configuration tool. Cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.