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1124.tex
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\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfigure}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usepackage{pifont}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{1124 Carrier Kasli 2.0}
\author{M-Labs Limited}
\date{January 2022}
\revision{Revision 1}
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
\begin{document}
\maketitle
\section{Features}
\begin{itemize}
\item{4 SFP 6Gb/s slots for Ethernet or DRTIO.}
\item{12 EEM Connectors.}
\item{4 MMCX clock outputs.}
\item{FPGA core device.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Runs ARTIQ kernels.}
\item{Control the EEMs.}
\item{Communication with the host.}
\end{itemize}
\section{General Description}
The 1124 Carrier Kasli 2.0 card is a 8hp EEM module.
It controls the EEMs by running ARTIQ kernels sent from the host.
It supports 12 EEM connections to other EEM cards in the ARTIQ Sinara family.
Real-time control of the EEMs are implemented using the RTIO system.
1ns temporal resolution can be achieved for TTL events.
4 SFP 6Gb/s slots are supported for Ethernet or DRTIO.
Communication with the host is supported by the Ethernet, while the
Distributed Real Time Input/Output (DRTIO) system allows inclusion of
additional core devices (e.g. Kasli 2.0) as DRTIO satellites,
indirectly controlled by the DRTIO Master.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{1.15}{
\begin{circuitikz}[european, every label/.append style={align=center}]
\begin{scope}[]
% Draw the FPGA
\draw (0, 0) node[twoportshape, t={FPGA}, circuitikz/bipoles/twoport/height=1.5, circuitikz/bipoles/twoport/width=1.2, scale=1] (fpga) {};
% External clock for RTIO, west of the FPGA
\draw [color=white, text=black] (-3.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (ext_clk) {};
\node [label=left:\tiny{EXT CLK}] at (-2.65, 0) {};
\begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=-40cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\draw [-latexslim] (ext_clk) -- (fpga.west);
% USB Mirco B port with USB-UART converter, north west of the FPGA
\draw (-3.2, 1.2) node[twoportshape, t={USB Micro B}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (usb) {};
\draw (-2, 1.2) node[twoportshape, t={\MymyLabel{USB-UART}{Converter}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (uart) {};
\draw [latexslim-latexslim] (usb.north) -- (uart.south);
\draw [latexslim-latexslim] (uart.north) -- (-1.3, 1.2) -- (-1.3, 0.4) -- (-0.85, 0.4);
% 4-SFP cage, south west of the FPGA
\draw (-3.4, -0.8) node[twoportshape, t={SFP 0}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp0) {};
\draw (-3, -0.8) node[twoportshape, t={SFP 1}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp1) {};
\draw (-3.4, -1.5) node[twoportshape, t={SFP 2}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp2) {};
\draw (-3, -1.5) node[twoportshape, t={SFP 3}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp3) {};
\draw [latexslim-latexslim] (-2.8, -1.15) -- (-2.2, -1.15) -- (-2.2, -0.4) -- (-0.85, -0.4);
% Clock signal cleaning path, south of the FPGA,
% clock signal loop from the south west to the south east
\draw (-0.8, -2.1) node[twoportshape, t={\MymyLabel{Clock}{Multiplier}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_mul) {};
\draw (0.8, -2.1) node[twoportshape, t={\MymyLabel{Clock}{Buffer}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_buf) {};
\draw [-latexslim] (-0.85, -0.8) -- (-1.6, -0.8) -- (-1.6, -1.9) -- (-1.05, -1.9);
% % A dashed path from EXT CLK to CDR CLK
\draw [dashed, -latexslim] (fpga.west) -- (-0.6, 0) -- (-0.6, -0.8) -- (-0.85, -0.8);
% % Internal oscillator for the RTIO clock
\draw (-2.2, -2.3) node[twoportshape, t={OSC}, circuitikz/bipoles/twoport/width=1, scale=0.5] (rtio_osc) {};
\draw [-latexslim] (rtio_osc.east) -- (-1.05, -2.3);
\draw [-latexslim] (clk_mul.north) -- (clk_buf.south);
\draw [-latexslim] (clk_buf.north) -- (1.6, -2.1) -- (1.6, -0.4) -- (0.85, -0.4);
% % MMCX output
\draw [color=white, text=black] (2.75, -1.05) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx0) {};
\draw [color=white, text=black] (2.75, -1.4) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx1) {};
\draw [color=white, text=black] (2.75, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx2) {};
\draw [color=white, text=black] (2.75, -2.1) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx3) {};
\node [label=right:\tiny{MMCX 0}] at (2.3, -1.05) {};
\node [label=right:\tiny{MMCX 1}] at (2.3, -1.4) {};
\node [label=right:\tiny{MMCX 2}] at (2.3, -1.75) {};
\node [label=right:\tiny{MMCX 3}] at (2.3, -2.1) {};
\begin{scope}[scale=0.07 , rotate=90, xshift=-30cm, yshift=-35cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=90, xshift=-25cm, yshift=-35cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=90, xshift=-20cm, yshift=-35cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\begin{scope}[scale=0.07 , rotate=90, xshift=-15cm, yshift=-35cm]
\draw (0,0.65) -- (0,3);
\clip (-1.5,0) rectangle (1.5,1.5);
\draw (0,0) circle(1.5);
\clip (-0.8,0) rectangle (0.8,0.8);
\draw (0,0) circle(0.8);
\end{scope}
\draw [-latexslim] (1.6, -1.05) -- (mmcx0);
\draw [-latexslim] (1.6, -1.4) -- (mmcx1);
\draw [-latexslim] (1.6, -1.75) -- (mmcx2);
\draw [-latexslim] (1.6, -2.1) -- (mmcx3);
% Memory modules, north of the FPGA
\draw (-0.55, 2.4) node[twoportshape, t={\MymyLabel{SPI}{Flash}}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (spi_flash) {};
\draw (0.55, 2.4) node[twoportshape, t={SDRAM}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (sdram) {};
\draw [latexslim-latexslim] (spi_flash.south) -- (-0.55, 1.05);
\draw [latexslim-latexslim] (sdram.south) -- (0.55, 1.05);
% EEM connectors x12, horizontally located at y=0.4
\draw (2, 1.8) node[twoportshape, t={EEM Port 0}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eem0) {};
\node at (2.4, 1.8)[circle,fill,inner sep=0.7pt]{};
\node at (2.6, 1.8)[circle,fill,inner sep=0.7pt]{};
\node at (2.8, 1.8)[circle,fill,inner sep=0.7pt]{};
\draw (3.2, 1.8) node[twoportshape, t={EEM Port 11}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eem11) {};
\draw [decorate, decoration = {brace}] (3.4, 1.1) -- (1.8, 1.1);
\draw [latexslim-latexslim] (2.6, 1) -- (2.6, 0.4) -- (0.85, 0.4);
\end{scope}
\end{circuitikz}
}
\caption{Simplified Block Diagram}
\end{figure}
\begin{figure}[hbt!]
\centering
\includegraphics[height=2in]{Kasli_FP.pdf}
\includegraphics[height=2in]{photo1124.jpg}
\caption{Kasli 2.0 Card photo}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\section{Electrical Specifications}
External clock parameters are derived based on the internal termination specified in UG471\footnote{\label{ug471}https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO},
and the voltage range specified in DS181\footnote{\label{ds181}https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}.
The figure had accounted for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}).
\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Clock input & & & & &\\
\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
\cline{2-6}
% 100R termination & 100/350/600 mV differential input after the transformer.
& \multicolumn{4}{c|}{10/100/125 MHz} & RTIO clock synthesized from input \\
\cline{2-6}
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
\hline
Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
\section{Distributed RTIO (DRTIO)}
DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central core device.
Multiple core devices (e.g. Kasli 2.0) can be interconnected through DRTIO. All core devices in the DRTIO system are classified as 1 of the 2 roles:
\begin{enumerate}
\item DRTIO Master \\
The DRTIO master is unique in a DRTIO system. It controls the DRTIO satellites(s) and local RTIO channels.
\item DRTIO Satellite \\
The rest of the core devices are DRTIO satellites. DRTIO satellites need an upstream connection to one other core devices (master or satellite).
It may provide downstream conenction to other DRTIO satellties.
\end{enumerate}
\section{Network Interface}
Communication between the host and the core device(s) is implemented using small form-factor pluggable (SFP) interfaces.
Approprate SFP transceivers must be plugged inside the corresponding SFP cages to enable communication between core devices.
\subsection{Upstream Connection}
A core device (e.g. Kasli 2.0) must acquire an upstream network connection through the \texttt{SFP0} slot.
\begin{itemize}
\item Standalone/DRTIO master \\
An Ethernet capable SFP transceiver must be inserted to the \texttt{SFP0} slot.
Typically, a RJ45 SFP module is inserted to the slot with an Ethernet cable with network connection attached to the module.
\item DRTIO Satellite \\
The \texttt{SFP0} port of DRTIO satellite should be connected to an appropriate SFP slot of the upstream core device (DRTIO master or satellite) with cable connection with SFP transceivers.
\end{itemize}
\subsection{Downstream Connection}
The 1124 Carrier Kasli 2.0 supports up to 3 DRTIO satellite connections per device.
DRTIO satellites can be connected using any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) through cable connections with SFP transceivers.
\section{Clock Routing}
\subsection{DRTIO Master/Standalone}
The RTIO clock is typically synthesized by the Si5324 clock multiplier, and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors.
An external reference can be supplied to synthesize the clock, which is supplied to the SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis.
Kasli 2.0 supports a set of clock systhesizing options for the (D)RTIO system:
\begin{table}[H]
\centering
\begin{tabular}{|c|c|c|}
\hline
RTIO frequency & Configuration & Clock generation \\ \hline
100 MHz & \texttt{int\char`_100} & internal crystal oscillator using PLL, 100 MHz output \\ \hline
\multirow{4}{*}{125 MHz} & \texttt{int\char`_125} & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_10to125} & external 10 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
& \texttt{ext0\char`_synth0\char`_125to125} & external 125 MHz reference using PLL, 125 MHz output \\ \hline
150 MHz & \texttt{int\char`_150} & internal crystal oscillator using PLL, 150 MHz output \\ \hline
\end{tabular}
\end{table}
Alternatively, the clock synthesizer can be bypassed using the \texttt{ext0\char`_bypass} clocking option, where the RTIO clock is directly supplied to the SMA connector.
The resulting clock signal is then routed to both the RTIO system and downstream DRTIO satellites.
Clocking options should be configured by setting the value of the \texttt{rtio} key to the desired configuration through \texttt{artiq\char`_coremgmt}.
For example, the RTIO frequency is synthesized from the external 10 MHz from the SMA connector after issuing the following command.
\begin{minted}{bash}
artiq_coremgmt config write -s rtio ext0_synth0_10to125
\end{minted}
\subsection{DRTIO Satellite}
The RTIO clock is first recovered from the SFP transceiver connected to the upstream device. The signal is then cleaned by Si5324 clock synthesizer.
The resulting clock signal is then routed to the RTIO system and downstream DRTIO satellties.
\newpage
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the system extensions of the ARTIQ control system.
These extensions make use of the resources on 1124 Carrier Kasli 2.0.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\subsection{Direct Memory Access (DMA)}
Instead of directly emitting RTIO events, a sequence of RTIO events can be recorded in advance and stored in the local SDRAM.
The event sequence can be replayed at another specified timestamp at a higher speed compared to the CPU alone.
The following example records an LED blinking sequence, and replayed twice consecutively using \texttt{CoreDMA}.
\texttt{led0} blinked twice in this example.
\inputcolorboxminted{firstline=10,lastline=29}{examples/dma.py}
The stored waveform can be referenced and replayed in different kernels.
However, the waveform is no longer retrievable once core device is rebooted.
\newpage
\subsection{Dataset Manipulation with Core Device Cache}
Experiments may require values computed/found in previously executed kernels.
To avoid invoking an RPC/sacrificing the pre-computation in \texttt{prepare()} stage, data can be cached in the core device cache.
The following code snippets consists of 2 experiments, where the data from the first experiement is cached.
The same data is retrieved and printed as hexadecimal in the second experiment.
\inputcolorboxminted{firstline=9,lastline=16}{examples/cache.py}
\inputcolorboxminted{firstline=24,lastline=35}{examples/cache.py}
Similar to DMA, the cached data is no longer retrievable once the core device is rebooted.
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 1124 Carrier Kasli 2.0 in the ARTIQ Sinara crate configuration tool.
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

65
2118-2128.tex
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@ -559,43 +559,32 @@ Timing accuracy in the examples below is well under 1 nanosecond thanks to the A
The channel should be configured as output in both the gateware and hardware.
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
\subsection{Morse code}
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
\newpage
\subsection{Sub-coarse-RTIO-cycle pulse}
With the use of the ARTIQ RTIO, only 1 event can be enqueued per coarse RTIO cycle, which is typically 8ns.
Therefore, to emit a pulse that is less than 8ns, additional delay is needed such that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted at different coarse RTIO cycles.
The TTL pulse must satisfy the minimum pulse width stated in the electircal specifications.
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
\subsection{Edge counting in a 1ms window}
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
The channel should be configured as input in both the gateware and hardware. Invoke one of the 3 methods to start edge detection.
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
The RTIO system can report at most 1 edge detection event for every coarse RTIO cycle.
For example, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is 1 coarse RTIO cycle (typically 8 ns) with consideration of the RTIO specification alone.
However, both the electircal specifications and the possibility of triggering \texttt{RTIOOverflow} should be considered.
\inputcolorboxminted{firstline=88,lastline=92}{examples/ttl.py}
\newpage
\subsection{Edge counting using \texttt{EdgeCounter}}
This example code uses the gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second.
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle.
Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
\subsection{Morse code}
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
\subsection{Counting rising edges in a 1ms window}
The channel should be configured as input in both the gateware and hardware.
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
To count falling edges or both rising \& falling edges, use \texttt{gate\char`_falling()} or \texttt{gate\char`_both()}.
\newpage
\subsection{Responding to an external trigger}
One channel needs to be configured as input, and the other as output.
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
\subsection{62.5 MHz clock signal generation}
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal.
@ -603,27 +592,7 @@ Each channel has a phase accumulator operating on the RTIO clock, where it is in
Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2. \\
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
\newpage
\subsection{Minimum Sustained Event Separation}
The minimum sustained event separation is the least amount of time separation between input gated events, in which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions.
The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
\begin{center}
\begin{table}[H]
\captionof{table}{Minimum sustained event separation of different carrier}
\centering
\begin{tabular}{|c|c|c|}
\hline
Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
Duration & 650 ns & 600 ns \\ \hline
\end{tabular}
\end{table}
\end{center}
\inputcolorboxminted{firstline=100,lastline=103}{examples/ttl.py}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.

2
2238.tex
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@ -494,7 +494,7 @@ Both recommended operating conditions and electrical characteristics are based o
\hline
Low-level output current & $I_{OL}$ & & & 24 & mA \\
\hline
Input edge rate & $\frac{\Delta t}{\Delta V}$ & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
Input edge rate & $\frac{\Delta t}{\Delta V}$ & 0 & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
\thickhline
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\end{tabularx}

29
2245.tex
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@ -344,6 +344,27 @@ Only shielded Ethernet Cat-6 cables should be connected.
Information in this section is based on the datasheet of the repeaters IC (FIN1101K8X\footnote{\label{repeaters}https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}).
The Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Other specifications should be met without exception.
\begin{table}[h]
\begin{threeparttable}
\caption{Absolute Maximum Ratings}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
LVDS DC input voltage & $V_{IN}$ & -0.5 & & 4.6 & V \\
\hline
LVDS DC output voltage & $V_{OUT}$ & -0.5 & & 4.6 & V \\
\hline
Continuous Short Circuit Current & $I_{OSD}$ & & 10 & & mA \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
\begin{table}[h]
\begin{threeparttable}
\caption{Recommended Input Voltage}
@ -355,10 +376,6 @@ Information in this section is based on the datasheet of the repeaters IC (FIN11
Magnitude of differential input & $|V_{ID}|$ & 0.1 & & 3.3 & V \\
\hline
Common mode input & $V_{IC}$ & $|V_{ID}|/2$ & & $3.3-|V_{ID}|/2$ & V \\
\hline
Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
\hline
Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
\thickhline
\end{tabularx}
\end{threeparttable}
@ -376,6 +393,10 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
\hline
Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
\hline
Output differentiual Voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
\cline{0-5}
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\

8
4410-4412.tex
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@ -702,8 +702,8 @@ The reported values are obtained from the oscilloscope.
\end{multicols}
The ideal RMS voltage is described by the linear function $V_\mathrm{rms,ideal}(\mathrm{ASF})=\frac{V_\mathrm{rms}(0.1)}{0.1}*\mathrm{ASF}$.
The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\mathrm{rms,ideal}(1)$) is shown below.
The expected RMS voltage is described by the linear function $V_\mathrm{rms,exp}(\mathrm{ASF})=\frac{V_\mathrm{rms}(0.1)}{0.1}*\mathrm{ASF}$.
The measured RMS voltage divided by the full scale expected RMS voltage (i.e. $V_\mathrm{rms,exp}(1)$) is shown below.
\begin{figure}[H]
\centering
@ -767,11 +767,11 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
(0, 0) (0.1, 16.6691) (0.2, 33.3762) (0.3, 49.8844) (0.4, 67.055) (0.5, 83.652)
(0.6, 99.970) (0.7, 116.906) (0.8, 133.368) (0.9, 150.839) (1.0, 167.033)
};
\legend{Ideal response, 0dB attenuation, 5dB attenuation, 10dB attenuation, 15dB attenuation}
\legend{Expected response, 0dB attenuation, 5dB attenuation, 10dB attenuation, 15dB attenuation}
\end{axis}
\end{tikzpicture}
\caption{RMS voltage scaled by ideal voltage at ASF=1, 100 MHz}
\caption{RMS voltage scaled by expected voltage at ASF=1, 100 MHz}
\end{figure}
\newpage

18
5108.tex
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@ -314,7 +314,7 @@ However, the sample rate in practice is typically limited by the use of ARTIQ-Py
\hline
Resolution &\multicolumn{4}{c|}{16 bits}& \\
\thickhline
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage magnitude must not exceed 5V.}
\multicolumn{6}{l}{*At 1x gain with 50\textOmega~termination enabled, the input voltage magnitude must not exceed 5V.}
\end{tabularx}
\end{threeparttable}
\end{table}
@ -340,14 +340,14 @@ The electrical characteristics are based on various test results\footnote{\label
& & 90 & & kHz & 1000x gain \\
\hline
Noise\repeatfootnote{sampler2} & & & & & 83.33 kHz sampling rate \\
\hspace{18mm} 1x gain & & 1.78 & & LSB RMS & Termination on \\
& & 1.75 & & LSB RMS & Termination off \\
\hspace{18mm} 10x gain & & 1.84 & & LSB RMS & Termination on \\
& & 3.09 & & LSB RMS & Termination off \\
\hspace{18mm} 100x gain & & 3.47 & & LSB RMS & Termination on \\
& & 26.02 & & LSB RMS & Termination off \\
\hspace{18mm} 1000x gain & & 13.87 & & LSB RMS & Termination on \\
& & 206.3 & & LSB RMS & Termination off \\
\hspace{18mm} 1x gain & & 1.78 & & LSB & Termination on \\
& & 1.75 & & LSB & Termination off \\
\hspace{18mm} 10x gain & & 1.84 & & LSB & Termination on \\
& & 3.09 & & LSB & Termination off \\
\hspace{18mm} 100x gain & & 3.47 & & LSB & Termination on \\
& & 26.02 & & LSB & Termination off \\
\hspace{18mm} 1000x gain & & 13.87 & & LSB & Termination on \\
& & 206.3 & & LSB & Termination off \\
% \hline
DC cross-talk\repeatfootnote{sinara226} & & & -96 & dB & 1x gain\\
\hline

20
7210.tex
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@ -35,7 +35,7 @@
\item{Distribute a low jitter clock signal.}
\item{SMA \& MMCX clock input.}
\item{4 SMA \& 6 MMCX output.}
\item{\textless100 fs RMS clock jitter.}
\item{\textless100 fs clock jitter.}
\end{itemize}
\section{Applications}
@ -46,13 +46,12 @@
\item{Drive clocks input for:\begin{itemize}
\item{4410/4412 DDS Urukul}
\item{4456 Synthesizer Mirny}
\item{4624 Phaser}
\end{itemize}}
\end{itemize}
\section{General Description}
The 7210 Clocker card is a 4hp EEM module.
It distrubites clock signal with \textless100 fs RMS jitter.
It distrubites clock signal with \textless100 fs jitter.
Clock input can be supplied to Clocker through the external SMA connector or the internal MMCX connector.
The input source can be selected using an SPDT switch.
@ -262,7 +261,7 @@ Otherwise, connect it to a carrier card (1124 Kasli or 1125 Kasli-SoC) using the
Specifications are derived based on the datasheets of
the clock buffer (ADCLK950BCPZ\footnote{\label{clock_buffer}https://www.analog.com/media/en/technical-documentation/data-sheets/ADCLK950.pdf}) \&
the RF transformer (TCM2-43X+\footnote{\label{rf_transformer}https://www.minicircuits.com/pdfs/TCM2-43X+.pdf}).
Clock output specifications is tested by supplying a 100 MHz DDS signal to the SMA input connector.\footnote{\label{clocker6}https://github.com/sinara-hw/Clocker/issues/6\#issuecomment-414048168}
Clock output specifications is tested by supplying a 100 MHz DDS signal to the SMA input connector.
The output is connected to an oscilloscope with 50\textOmega~termination.
\begin{table}[h]
@ -275,12 +274,14 @@ The output is connected to an oscilloscope with 50\textOmega~termination.
\textbf{Unit} & \textbf{Conditions} \\
\hline
Clock input\repeatfootnote{clock_buffer}\textsuperscript{,}\repeatfootnote{rf_transformer} & & & & & \\
\hspace{3mm} Peak-to-peak voltage & 0.40 & & 2.40 & V\textsubscript{p-p} & \\
\hspace{3mm} Differential peak-to-peak voltage & 0.40 & & 2.40 & V\textsubscript{p-p} & \\
\hspace{3mm} Frequency & 10 & & 4000 & MHz & \\
\hline
Clock output
Differential output
& & 0.8 & & V\textsubscript{p-p} & \multirow{3}{*}{50\textOmega~load, 100 MHz} \\
& & 5 & & dBm & \\
\cline{0-4}
Rise time (-200mV to 200mV) & & 415 & & ps & \\
\thickhline
\end{tabularx}
\end{threeparttable}
@ -289,9 +290,14 @@ The output is connected to an oscilloscope with 50\textOmega~termination.
\begin{figure}[H]
\centering
\includegraphics[width=5in]{clocker_waveform.png}
\caption{Waveform of Clocker at 100 MHz\repeatfootnote{clocker6}}
\caption{Waveform of Clocker at 100 MHz}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=5in]{clocker_rise_time.png}
\caption{Rising Edge of Clocker at 100 MHz}
\end{figure}
\newpage
\section{Selecting Clock Source}

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35
examples/cache.py
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@ -1,35 +0,0 @@
from artiq.experiment import *
class CachePut(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("core_cache")
@kernel
def put(self, key, value):
self.core_cache.put(key, value)
# First experiment
@kernel
def run(self):
self.put("data", [0xCAFE, 0xDEAD, 0xBEEF])
class CacheGet(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("core_cache")
@kernel
def get(self, key):
return self.core_cache.get(key)
@rpc(flags={"async"})
def p(self, p):
print([hex(_) for _ in p])
# Second experiment
@kernel
def run(self):
self.p(self.get("data"))

29
examples/dma.py
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@ -1,29 +0,0 @@
from artiq.experiment import *
class DMA(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("core_dma")
self.setattr_device("led0")
@kernel
def record(self):
with self.core_dma.record("led_blink"):
delay(100*ms)
self.led0.on()
delay(100*ms)
self.led0.off()
@kernel
def playback(self, n):
handle = self.core_dma.get_handle("led_blink")
self.core.break_realtime()
for _ in range(n):
self.core_dma.playback_handle(handle)
@kernel
def run(self):
self.core.reset()
self.record()
self.playback(2)

28
examples/ttl.py
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@ -52,6 +52,34 @@ class SoftwareEdgeCount(EnvExperiment):
print(counts)
class EdgeCounter(EnvExperiment):
def build(self):
self.setattr_device("core")
self.edgecounter0 = self.get_device("ttl0_counter")
@kernel
def run(self):
self.core.reset()
self.edgecounter0.gate_rising(1*ms)
counts = self.edgecounter0.fetch_count()
print(counts)
class ExternalTrigger(EnvExperiment):
def build(self):
self.setattr_device("core")
self.ttlin = self.get_device("ttl0")
self.ttlout = self.get_device("ttl4")
@kernel
def run(self):
self.core.reset()
gate_end_mu = self.ttlin.gate_rising(5*ms)
timestamp_mu = self.ttlin.timestamp_mu(gate_end_mu)
at_mu(timestamp_mu + self.core.seconds_to_mu(10*ms))
self.ttlout.pulse(1*us)
class ShortPulse(EnvExperiment):
def build(self):
self.setattr_device("core")

98
examples/ttl_in.py
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@ -1,98 +0,0 @@
from artiq.experiment import *
class SoftwareEdgeCount(EnvExperiment):
def build(self):
self.setattr_device("core")
self.ttlin = self.get_device("ttl0")
self.ttlout = self.get_device("ttl7")
@kernel
def run(self):
self.core.reset()
gate_start_mu = now_mu()
# Start input gate & advance timeline cursor to gate_end_mu
gate_end_mu = self.ttlin.gate_rising(1*ms)
at_mu(gate_start_mu)
for _ in range(64):
self.ttlout.pulse(8*ns)
delay(8*ns)
counts = self.ttlin.count(gate_end_mu)
print(counts)
class EdgeCounter(EnvExperiment):
def build(self):
self.setattr_device("core")
self.edgecounter0 = self.get_device("ttl0_counter")
@kernel
def run(self):
self.core.reset()
self.edgecounter0.gate_rising(1*ms)
counts = self.edgecounter0.fetch_count()
print(counts)
class ExternalTrigger(EnvExperiment):
def build(self):
self.setattr_device("core")
self.ttlin = self.get_device("ttl0")
self.ttlout = self.get_device("ttl4")
@kernel
def run(self):
self.core.reset()
gate_end_mu = self.ttlin.gate_rising(5*ms)
timestamp_mu = self.ttlin.timestamp_mu(gate_end_mu)
at_mu(timestamp_mu + self.core.seconds_to_mu(10*ms))
self.ttlout.pulse(1*us)
import time
class MeanTimestampDuration(EnvExperiment):
def build(self):
self.setattr_device("core")
self.ttlin = self.get_device("ttl0")
self.ttlclk = self.get_device("ttl7")
@kernel
def get_timestamp_duration(self, pulse_num) -> TInt64:
self.core.break_realtime()
delay(1*ms)
gate_start_mu = now_mu()
# Start input gate & advance timeline cursor to gate_end_mu
gate_end_mu = self.ttlin.gate_rising(1*ms)
at_mu(gate_start_mu)
self.ttlclk.set_mu(0x800000)
delay(16*pulse_num*ns)
self.ttlclk.set_mu(0)
# Guarantee t0 > gate_end_mu
# Otherwise timestamp_mu may wait for pulses till gate_end_mu
rtio_time_mu = self.core.get_rtio_counter_mu()
sleep_mu = float(gate_end_mu - rtio_time_mu)
self.rpc_sleep(self.core.mu_to_seconds(sleep_mu))
t0 = self.core.get_rtio_counter_mu()
while self.ttlin.timestamp_mu(gate_end_mu) >= 0:
pass
t1 = self.core.get_rtio_counter_mu()
return t1 - t0
@rpc
def rpc_sleep(self, duration):
time.sleep(duration)
@kernel
def run(self):
self.core.reset()
t64 = self.get_timestamp_duration(64)
t8 = self.get_timestamp_duration(8)
print("Mean timestamp_mu duration:")
print(self.core.mu_to_seconds((t64 - t8)/((64 + 1) - (8 + 1))))

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7
shell.nix
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@ -2,7 +2,7 @@ let
pkgs = import <nixpkgs> {};
in
pkgs.mkShell {
buildInputs = [
buildInputs = with pkgs;[
#pkgs.texlive.combined.scheme-small
@ -39,6 +39,9 @@ in
# if available, just add it to the above list
})
];
python3
] ++ (with python3Packages; [
pygments
]);
}