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11
.gitignore
vendored
11
.gitignore
vendored
@ -1,11 +0,0 @@
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*.out
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*.aux
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*.fls
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*.fdb_latexmk
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_minted-*
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build
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result
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images/unsorted
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examples/unsorted
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76
1008.tex
76
1008.tex
@ -1,76 +0,0 @@
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\input{preamble.tex}
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\graphicspath{{images/1008}{images}}
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\title{1008 VHDCI Carrier}
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\author{M-Labs Limited}
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\date{January 2025}
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\revision{Revision 1}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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\begin{itemize}
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\item{8 channels}
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\item{8 internal EEM connectors}
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\item{2 external VHDCI connectors}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{Break out VHDCI to extension boards}
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\item{Carry signals over VHDCI between crates}
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\item{Low-cost alternative to DRTIO}
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\item{Adapter for certain KC705 ARTIQ systems}
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\end{itemize}
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\section{General Description}
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The 1008 VHDCI Carrier is a 4hp EEM module, part of the ARTIQ/Sinara family. It is a passive adapter card which converts VHDCI connections to or from EEM connections.
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The 1008 VHDCI Carrier is bidirectional; it can be driven by a core device carrier board, or can drive other cards.
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A pair of VHDCI Carrier cards can be paired with VHDCI SCSI-3 cables to carry EEM signals over short distances between crates. Depending on the application, this can serve as a simple, low-cost, low-latency alternative to multiple core devices and ARTIQ DRTIO.
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% Switch to next column
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\vfill\break
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%\begin{figure}[h]
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% \centering
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% \scalebox{1.15}{
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% \begin{circuitikz}[european, every label/.append style={align=center}]
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% \begin{scope}[]
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% % if applicable
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% \end{scope}
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% \end{circuitikz}
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% }
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% \caption{Simplified Block Diagram}
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%\end{figure}
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\begin{figure}[hbt!]
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\centering
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\includegraphics[height=2.5in]{photo1008.jpg}
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\caption{VHDCI Carrier card}
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\includegraphics[height=2.5in, angle=90]{fp1008.pdf}
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\caption{VHDCI Carrier front panel}
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\end{figure}
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% For wide tables, a single column layout is better. It can be switched
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% page-by-page.
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\onecolumn
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\sourcesection{1008 VHDCI Carrier}{https://github.com/sinara-hw/VHDCI_Carrier}
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\section{Power}
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Power supply is required when driving EEM cards. 12V should be supplied through barrel jacks (2.50 mm ID, 5.50 mm OD) either in front panel or at back of card.
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\ordersection{1008 VHDCI Carrier}
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\finalfootnote
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\end{document}
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97
1106.tex
97
1106.tex
@ -1,97 +0,0 @@
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\input{preamble.tex}
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\graphicspath{{images/1106}, {images}}
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\title{1106 EEM AC Power Module}
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\author{M-Labs Limited}
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\date{January 2025}
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\revision{Revision 1}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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\begin{itemize}
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\item{Front panel IEC inlet}
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\item{80-264V input range}
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\item{Five 4-pin Molex MiniFit outputs}
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\item{EMC filter}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{Power supply for ARTIQ/Sinara systems}
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\item{Provides 400W at 25CFM cooling, 200W with free air convection}
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\end{itemize}
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\section{General Description}
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The 1106 EEM AC Power Module is a 8hp EEM form factor module, part of the ARTIQ/Sinara family. It serves as an in-crate power supply to other Sinara cards such as 1124 Carrier Kasli 2.0 and 1125 Carrier Kasli-SoC.
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The AC Power Module features universal IEC input in the front panel and five 4-pin Molex output, directly compatible with Kasli Carriers, at the very rear side of the module. The mains circuit is protected by a steel cover.
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% Switch to next column
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\vfill\break
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%\begin{figure}[h]
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% \centering
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% \scalebox{1.15}{
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% \begin{circuitikz}[european, every label/.append style={align=center}]
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% \begin{scope}[]
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% % if applicable
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% \end{scope}
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% \end{circuitikz}
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% }
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% \caption{Simplified Block Diagram}
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%\end{figure}
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\begin{figure}[hbt!]
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\centering
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\includegraphics[height=2.5in]{photo1106.jpg}
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\caption{EEM AC Power Module with handle}
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\includegraphics[height=2.5in, angle=90]{fp1106.pdf}
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\caption{EEM AC Power Module front panel}
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\end{figure}
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% For wide tables, a single column layout is better. It can be switched
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% page-by-page.
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\onecolumn
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\sourcesection{1106 EEM AC Power Module}{https://github.com/sinara-hw/EEM_PWR_MOD_AC}
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\section{Electrical Specifications}
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Specifications of parameters are based on the datasheet of the EPP-400-12 power supply\footnote{\url{https://www.meanwell.com/upload/pdf/EPP-400/EPP-400-SPEC.PDF}}.
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\begin{table}[h]
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\centering
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\begin{threeparttable}
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\caption{Electrical Specifications}
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||||
\begin{tabularx}{0.75\textwidth}{l | c c c | c | X}
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||||
\thickhline
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||||
\textbf{Parameter} & \textbf{Min} & \textbf{Typ.} & \textbf{Max} & \textbf{Unit} & \textbf{Conditions} \\
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||||
\hline
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||||
Output voltage & & 12 & & V & \\ \hline
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\multirow{2}{*}{Rated current} & & 33.3 & & \multirow{2}{*}{A} & 25CFM forced cooling \\ \cline{2-4}
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& & 20.8 & & & Convection \\ \hline
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\multirow{2}{*}{Rated power} & & 399.6 & & \multirow{2}{*}{W} & 25CFM forced cooling \\ \cline{2-4}
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& & 249.6 & & & Convection \\ \hline
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Input voltage & 80 & & 264 & VAC & \\ \hline
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Input frequency range & 47 & & 63 & Hz & \\ \hline
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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\section{Indicator LEDs}
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The 1106 EEM AC Power Module features several indicator LEDs. Four serve as current indicators signaling 25\%, 50\%, 75\% and 100\% load. \texttt{12V} LED signals power on. Additional \texttt{OVERTEMP} LED signals overtemp or overload.
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\ordersection{1106 EEM AC Power Module}
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\finalfootnote
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\end{document}
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245
1124.tex
245
1124.tex
@ -1,11 +1,30 @@
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\input{preamble.tex}
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\input{shared/coredevice.tex}
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\graphicspath{{images/1124}{images}}
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\documentclass[10pt]{datasheet}
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\usepackage{palatino}
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\usepackage{textgreek}
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\usepackage{minted}
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\usepackage{tcolorbox}
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\usepackage{etoolbox}
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\usepackage[justification=centering]{caption}
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\usepackage[utf8]{inputenc}
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\usepackage[english]{babel}
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\usepackage[english]{isodate}
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\usepackage{graphicx}
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\usepackage{subfigure}
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\usepackage{tikz}
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\usepackage{pgfplots}
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\usepackage{circuitikz}
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\usepackage{pifont}
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\usetikzlibrary{calc}
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\usetikzlibrary{fit,backgrounds}
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\title{1124 Carrier Kasli 2.0}
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\author{M-Labs Limited}
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\date{April 2025}
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\revision{Revision 3}
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\date{January 2022}
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\revision{Revision 1}
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||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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@ -14,32 +33,46 @@
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\section{Features}
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||||
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||||
\begin{itemize}
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\item{4 SFP 6Gb/s slots for Ethernet \& DRTIO at 2.5Gb/s}
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\item{12 EEM ports for daughtercards}
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\item{4 MMCX clock outputs}
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\item{Xilinx Artix-7 FPGA core}
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\item{DDR3 SDRAM}
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||||
\item{4 SFP 6Gb/s slots for Ethernet or DRTIO.}
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||||
\item{12 EEM Connectors.}
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\item{4 MMCX clock outputs.}
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||||
\item{FPGA core device.}
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||||
\end{itemize}
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||||
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||||
\section{Applications}
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||||
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\begin{itemize}
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\item{Run ARTIQ kernels}
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\item{Communicate with the host}
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\item{Control other Sinara EEM cards}
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\item{Distributed Real-Time I/O}
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\item{Runs ARTIQ kernels.}
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||||
\item{Control the EEMs.}
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\item{Communication with the host.}
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||||
\end{itemize}
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||||
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||||
\section{General Description}
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||||
The 1124 Kasli 2.0 Carrier card is an 8hp EEM module, designed to run ARTIQ kernels sent from a host machine over the network. It supports up to 12 EEM connections to other EEM cards in the ARTIQ/Sinara family and up four SFP connections, used for comunications with other carriers and/or Ethernet.
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||||
The 1124 Carrier Kasli 2.0 card is a 8hp EEM module.
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||||
It controls the EEMs by running ARTIQ kernels sent from the host.
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||||
Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
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||||
It supports 12 EEM connections to other EEM cards in the ARTIQ Sinara family.
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||||
Real-time control of the EEMs are implemented using the RTIO system.
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||||
1ns temporal resolution can be achieved for TTL events.
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||||
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||||
4 SFP 6Gb/s slots are provided. One may be used for Ethernet, which supports communication with a host machine. Remaining slots can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the \mbox{DRTIO} master.
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||||
4 SFP 6Gb/s slots are supported for Ethernet or DRTIO.
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||||
Communication with the host is supported by the Ethernet, while the
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||||
Distributed Real Time Input/Output (DRTIO) system allows inclusion of
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||||
additional core devices (e.g. Kasli 2.0) as DRTIO satellites,
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||||
indirectly controlled by the DRTIO Master.
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||||
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% Switch to next column
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\vfill\break
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\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
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\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
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||||
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
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||||
\newcommand{\inputcolorboxminted}[2]{%
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||||
\begin{tcolorbox}[colback=white]
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||||
\inputminted[#1, gobble=4]{python}{#2}
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||||
\end{tcolorbox}
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||||
}
|
||||
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||||
\begin{figure}[h]
|
||||
\centering
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||||
\scalebox{1.15}{
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@ -64,7 +97,7 @@
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||||
% USB Mirco B port with USB-UART converter, north west of the FPGA
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\draw (-3.2, 1.2) node[twoportshape, t={USB Micro B}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (usb) {};
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||||
\draw (-2, 1.2) node[twoportshape, t={\fourcm{USB-UART}{Converter}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (uart) {};
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||||
\draw (-2, 1.2) node[twoportshape, t={\MymyLabel{USB-UART}{Converter}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (uart) {};
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||||
\draw [latexslim-latexslim] (usb.north) -- (uart.south);
|
||||
\draw [latexslim-latexslim] (uart.north) -- (-1.3, 1.2) -- (-1.3, 0.4) -- (-0.85, 0.4);
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||||
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@ -77,8 +110,8 @@
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% Clock signal cleaning path, south of the FPGA,
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||||
% clock signal loop from the south west to the south east
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||||
\draw (-0.8, -2.1) node[twoportshape, t={\fourcm{Clock}{Multiplier}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_mul) {};
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||||
\draw (0.8, -2.1) node[twoportshape, t={\fourcm{Clock}{Buffer}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_buf) {};
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||||
\draw (-0.8, -2.1) node[twoportshape, t={\MymyLabel{Clock}{Multiplier}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_mul) {};
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||||
\draw (0.8, -2.1) node[twoportshape, t={\MymyLabel{Clock}{Buffer}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_buf) {};
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||||
\draw [-latexslim] (-0.85, -0.8) -- (-1.6, -0.8) -- (-1.6, -1.9) -- (-1.05, -1.9);
|
||||
% % A dashed path from EXT CLK to CDR CLK
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||||
\draw [dashed, -latexslim] (fpga.west) -- (-0.6, 0) -- (-0.6, -0.8) -- (-0.85, -0.8);
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||||
@ -131,7 +164,7 @@
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\draw [-latexslim] (1.6, -2.1) -- (mmcx3);
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||||
|
||||
% Memory modules, north of the FPGA
|
||||
\draw (-0.55, 2.4) node[twoportshape, t={\fourcm{SPI}{Flash}}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (spi_flash) {};
|
||||
\draw (-0.55, 2.4) node[twoportshape, t={\MymyLabel{SPI}{Flash}}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (spi_flash) {};
|
||||
\draw (0.55, 2.4) node[twoportshape, t={SDRAM}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (sdram) {};
|
||||
\draw [latexslim-latexslim] (spi_flash.south) -- (-0.55, 1.05);
|
||||
\draw [latexslim-latexslim] (sdram.south) -- (0.55, 1.05);
|
||||
@ -153,88 +186,144 @@
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=2in]{Kasli_FP.pdf}
|
||||
\includegraphics[height=2in]{photo1124.jpg}
|
||||
\caption{Kasli 2.0 card}
|
||||
\caption{Kasli 2.0 Card photo}
|
||||
\end{figure}
|
||||
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[angle=90,height=0.9in]{fp1124.jpg}
|
||||
\caption{Kasli 2.0 front panel}
|
||||
\end{figure}
|
||||
|
||||
% END PAGE ONE (for wide pages a single-column layout is preferable)
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{Kasli 2.0}{https://github.com/sinara-hw/Kasli}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
External clock parameters are derived based on the internal termination specified in UG471\footnote{\label{ug471}https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO},
|
||||
and the voltage range specified in DS181\footnote{\label{ds181}https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}.
|
||||
The figure had accounted for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}).
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Clock input & & & & &\\
|
||||
\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
|
||||
\cline{2-6}
|
||||
% 100R termination & 100/350/600 mV differential input after the transformer.
|
||||
& \multicolumn{4}{c|}{10/100/125 MHz} & RTIO clock synthesized from input \\
|
||||
\cline{2-6}
|
||||
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
|
||||
\hline
|
||||
Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
External clock parameters are derived based on the internal termination specified in
|
||||
UG471\footnote{\label{ug471}\url{https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO}}
|
||||
and the voltage range specified in
|
||||
DS181\footnote{\label{ds181}\url{https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
|
||||
\section{Distributed RTIO (DRTIO)}
|
||||
DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central core device.
|
||||
Multiple core devices (e.g. Kasli 2.0) can be interconnected through DRTIO. All core devices in the DRTIO system are classified as 1 of the 2 roles:
|
||||
\begin{enumerate}
|
||||
\item DRTIO Master \\
|
||||
The DRTIO master is unique in a DRTIO system. It controls the DRTIO satellites(s) and local RTIO channels.
|
||||
\item DRTIO Satellite \\
|
||||
The rest of the core devices are DRTIO satellites. DRTIO satellites need an upstream connection to one other core devices (master or satellite).
|
||||
It may provide downstream conenction to other DRTIO satellties.
|
||||
\end{enumerate}
|
||||
|
||||
\spectable
|
||||
|
||||
\section{FPGA}
|
||||
\section{Network Interface}
|
||||
Communication between the host and the core device(s) is implemented using small form-factor pluggable (SFP) interfaces.
|
||||
Approprate SFP transceivers must be plugged inside the corresponding SFP cages to enable communication between core devices.
|
||||
|
||||
Kasli 2.0 features an XC7A100T-3FGG484E Xilinx Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.
|
||||
\subsection{Upstream Connection}
|
||||
A core device (e.g. Kasli 2.0) must acquire an upstream network connection through the \texttt{SFP0} slot.
|
||||
\begin{itemize}
|
||||
\item Standalone/DRTIO master \\
|
||||
An Ethernet capable SFP transceiver must be inserted to the \texttt{SFP0} slot.
|
||||
Typically, a RJ45 SFP module is inserted to the slot with an Ethernet cable with network connection attached to the module.
|
||||
\item DRTIO Satellite \\
|
||||
The \texttt{SFP0} port of DRTIO satellite should be connected to an appropriate SFP slot of the upstream core device (DRTIO master or satellite) with cable connection with SFP transceivers.
|
||||
\end{itemize}
|
||||
|
||||
A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
|
||||
\subsection{Downstream Connection}
|
||||
The 1124 Carrier Kasli 2.0 supports up to 3 DRTIO satellite connections per device.
|
||||
DRTIO satellites can be connected using any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) through cable connections with SFP transceivers.
|
||||
|
||||
\artiqsection
|
||||
\section{Clock Routing}
|
||||
\subsection{DRTIO Master/Standalone}
|
||||
The RTIO clock is typically synthesized by the Si5324 clock multiplier, and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors.
|
||||
An external reference can be supplied to synthesize the clock, which is supplied to the SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis.
|
||||
Kasli 2.0 supports a set of clock systhesizing options for the (D)RTIO system:
|
||||
\begin{table}[H]
|
||||
\centering
|
||||
\begin{tabular}{|c|c|c|}
|
||||
\hline
|
||||
RTIO frequency & Configuration & Clock generation \\ \hline
|
||||
100 MHz & \texttt{int\char`_100} & internal crystal oscillator using PLL, 100 MHz output \\ \hline
|
||||
\multirow{4}{*}{125 MHz} & \texttt{int\char`_125} & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
|
||||
& \texttt{ext0\char`_synth0\char`_10to125} & external 10 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
|
||||
& \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
|
||||
& \texttt{ext0\char`_synth0\char`_125to125} & external 125 MHz reference using PLL, 125 MHz output \\ \hline
|
||||
150 MHz & \texttt{int\char`_150} & internal crystal oscillator using PLL, 150 MHz output \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
Alternatively, the clock synthesizer can be bypassed using the \texttt{ext0\char`_bypass} clocking option, where the RTIO clock is directly supplied to the SMA connector.
|
||||
The resulting clock signal is then routed to both the RTIO system and downstream DRTIO satellites.
|
||||
|
||||
\noteondrtio{Kasli 2.0}
|
||||
Clocking options should be configured by setting the value of the \texttt{rtio} key to the desired configuration through \texttt{artiq\char`_coremgmt}.
|
||||
For example, the RTIO frequency is synthesized from the external 10 MHz from the SMA connector after issuing the following command.
|
||||
\begin{minted}{bash}
|
||||
artiq_coremgmt config write -s rtio ext0_synth0_10to125
|
||||
\end{minted}
|
||||
|
||||
\section{Communication Interfaces}
|
||||
\subsection{DRTIO Satellite}
|
||||
The RTIO clock is first recovered from the SFP transceiver connected to the upstream device. The signal is then cleaned by Si5324 clock synthesizer.
|
||||
The resulting clock signal is then routed to the RTIO system and downstream DRTIO satellties.
|
||||
|
||||
Communication between devices is implemented using 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on the Kasli 2.0. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
|
||||
\newpage
|
||||
|
||||
Transceiver maximum speed is 6.6 Gb/s\footnote{\url{https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/high-speed-serial.html}}. DRTIO is normally run at 2.5 Gb/s with 8b10b encoding.
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the system extensions of the ARTIQ control system.
|
||||
These extensions make use of the resources on 1124 Carrier Kasli 2.0.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
\subsection{Upstream connection}
|
||||
\subsection{Direct Memory Access (DMA)}
|
||||
Instead of directly emitting RTIO events, a sequence of RTIO events can be recorded in advance and stored in the local SDRAM.
|
||||
The event sequence can be replayed at another specified timestamp at a higher speed compared to the CPU alone.
|
||||
The following example records an LED blinking sequence, and replayed twice consecutively using \texttt{CoreDMA}.
|
||||
\texttt{led0} blinked twice in this example.
|
||||
|
||||
A Kasli 2.0 board must acquire an upstream connection through the \texttt{SFP0} slot.
|
||||
\inputcolorboxminted{firstline=10,lastline=29}{examples/dma.py}
|
||||
|
||||
\begin{itemize}
|
||||
\item \textbf{Standalone/Master} \\
|
||||
An Ethernet-capable SFP transceiver should be inserted into the \texttt{SFP0} slot. Typically, a 10000Base-X RJ45 SFP module is used, with an network-connected Ethernet cable attached to the module.
|
||||
\item \textbf{Satellite} \\
|
||||
The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable or fibre connection with SFP transceivers.
|
||||
\end{itemize}
|
||||
The stored waveform can be referenced and replayed in different kernels.
|
||||
However, the waveform is no longer retrievable once core device is rebooted.
|
||||
|
||||
\subsection{Downstream connection}
|
||||
Kasli 2.0 supports up to 3 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be used. The destination on port \texttt{SFPn} normally receives the destination number \texttt{n}.
|
||||
\newpage
|
||||
|
||||
\clockingsection{Kasli 2.0}{FPGA}
|
||||
\subsection{Dataset Manipulation with Core Device Cache}
|
||||
Experiments may require values computed/found in previously executed kernels.
|
||||
To avoid invoking an RPC/sacrificing the pre-computation in \texttt{prepare()} stage, data can be cached in the core device cache.
|
||||
The following code snippets consists of 2 experiments, where the data from the first experiement is cached.
|
||||
The same data is retrieved and printed as hexadecimal in the second experiment.
|
||||
|
||||
\section{User LEDs}
|
||||
\inputcolorboxminted{firstline=9,lastline=16}{examples/cache.py}
|
||||
\inputcolorboxminted{firstline=24,lastline=35}{examples/cache.py}
|
||||
|
||||
Kasli 2.0 supplies three user LEDs for debugging purposes. Two are located on the front panel. The third is located on the PCB itself, beside the SFP cage. An additional ERR LED on the front panel is used by ARTIQ firmware to indicate a runtime panic.
|
||||
Similar to DMA, the cached data is no longer retrievable once the core device is rebooted.
|
||||
|
||||
\sysdescsection
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 1124 Carrier Kasli 2.0 in the ARTIQ Sinara crate configuration tool.
|
||||
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
An example description file for a system using 1124 Kasli 2.0 as a master core device might begin:
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
"target": "kasli",
|
||||
"variant": "my_variant",
|
||||
"hw_rev": "v2.0",
|
||||
"base": "master",
|
||||
"peripherals": [ ]
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
\coresysdesc
|
||||
|
||||
\coredevicecode{Kasli 2.0 1124 carrier}
|
||||
|
||||
\ordersection{1124 Carrier Kasli 2.0}
|
||||
|
||||
\finalfootnote
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
148
1125.tex
148
1125.tex
@ -1,148 +0,0 @@
|
||||
\input{preamble}
|
||||
\input{shared/coredevice}
|
||||
\graphicspath{{images/1125}{images}}
|
||||
|
||||
\title{1125 Carrier Kasli-SoC}
|
||||
\author{M-Labs Limited}
|
||||
\date{April 2025}
|
||||
\revision{Revision 2}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
\maketitle
|
||||
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{RJ45 10/100/1000T Ethernet connector}
|
||||
\item{4 SFP 12Gb/s slots for DRTIO at 2.5Gb/s}
|
||||
\item{12 EEM ports for daughtercards}
|
||||
\item{Xilinx Zynq-7000 SoC with Kintex-7 FPGA}
|
||||
\item{SD card flash memory}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Run ARTIQ kernels}
|
||||
\item{Communicate with the host}
|
||||
\item{Control other Sinara EEM cards}
|
||||
\item{Distributed Real-Time I/O}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
|
||||
The 1125 Kasli-SoC Carrier card is an 8hp EEM module, designed to run ARTIQ-Zynq kernels sent over the network from a host machine. Kasli-SoC is built around a Xilinx Zynq-7000 SoC, capable of running more complex computations at high speed than its sister card 1124 Kasli 2.0. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections for comunications with other carriers. A dedicated Ethernet port is used for communications with the host.
|
||||
|
||||
Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
|
||||
|
||||
4 SFP 12Gb/s slots are provided. These can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli or other Kasli-SoCs) as satellite cards, capable of running subkernels or relaying commands to a larger number of peripherals.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
% TODO, possibly: block diagram
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=3in]{photo1125.jpg}
|
||||
\caption{Kasli-SoC card}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[angle=90,height=1in]{fp1125.jpg}
|
||||
\caption{Kasli-SoC front panel}
|
||||
\end{figure}
|
||||
|
||||
% END PAGE ONE (for wide pages a single-column layout is preferable)
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{Kasli-SoC}{https://github.com/sinara-hw/Kasli-SOC/}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
External clock parameters are derived based on the internal termination specified in
|
||||
UG471\footnote{\label{ug471}\url{https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO}}
|
||||
and the voltage range specified in
|
||||
DS191\footnote{\label{ds191}\url{https://docs.amd.com/v/u/en-US/ds191-XC7Z030-XC7Z045-data-sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
|
||||
|
||||
\spectable
|
||||
|
||||
\section{SoC}
|
||||
|
||||
Kasli-SoC features a XC7Z030-3FFG676E Xilinx Zynq-7000 System-on-Chip with a Kintex-7 FGPA and an Cortex-A9 dual-core processor to facilitate high-speed real-time control of inputs and outputs. The use of the SoC allows for more complex computations at higher speed than Kasli 2.0's purely on-FPGA CPU. Usually, the SoC is flashed with firmware and gateware binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with the ability to control other Sinara EEMs and run ARTIQ experiment kernels.
|
||||
|
||||
A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
|
||||
|
||||
\artiqsection
|
||||
|
||||
ARTIQ-supported core devices based on Zynq-7000 SoCs, including Kasli-SoC, require firmware and gateware compiled from the ARTIQ-Zynq port, which can be found in the repository \url{https://git.m-labs.hk/M-Labs/artiq-zynq}.
|
||||
|
||||
\noteondrtio{Kasli-SoC}
|
||||
|
||||
\section{Communication Interfaces}
|
||||
|
||||
Communication between core devices is implemented with 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on 1125 Kasli-SoC. Each SFP connector possesses an indicator LED.
|
||||
|
||||
Transceiver maximum speed is 12.5 Gb/s\footnote{\url{https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/high-speed-serial.html}}. DRTIO is normally run at 2.5 Gb/s with 8b10b encoding.
|
||||
|
||||
Additionally, a RJ45 10/100/1000T Ethernet port is featured for network connection to a host machine.
|
||||
|
||||
\subsection{Upstream connection}
|
||||
|
||||
\begin{itemize}
|
||||
\item \textbf{Standalone/Master} \\
|
||||
A network-connected Ethernet cable should be attached the front panel Ethernet port to enable communication with a host machine.
|
||||
\item \textbf{Satellite} \\
|
||||
Satellites must acquire an upstream connection to another satellite or the master. The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable or fibre connection with SFP transceivers.
|
||||
\end{itemize}
|
||||
|
||||
\subsection{Downstream connection}
|
||||
Kasli-SoC supports up to 4 DRTIO satellite connections per device. Any of the 4 downstream SFP ports (i.e. \texttt{SFP0}, \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be freely used. Port \texttt{SFPn} normally receives the destination number \texttt{n + 1}.
|
||||
|
||||
\clockingsection{Kasli-SoC}{SoC}
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Configuring Boot Mode}
|
||||
|
||||
Kasli-SoC is capable of booting either remotely, over JTAG USB, or directly from the SD card. See the ARTIQ manual for more instructions on how to correctly flash and boot a core device. Boot mode must be configured by flipping physical switches on the board. The boot mode DIP switches are located in the middle of the board. To boot from USB, flip both switches towards the label \texttt{JTAG}. To boot from the SD card, flip both switches towards the label \texttt{SD}.
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=3in]{kasli_soc_dip_switches.jpg}
|
||||
\caption{Position of DIP switches, SD card, and reset pins}
|
||||
\end{figure}
|
||||
|
||||
\subsection{POR jumpers and POR reset}
|
||||
|
||||
A known Xilinx hardware bug prevents repeatedly booting over JTAG without a POR reset. If necessary, repeated boots can be made possible by physically setting jumpers on both the \texttt{PS\_POR\_B} and \texttt{PS\_SRST\_B} pins (marked in figure above) and triggering a reset over JTAG, see also the M-Labs POR reset script.\footnote{\url{https://git.m-labs.hk/M-Labs/zynq-rs/src/branch/master/kasli_soc_por.py}}
|
||||
|
||||
\section{User LEDs}
|
||||
|
||||
Kasli-SoC designates two user LEDs for debugging purposes. One is located on the PCB; it can be found at the very bottom left of the board, below the SFP cage, labeled \texttt{USER0}. The second is located on the front panel, besides the Ethernet port, labeled \texttt{L1}.
|
||||
|
||||
\sysdescsection
|
||||
|
||||
An example description file for a system using 1125 Kasli-SoC as a master core device might begin:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
"target": "kasli_soc",
|
||||
"variant": "my_variant",
|
||||
"hw_rev": "v1.0",
|
||||
"base": "master",
|
||||
"peripherals": [ ]
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
\coresysdesc
|
||||
|
||||
\coredevicecode{1125 Kasli-SoC carrier}
|
||||
|
||||
\ordersection{1125 Carrier Kasli-SoC}
|
||||
|
||||
\finalfootnote
|
||||
|
||||
\end{document}
|
||||
250
1550.tex
250
1550.tex
@ -1,250 +0,0 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images}, {images/1550}}
|
||||
|
||||
\title{1550 Laser Diode Driver Kirdy}
|
||||
\author{M-Labs Limited}
|
||||
\date{April 2025}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
\maketitle
|
||||
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{307.2 mA max output current, 20-bit resolution}
|
||||
\item{Low noise current source, 300 pA/rtHz @ 1 kHz}
|
||||
\item{Modulation input with DC-18 MHz bandwidth}
|
||||
\item{Monitor photodiode and LD protection}
|
||||
\item{Temperature controller with sub-mK stability}
|
||||
\item{Full digital control over Ethernet}
|
||||
\item{Bias-tee for RF modulation input}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Spectroscopy}
|
||||
\item{Laser cooling}
|
||||
\item{Atomic clocks}
|
||||
\item{Suitable for use with adapter and preinstalled laser assembly or with external laser heads}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
|
||||
The 1550 Laser Diode Driver Kirdy is an 8hp EEM module, part of the Sinara open hardware family. It serves as a precision laser diode driver, featuring a low-noise current source, low- and high-frequency modulation inputs, and full digital control over Ethernet. Soft start, laser power monitoring with a user-defined trip point, overtemperature protection, and a protection relay minimize the risk of damage to the laser diode.
|
||||
|
||||
1550 Kirdy supports both low-frequency modulation, suitable for laser locks and linewidth reduction, as well as RF modulation injected directly into the diode, typically to add sidebands to the optical output and implement stabilization schemes such as Pound-Drever-Hall and modulation transfer spectroscopy.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
%\begin{figure}[h]
|
||||
% \centering
|
||||
% \scalebox{1.15}{
|
||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
||||
% \begin{scope}[]
|
||||
% % if applicable
|
||||
% \end{scope}
|
||||
% \end{circuitikz}
|
||||
% }
|
||||
%
|
||||
% \caption{Simplified Block Diagram}
|
||||
%\end{figure}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=2.5in]{photo1550.jpg}
|
||||
\caption{Kirdy card photo}
|
||||
\includegraphics[height=3in, angle=90]{fp1550.pdf}
|
||||
\caption{Kirdy front panel}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{1550 Laser Diode Driver Kirdy}{https://git.m-labs.hk/sinara-hw/kirdy} The associated adapter can be found at the repository \url{https://git.m-labs.hk/sinara-hw/kirdyAdapter/src/branch/master}.
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
These specifications are based upon various information from the Sinara hardware repository\footnote{\label{repo}\url{https://git.m-labs.hk/sinara-hw/kirdy/}}.
|
||||
|
||||
\begin{table}[hbt!]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input power & & & & & \\
|
||||
\hspace{3mm} Voltage & & 12 & & V \\
|
||||
\hspace{3mm} Current & & & 2.0 & A & \\
|
||||
\hline
|
||||
LF modulation input\textdagger & & & & & \\
|
||||
\hspace{3mm} Voltage & -1 & & 1 & V \\
|
||||
\hspace{3mm} Bandwidth (-3 dB) & & 18 & & MHz & \\
|
||||
\hspace{3mm} Impedance & & 50 / 43.3k & & $\Omega$ & Termination switch on/off \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
1550 Kirdy supports Power-over-Ethernet, PoE+ (802.3at) and PoE (802.3af) standards. Alternatively, power can be provided via input in front panel. When using PoE, TEC output current should be limited to ±2A.
|
||||
|
||||
\begin{table}[hbt!]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Photodiode\textdagger & & & & & \\
|
||||
\hspace{3mm} Photocurrent range & 0 & & 3.0 & mA & \\
|
||||
\hspace{3mm} Photocurrent resolution & & 0.8 & & μA & \\
|
||||
\hspace{3mm} Bandwidth (-3 dB) & & 500 & & Hz & \\
|
||||
\hline
|
||||
Laser diode current driver & & & & & \\
|
||||
\hspace{3mm} Resolution & & 0.292 & & μA & \\
|
||||
\hspace{3mm} Control range & & & 307.2 & mA & \\
|
||||
\hspace{3mm} Current limit & & 319 & & mA & \\
|
||||
\hspace{3mm} Compliance & 4.928 & & & V & \\
|
||||
\hspace{3mm} Current noise @ 1 kHz & & & 300 & pA/rtHz & 300 mA DC bias, 10 $\Omega$ load \\
|
||||
\hspace{3mm} RMS noise @ 10 Hz-1 MHz & & & 300 & nA & 300 mA DC bias, 10 $\Omega$ load \\
|
||||
\hspace{3mm} Temp. coefficient & -1 & & +1 & ppm/°C & 50 mA DC bias, tested 43-56 °C \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\textdagger Circuit may be damaged if photodiode input current exceeds 3.0 mA. It is possible to modify the circuit and reprogram the photodiode current monitor range in the Kirdy driver.
|
||||
|
||||
\newpage
|
||||
|
||||
\begin{table}[hbt!]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Specifications, cont.}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\thickhline
|
||||
PID temperature controller & & & & & \\
|
||||
\hspace{3mm} Stability & & 1 & & mK & with Kirdy adapter, copper plate; \mbox{subject} to operating conditions \\
|
||||
\hline
|
||||
TEC output & & & & & \\
|
||||
\hspace{3mm} Resolution & & 22.9 & & μA & \\
|
||||
\hspace{3mm} Control range & -3.0 & & 3.0 & A & 12 V power, active cooling \\
|
||||
& -2.0 & & 2.0 & A & with PoE (802.3af) \\
|
||||
\hspace{3mm} Compliance & & 4.3 & & V & \\
|
||||
\hspace{3mm} Voltage reading resolution & & 3.22 & & mV & \\
|
||||
\hspace{3mm} Current reading resolution & & 2.9 & & mA & \\
|
||||
\hline
|
||||
TEC limits & & & & \\
|
||||
\hspace{3mm} Voltage limit range & 0 & & 4.3 & V & \\
|
||||
\hspace{3mm} Voltage limit resolution & & 3.14 & & mV & \\
|
||||
\hspace{3mm} Current limit range & -3.0 & & 3.0 & A & \\
|
||||
\hspace{3mm} Current limit resolution & & 1.57 & & mA & \\
|
||||
\hline
|
||||
NTC thermistor sensor & & & & \\
|
||||
\hspace{3mm} Resolution & & 0.01 & & mK & 10 k$\Omega$, B-constant 3950K, $T_{0}$ 25°C \\
|
||||
\hspace{3mm} Sampling rate & & 16.67 & $>$1000 & Hz & Subject to operating conditions \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\section{Modulation inputs}
|
||||
|
||||
1550 Kirdy supports two additional modulation inputs via SMA in the front panel, respectively \texttt{HF MOD} for high-frequency and \texttt{LF MOD} for low-frequency. LF modulation input can accept DC input to impose a DC offset on the output current. HF modulation input is AC-coupled and acts as a bias-tee.
|
||||
|
||||
The relationship of modulation input to output current is governed by the following equation:
|
||||
|
||||
\[I_{L} = max(I_{D} + U_{in} \cdot G_{mod}, 0)\]
|
||||
|
||||
where $I_{L}$ is the laser diode current, $I_{D}$ is the laser diode driver output current, $U_{in}$ is the input voltage, and $G_{mod}$ is the modulation gain. Care should be taken that $I_{L}$ always remains under the current limit. Otherwise, overcurrent protection may be triggered.
|
||||
|
||||
\newpage
|
||||
|
||||
Modulation gain is adjustable by DIP switch in top right of board. \textit{Exactly one} DIP switch should be enabled at all times. Enabling zero DIP switches may cause serious damage to the laser diode. Other configurations (multiple switches enabled) are invalid, but will not cause damage.
|
||||
|
||||
\begin{multicols}{2}
|
||||
|
||||
\centering
|
||||
\vspace*{10pt}
|
||||
\begin{tabular}{|l|c|}
|
||||
\hline
|
||||
\textbf{Switch} & \textbf{Setting} \\
|
||||
\thickhline
|
||||
1 & 25 mA/V \\
|
||||
2 & 2.5 mA/V \\
|
||||
3 & 0.25 mA/V \\
|
||||
\thickhline
|
||||
\end{tabular}
|
||||
\captionof{table}{DIP switch settings}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\centering
|
||||
\includegraphics[height=1.5in]{kirdy_mod_switch.jpg}
|
||||
\captionof{figure}{Position of DIP switch}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
|
||||
\section{Configuring termination}
|
||||
|
||||
LF modulation input termination must be configured by setting a physical switch on the board. The termination DIP switch is found at the upper left part of the board, behind the front panel. Turning this switch on adds a 50 $\Omega$ termination to the LF modulation input. Without the switch, the input impedance is approximately 43.4k $\Omega$.
|
||||
|
||||
\vspace*{20pt}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\centering
|
||||
\includegraphics[height=1.5in]{kirdy_imp_switch.jpg}
|
||||
\captionof{figure}{Position of DIP switch}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
|
||||
\section{Adapter and Laser Options}
|
||||
|
||||
An optional adapter allows compact lasers in butterfly packages to be mounted directly onto 1550 Kirdy, with a fibre-optic output in the front panel. Multiple single-frequency narrow-linewidth lasers are currently available as preinstalled options for order.
|
||||
|
||||
Alternatively, Kirdy accepts laser signals broken out to the front panel and is suitable for use in driving external laser heads, including commercial or custom ECDLs (with additional piezo driver not included with Kirdy) or injection-locked Fabry-Perot diodes.
|
||||
|
||||
\section{Firmware and driver}
|
||||
|
||||
1550 Kirdy features front panel Ethernet and USB-C. Either DFU or OpenOCD can be used to flash firmware; OpenOCD however requires a JTAG adapter.
|
||||
|
||||
Using M-Labs firmware, communication with a host system is performed over Ethernet/TCP in the form of predefined JSON objects. A Python driver implementing these can be found in the Kirdy firmware repo, hosted at \url{https://git.m-labs.hk/M-Labs/kirdy/}, under \texttt{pykirdy}. See inline documentation for descriptions of particular functions and implemented capabilities.
|
||||
|
||||
This driver may be used directly or through the Kirdy GUI, hosted in the same repo. To start the GUI, run the file \texttt{pykirdy/pykirdy/kirdy\_qt.py}, or install it using \texttt{pykirdy/pyproject.toml}. Users familiar with the Nix package manager through ARTIQ or for other reasons may note that the root of the repository includes a \texttt{flake.nix} with an appropriate development shell (e.g. \texttt{nix develop}) including all dependencies.
|
||||
|
||||
Examples in the \texttt{pykirdy} folder further demonstrate the use of the Kirdy driver, as well as the PID autotune temperature regulation feature.
|
||||
|
||||
\newpage
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[width=\textwidth]{kirdy_gui.jpg}
|
||||
\caption{Kirdy driver GUI}
|
||||
\end{figure}
|
||||
|
||||
To first connect to Kirdy, use the "Connect" button in the lower right corner and the IP address and port number assigned to Kirdy. By default, these are \texttt{192.168.1.128} and \texttt{1550} respectively. They can also be changed using commands supplied by the Python driver.
|
||||
|
||||
|
||||
\ordersection{1550 Laser Diode Driver Kirdy}
|
||||
|
||||
Kirdy can ship with a single-frequency narrow-linewidth laser pre-mounted and configured. Current wavelength options include 1270-1610 nm and 633-1064 nm. See the M-Labs hardware selection tool or contact M-Labs for prices and details.
|
||||
|
||||
\finalfootnote
|
||||
|
||||
\end{document}
|
||||
568
2118-2128.tex
568
2118-2128.tex
@ -1,10 +1,30 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/2118-2128}{images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfig}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usepackage{pifont}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\title{2118 BNC-TTL / 2128 SMA-TTL}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2022}
|
||||
\revision{Revision 3}
|
||||
\revision{Revision 2}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -13,34 +33,45 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{8 TTL channels}
|
||||
\item{Input- and output-capable}
|
||||
\item{Galvanically isolated}
|
||||
\item{3ns minimum pulse width}
|
||||
\item{BNC or SMA connectors}
|
||||
\item{8 channels.}
|
||||
\item{Input and output capable.}
|
||||
\item{Galvanically isolated.}
|
||||
\item{3ns minimum pulse width.}
|
||||
\item{BNC or SMA connectors.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Photon counting.}
|
||||
\item{External equipment trigger.}
|
||||
\item{Optical shutter control.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 2118 BNC-TTL card is a 8hp EEM module, while the 2128 SMA-TTL card is a 4hp EEM module.
|
||||
Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
Each card provides two banks of four digital channels each, with BNC (2118) or SMA (2128) connectors.
|
||||
Each bank has individual ground isolation.
|
||||
The direction (input or output) of each bank can be selected using DIP switches.
|
||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
|
||||
Outputs tolerate short circuits indefinitely.
|
||||
The card support a minimum pulse width of 3ns.
|
||||
|
||||
Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
||||
|
||||
Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely. Both cards are capable of a minimum pulse width of 3ns.
|
||||
|
||||
Isolated TTL cards are not well suited to low-noise or low-jitter applications due to interference from isolation components. For low-noise applications, use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
|
||||
\newcommand{\inputcolorboxminted}[2]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#1, gobble=4]{python}{#2}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{0.88}{
|
||||
@ -50,7 +81,7 @@
|
||||
|
||||
\draw[color=white, text=black] (-0.1,0) node[twoportshape,t={IO 0}, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (io0) {};
|
||||
\draw[color=white, text=black] (-0.1,-0.7) node[twoportshape,t={IO 1}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io1) {};
|
||||
\draw[color=white, text=black] (-0.1,-1.4) node[twoportshape,t={IO 2}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io2) {};
|
||||
\draw[color=white, text=black] (-0.1,-1.4) node[twoportshape,t={IO 2}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io2) {};
|
||||
\draw[color=white, text=black] (-0.1,-2.1) node[twoportshape,t={IO 3}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io3) {};
|
||||
|
||||
\node [label={[xshift=-0.18cm, yshift=-0.305cm]\tiny{IO 0}}] {};
|
||||
@ -58,7 +89,7 @@
|
||||
\node [label={[xshift=-0.18cm, yshift=-1.64cm]\tiny{IO 2}}] {};
|
||||
\node [label={[xshift=-0.18cm, yshift=-2.302cm]\tiny{IO 3}}] {};
|
||||
|
||||
% draw female SMA_0,1,2,3
|
||||
% draw female SMA_0,1,2,3
|
||||
\begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
|
||||
\draw (0,0.65) -- (0,3);
|
||||
\clip (-1.5,0) rectangle (1.5,1.5);
|
||||
@ -86,7 +117,9 @@
|
||||
\draw (0,0) circle(1.5);
|
||||
\clip (-0.8,0) rectangle (0.8,0.8);
|
||||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
\end{scope}
|
||||
|
||||
|
||||
|
||||
\draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus1) {};
|
||||
|
||||
@ -96,36 +129,36 @@
|
||||
\draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso4) {};
|
||||
\draw (3.05,-2.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso1) {};
|
||||
|
||||
\draw (4.5,-1.15) node[twoportshape,t=\fourcm{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds1) {};
|
||||
\draw (4.5,-1.15) node[twoportshape,t=\MymyLabel{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds1) {};
|
||||
|
||||
\draw (6.8,-0.9) -- ++(0.00001,0) node[twoportshape, anchor=left, t={EEM port}, circuitikz/bipoles/twoport/width=6, scale=0.6, rotate=-90] (kasli) {} ;
|
||||
\draw (0.8,-3.5) node[twoportshape,t=\fourcm{Per-bank \phantom{spac} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
|
||||
\draw (3.05,-3.5) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
|
||||
\draw (0.8,-3.5) node[twoportshape,t=\MymyLabel{Per-bank \phantom{spac} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
|
||||
\draw (3.05,-3.5) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
|
||||
|
||||
\draw (5.68,-2.3) node[twoportshape,t=EEPROM, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom) {};
|
||||
|
||||
\draw (0.8,-2.7) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
|
||||
\draw (0.8,-2.7) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
|
||||
|
||||
% Termination Switch 1,2,3,4
|
||||
\begin{scope}[xshift=0.9cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.2cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
\end{scope}
|
||||
@ -134,42 +167,42 @@
|
||||
\begin{scope}[xshift=1.2cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.32cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
\draw (0.8,-3.05) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
|
||||
\draw (0.8,-3.05) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
|
||||
|
||||
% Termination Switch 5,6,7,8
|
||||
\begin{scope}[xshift=0.9cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.2cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% channel 5,6,7,8
|
||||
\begin{scope}[yshift=-3.6cm]
|
||||
\draw[color=white, text=black] (-0.1,0) node[twoportshape,t={IO 4}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io4) {};
|
||||
\draw[color=white, text=black] (-0.1,-0.7) node[twoportshape,t={IO 5}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io5) {};
|
||||
\draw[color=white, text=black] (-0.1,-0.7) node[twoportshape,t={IO 5}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io5) {};
|
||||
\draw[color=white, text=black] (-0.1,-1.4) node[twoportshape,t={IO 6}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io6) {};
|
||||
\draw[color=white, text=black] (-0.1,-2.1) node[twoportshape,t={IO 7}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io7) {};
|
||||
|
||||
@ -206,7 +239,7 @@
|
||||
\draw (0,0) circle(1.5);
|
||||
\clip (-0.8,0) rectangle (0.8,0.8);
|
||||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
\end{scope}
|
||||
|
||||
|
||||
\draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus2) {};
|
||||
@ -217,7 +250,7 @@
|
||||
\draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso8) {};
|
||||
\draw (3.05,0.6) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso2) {};
|
||||
|
||||
\draw (4.5,-1.05) node[twoportshape,t=\fourcm{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds2) {};
|
||||
\draw (4.5,-1.05) node[twoportshape,t=\MymyLabel{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds2) {};
|
||||
|
||||
\end{scope}
|
||||
|
||||
@ -294,201 +327,312 @@
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=1.8in]{photo2118-2128.jpg }
|
||||
\caption{BNC-TTL and SMA-TTL cards}
|
||||
\includegraphics[angle=90, height=0.7in]{fp2118.jpg}
|
||||
\includegraphics[angle=90, height=0.4in]{fp2128.jpg}
|
||||
\caption{BNC-TTL and SMA-TTL front panels}
|
||||
\label{fig:example}
|
||||
\subfloat[\centering BNC-TTL]{{
|
||||
\includegraphics[height=1.8in]{DIO_BNC_FP.jpg}
|
||||
\includegraphics[height=1.8in]{photo2118.jpg}
|
||||
}}%
|
||||
\subfloat[\centering SMA-TTL]{{
|
||||
\includegraphics[height=1.8in]{DIO_SMA_FP.jpg}
|
||||
\includegraphics[height=1.8in]{photo2128.jpg}
|
||||
}}%
|
||||
\caption{BNC-TTL/SMA-TTL Card photos}%
|
||||
\label{fig:example}%
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesectiond{2118 BNC-TTL}{2128 SMA-TTL}{https://github.com/sinara-hw/DIO_BNC}{https://github.com/sinara-hw/DIO_SMA}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
|
||||
Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
|
||||
All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
|
||||
Specifications are based on the bus transceivers IC (SN74BCT25245DW\footnote{\label{transceiver}https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf})
|
||||
and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}).
|
||||
The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}https://github.com/sinara-hw/sinara/issues/187}.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
|
||||
\hline
|
||||
Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
|
||||
\hline
|
||||
Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
|
||||
\hline
|
||||
High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
|
||||
\hline
|
||||
Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
|
||||
\thickhline
|
||||
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
High-level input voltage\repeatfootnote{transceiver} & $V_{IH}$ & 2 & & 5.5* & V & \\
|
||||
\hline
|
||||
Low-level input voltage\repeatfootnote{transceiver} & $V_{IL}$ & -0.5 & & 0.8 & V & \\
|
||||
\hline
|
||||
Input clamp current\repeatfootnote{transceiver} & $I_{OH}$ & & & -18 & mA & termination disabled \\
|
||||
\hline
|
||||
High-level output current\repeatfootnote{transceiver} & $I_{OH}$ & & & -160 & mA & \\
|
||||
\hline
|
||||
Low-level output current\repeatfootnote{transceiver} & $I_{OL}$ & & & 376 & mA & \\
|
||||
\thickhline
|
||||
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
High-level output voltage\repeatfootnote{transceiver} & 2 & & & V & $I_{OH}$=-160mA \\
|
||||
& 2.7 & & & V & $I_{OH}$=-6mA \\
|
||||
\hline
|
||||
Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
|
||||
& & & 0.7 & V & $I_{OL}$=376mA \\
|
||||
\hline
|
||||
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
|
||||
\hline
|
||||
Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns & \\
|
||||
\hline
|
||||
Peak jitter\repeatfootnote{isolator} & & 350 & & ps & \\
|
||||
\hline
|
||||
Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
Low-jitter applications should note carefully the jitter introduced by the signal isolator. Noise is also introduced between the primary and secondary domains by the DC/DC converter. Where noise or jitter are crucial, it is instead recommended to use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
|
||||
|
||||
Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
|
||||
|
||||
\begin{figure}[ht]
|
||||
\centering
|
||||
\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
|
||||
\caption{Minimum pulse width required for BNC-TTL card}
|
||||
\label{fig:pulsewidth}
|
||||
\end{figure}
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
High-level output voltage\repeatfootnote{transceiver} & $V_{OH}$ & 2 & & & V & $I_{OH}$=-160mA \\
|
||||
& & 2.7 & & & V & $I_{OH}$=-6mA \\
|
||||
\hline
|
||||
Low-level output voltage\repeatfootnote{transceiver} & $V_{OL}$ & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
|
||||
& & & & 0.7 & V & $I_{OL}$=376mA \\
|
||||
\hline
|
||||
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & & 3 & 5 & ns & \\
|
||||
\hline
|
||||
Pulse width distortion\repeatfootnote{isolator} & $PWD$ & & 0.2 & 4.5 & ns & \\
|
||||
\hline
|
||||
Peak jitter\repeatfootnote{isolator} & $T_{JIT(PK)}$ & & 350 & & ps & \\
|
||||
\hline
|
||||
Data rate\repeatfootnote{isolator} & & 0 & & 150 & Mbps & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly.
|
||||
Minimum pulse width was measured\repeatfootnote{sinara187}.
|
||||
Pulses were generated from a DDS generator as an input of a BNC-TTL card.
|
||||
The input BNC-TTL card is connected to another BNC-TTL card as an output.
|
||||
The output signal is measured and shown.
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
|
||||
\caption{Minimum pulse width required for BNC-TTL card}
|
||||
\end{figure}
|
||||
|
||||
IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank.
|
||||
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\subfloat[\centering BNC-TTL]{{
|
||||
\includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
|
||||
}}%
|
||||
\subfloat[\centering SMA-TTL]{{
|
||||
\includegraphics[height=1.5in]{sma_ttl_switches.jpg}
|
||||
}}%
|
||||
\caption{Position of switches}%
|
||||
\end{figure}
|
||||
|
||||
\sysdescsection
|
||||
|
||||
2118 BNC-TTL and 2128 SMA-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
"name" : {
|
||||
"type": "dio",
|
||||
"board": "DIO_BNC", // or "DIO_SMA", optional
|
||||
"ports": [0],
|
||||
"edge_counter": true, // optional
|
||||
"bank_direction_low": "input", // or "output"
|
||||
"bank_direction_high": "output" // or "input"
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false.
|
||||
|
||||
\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
|
||||
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
The red trace refers to the input pulses from the DDS generator, while the blue trace is the measured signal from the output BNC-TTL card.
|
||||
Note that the first input (red) pulse could not propagate through the signal chain.
|
||||
The first output (blue) pulse is the result of the second input (red, 3ns width) pulse.
|
||||
|
||||
\newpage
|
||||
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
|
||||
\subsection{Sub-coarse-RTIO-cycle pulse}
|
||||
With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
|
||||
|
||||
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
|
||||
\subsection{Edge counting in a 1ms window}
|
||||
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
|
||||
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
|
||||
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
|
||||
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
|
||||
|
||||
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
|
||||
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
|
||||
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
|
||||
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
|
||||
|
||||
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
|
||||
|
||||
\newpage
|
||||
|
||||
\subsection{Edge counting using \texttt{EdgeCounter}}
|
||||
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
|
||||
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
|
||||
|
||||
\subsection{62.5 MHz clock signal generation}
|
||||
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
|
||||
|
||||
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
|
||||
|
||||
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
|
||||
\subsection{Minimum sustained event separation}
|
||||
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
|
||||
|
||||
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
|
||||
\section{Front Panel Drawings}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\begin{table}[H]
|
||||
\captionof{table}{Minimum sustained event separation of different carriers}
|
||||
\centering
|
||||
\begin{tabular}{|c|c|c|}
|
||||
\hline
|
||||
Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
|
||||
Duration & 650 ns & 600 ns \\ \hline
|
||||
\includegraphics[height=2.8in]{bnc_ttl_drawings.pdf}
|
||||
\captionof{figure}{2118 BNC-TTL front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.8in]{bnc_ttl_assembly.pdf}
|
||||
\captionof{figure}{2118 BNC-TTL front panel assembly}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (2118 Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90560220 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
|
||||
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
\end{center}
|
||||
|
||||
\ordersection{2118 BNC-TTL/2128 SMA-TTL}
|
||||
\columnbreak
|
||||
|
||||
\finalfootnote
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (2118 Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90457987 & 4 & CSCR M2.5*12.3 PAN PHL SS \\ \hline
|
||||
2 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
3 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
4 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
5 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
|
||||
6 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
|
||||
7 & 3207076 & 0.01 & SCR M2.5*16 PAN 100 21101-222 \\ \hline
|
||||
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
|
||||
9 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
|
||||
10 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT(100PCS) \\ \hline
|
||||
11 & 90560220 & 1 & FP-LYKJ 3U8HP PANEL \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=3in]{sma_ttl_drawings.pdf}
|
||||
\captionof{figure}{2128 SMA-TTL front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=3in]{sma_ttl_assembly.pdf}
|
||||
\captionof{figure}{2128 SMA-TTL front panel assembly}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (2128 Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90531967 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
|
||||
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (2128 Assembled)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90531967 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
|
||||
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
|
||||
5 & 3001012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
|
||||
6 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
7 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
|
||||
8 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
|
||||
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
The termination and IO direction can be configured by switches.
|
||||
The per-channel termination and per-bank IO direction switches are found at the middle-left and middle-right of both cards respectively.
|
||||
|
||||
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
|
||||
|
||||
IO direction switches partly decides the IO direction of each bank.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item Closed switch (ON) \\
|
||||
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item Opened switch (OFF) \\
|
||||
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\subfloat[\centering BNC-TTL]{{
|
||||
\includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
|
||||
}}%
|
||||
\subfloat[\centering SMA-TTL]{{
|
||||
\includegraphics[height=1.5in]{sma_ttl_switches.jpg}
|
||||
}}%
|
||||
\caption{Position of switches}%
|
||||
\end{figure}
|
||||
|
||||
\newpage
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 2118 BNC-TTL/2128 SMA-TTL card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
\subsection{Sub-coarse-RTIO-cycle pulse}
|
||||
With the use of the ARTIQ RTIO, only 1 event can be enqueued per coarse RTIO cycle, which is typically 8ns.
|
||||
Therefore, to emit a pulse that is less than 8ns, additional delay is needed such that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted at different coarse RTIO cycles.
|
||||
The TTL pulse must satisfy the minimum pulse width stated in the electircal specifications.
|
||||
|
||||
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
|
||||
|
||||
\subsection{Edge counting in a 1ms window}
|
||||
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
|
||||
The channel should be configured as input in both the gateware and hardware. Invoke one of the 3 methods to start edge detection.
|
||||
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
|
||||
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
|
||||
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
|
||||
The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
|
||||
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
|
||||
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
|
||||
|
||||
The RTIO system can report at most 1 edge detection event for every coarse RTIO cycle.
|
||||
For example, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is 1 coarse RTIO cycle (typically 8 ns) with consideration of the RTIO specification alone.
|
||||
However, both the electircal specifications and the possibility of triggering \texttt{RTIOOverflow} should be considered.
|
||||
|
||||
\newpage
|
||||
\subsection{Edge counting using \texttt{EdgeCounter}}
|
||||
This example code uses the gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
|
||||
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle.
|
||||
Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
|
||||
|
||||
\subsection{62.5 MHz clock signal generation}
|
||||
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal.
|
||||
Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle.
|
||||
Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2. \\
|
||||
|
||||
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
|
||||
|
||||
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
\subsection{Minimum Sustained Event Separation}
|
||||
The minimum sustained event separation is the least amount of time separation between input gated events, in which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions.
|
||||
The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
|
||||
|
||||
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
|
||||
|
||||
\begin{center}
|
||||
\begin{table}[H]
|
||||
\captionof{table}{Minimum sustained event separation of different carrier}
|
||||
\centering
|
||||
\begin{tabular}{|c|c|c|}
|
||||
\hline
|
||||
Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
|
||||
Duration & 650 ns & 600 ns \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
\end{center}
|
||||
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
352
2238.tex
352
2238.tex
@ -1,10 +1,29 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/2238}{images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfig}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\title{2238 MCX-TTL}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2022}
|
||||
\revision{Revision 3}
|
||||
\revision{Revision 2}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -13,32 +32,43 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{16 MCX-TTL channels}
|
||||
\item{Input and output capable}
|
||||
\item{No galvanic isolation}
|
||||
\item{High speed and low jitter}
|
||||
\item{MCX connectors}
|
||||
\item{16 channels.}
|
||||
\item{Input and output capable.}
|
||||
\item{No galvanic isolation.}
|
||||
\item{High speed and low jitter.}
|
||||
\item{MCX connectors.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Photon counting.}
|
||||
\item{External equipment trigger.}
|
||||
\item{Optical shutter control.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 2238 MCX-TTL card is a 4hp EEM module.
|
||||
It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
||||
|
||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||
Each card provides four banks of four digital channels each, with MCX connectors, controlled through 2 EEM connectors.
|
||||
Each EEM connector controls two banks independently.
|
||||
Single EEM operation is possible.
|
||||
The direction (input or output) of each bank can be selected using DIP switches.
|
||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
|
||||
This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\inputcolorboxminted}[2]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#1, gobble=4]{python}{#2}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{0.88}{
|
||||
@ -211,103 +241,103 @@
|
||||
\node[fill=white, scale=0.7, rotate=-90] at (bank3.west) {Bank 3};
|
||||
|
||||
% Draw bus transceivers
|
||||
\draw (3.25, -0.7) node[twoportshape,t=\fourcm{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus0) {};
|
||||
\draw (3.25, -5.6) node[twoportshape,t=\fourcm{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus1) {};
|
||||
\draw (3.25, -0.7) node[twoportshape,t=\MymyLabel{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus0) {};
|
||||
\draw (3.25, -5.6) node[twoportshape,t=\MymyLabel{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus1) {};
|
||||
|
||||
% Draw termination switches
|
||||
% Bus transceiver 0
|
||||
\draw (1.7, 1.2) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch0) {};
|
||||
\draw (1.7, 1.2) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch0) {};
|
||||
\begin{scope}[xshift=1.8cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.9cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=2.0cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=2.1cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% Bus transceiver 1
|
||||
\draw (1.5, -2.6) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
|
||||
\draw (1.5, -2.6) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
|
||||
\begin{scope}[xshift=1.6cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.7cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.8cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.9cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% Bus transceiver 2
|
||||
\draw (1.7, -3.7) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
|
||||
\draw (1.7, -3.7) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
|
||||
\begin{scope}[xshift=1.8cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.9cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=2cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=2.1cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% Bus transceiver 3
|
||||
\draw (1.5, -7.5) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch3) {};
|
||||
\draw (1.5, -7.5) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch3) {};
|
||||
\begin{scope}[xshift=1.6cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.7cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.8cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=1.9cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% Connection termination switches to each IO line
|
||||
% Connection termination switches to each IO line
|
||||
% IO 0, 2, 4, 6
|
||||
\draw [-] (1.4, 1) -- (1.4, 0.7);
|
||||
\draw [-] (1.6, 1) -- (1.6, 0);
|
||||
@ -354,39 +384,39 @@
|
||||
\draw [latexslim-latexslim] (mcx15) -- (2.9, -7);
|
||||
|
||||
% Draw LVDS transceivers
|
||||
\draw (5.05, -0.025) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds0) {};
|
||||
\draw (5.05, -1.675) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds1) {};
|
||||
\draw (5.05, -4.625) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds2) {};
|
||||
\draw (5.05, -6.275) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds3) {};
|
||||
\draw (5.05, -0.025) node[twoportshape,t={\MymyLabel{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds0) {};
|
||||
\draw (5.05, -1.675) node[twoportshape,t={\MymyLabel{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds1) {};
|
||||
\draw (5.05, -4.625) node[twoportshape,t={\MymyLabel{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds2) {};
|
||||
\draw (5.05, -6.275) node[twoportshape,t={\MymyLabel{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds3) {};
|
||||
|
||||
% Aesthetic EEPROM at each end of LVDS transceivers
|
||||
\draw (5.05, 1.1) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom0) {};
|
||||
\draw (5.05, -7.4) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom1) {};
|
||||
|
||||
% I/O expander
|
||||
\draw (6.65, -3.5) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
|
||||
\draw (6.65, -3.5) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
|
||||
|
||||
% I/O direction switches
|
||||
\draw (5.05, -2.8) node[twoportshape,t=\fourcm{Per-bank \phantom{space} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
|
||||
\draw (5.05, -2.8) node[twoportshape,t=\MymyLabel{Per-bank \phantom{space} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
|
||||
\begin{scope}[xshift=5.3cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=5.4cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=5.5cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=5.6cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% EEM Ports
|
||||
@ -437,159 +467,131 @@
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=1.8in]{DIO_MCX_FP.pdf}
|
||||
\includegraphics[height=2in]{photo2238.jpg}
|
||||
\caption{MCX-TTL card}
|
||||
\includegraphics[angle=90, height=0.5in]{fp2238.jpg}
|
||||
\caption{MCX-TTL front panel}
|
||||
\caption{MCX-TTL Card photo}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{2238 MCX-TTL}{https://github.com/sinara-hw/DIO_MCX/wiki}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
|
||||
Both recommended operating conditions and electrical characteristics are based on the datasheet of the bus transceivers IC (74LVT162245MTD\footnote{\label{transceiver}https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}).
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input voltage & 0 & & 5.5* & V \\
|
||||
\hline
|
||||
High-level output current & & & -24 & mA \\
|
||||
\hline
|
||||
Low-level output current & & & 24 & mA \\
|
||||
\hline
|
||||
Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
|
||||
\thickhline
|
||||
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input voltage & $V_{I}$ & 0 & & 5.5* & V \\
|
||||
\hline
|
||||
High-level output current & $I_{OH}$ & & & -24 & mA \\
|
||||
\hline
|
||||
Low-level output current & $I_{OL}$ & & & 24 & mA \\
|
||||
\hline
|
||||
Input edge rate & $\frac{\Delta t}{\Delta V}$ & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
|
||||
\thickhline
|
||||
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
|
||||
All specifications are in the recommended operating temperature range unless otherwise noted.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
|
||||
\hline
|
||||
Input high voltage & 2.0 & & & V & \\
|
||||
\hline
|
||||
Input low voltage & & & 0.8 & V & \\
|
||||
\hline
|
||||
Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
|
||||
& 3.1 & & & V & $I_{OH}=-200\mu A$ \\
|
||||
\hline
|
||||
Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
|
||||
& & & 0.2 & V & $I_{OL}=-200\mu A$ \\
|
||||
\hline
|
||||
Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
|
||||
& & & 2 & \textmu A & $V_I=3.3V$ \\
|
||||
& & & -10 & \textmu A & $V_I=0V$ \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input clamp diode voltage & $V_{IK}$ & & & -1.2 & V & $I_I =-36 mA$ \\
|
||||
\hline
|
||||
Input high voltage & $V_{IH}$ & 2.0 & & & V & \\
|
||||
\hline
|
||||
Input low voltage & $V_{IL}$ & & & 0.8 & V & \\
|
||||
\hline
|
||||
Output high voltage & $V_{OH}$ & 2.0 & & & V & $I_{OH}=-24mA$ \\
|
||||
& & 3.1 & & & V & $I_{OH}=-200\mu A$ \\
|
||||
\hline
|
||||
Output low voltage & $V_{OL}$ & & & 0.8 & V & $I_{OL}=-24mA$ \\
|
||||
& & & & 0.2 & V & $I_{OL}=-200\mu A$ \\
|
||||
\hline
|
||||
Input current & $I_I$ & & & 20 & \textmu A & $V_I=5.5V$ \\
|
||||
& & & & 2 & \textmu A & $V_I=3.3V$ \\
|
||||
& & & & -10 & \textmu A & $V_I=0V$ \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
The termination and IO direction can be configured by switches.
|
||||
The per-channel termination and per-bank IO direction switches are found at the top and middle of the card respectively.
|
||||
\begin{multicols}{2}
|
||||
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
|
||||
|
||||
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
|
||||
|
||||
\begin{multicols}{2}
|
||||
|
||||
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
|
||||
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\sysdescsection
|
||||
|
||||
2238 MCX-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "dio",
|
||||
"board": "DIO_MCX", // optional
|
||||
"ports": [0],
|
||||
"edge_counter": true, // optional
|
||||
"bank_direction_low": "input", // or "output"
|
||||
"bank_direction_high": "output" // or "input"
|
||||
},
|
||||
{
|
||||
"type": "dio",
|
||||
"board": "DIO_MCX",
|
||||
"ports": [1],
|
||||
"bank_direction_low": "output",
|
||||
"bank_direction_high": "output"
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Note that due to its high channel account and double EEM connections 2238 MCX-TTL is entered into a system description as two peripheral entries, each representing two banks.
|
||||
|
||||
The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry.
|
||||
|
||||
For single-EEM operation, use only one of two peripheral entries.
|
||||
IO direction switches partly decides the IO direction of each bank.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item Closed switch (ON) \\
|
||||
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item Opened switch (OFF) \\
|
||||
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\newpage
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
\codesection{2238 MCX-TTL card}
|
||||
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
|
||||
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
\subsection{Counting rising edges in a 1ms window}
|
||||
The channel should be configured as input in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
|
||||
\subsection{Edge counting in an 1ms window}
|
||||
The channel should be configured as input in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 2238 MCX-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\ordersection{2238 MCX-TTL}
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\finalfootnote
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
713
2245.tex
713
2245.tex
@ -1,5 +1,24 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/2245}{images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfig}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\usepackage{tikz-timing}
|
||||
\usetikztiminglibrary{counters}
|
||||
@ -7,7 +26,7 @@
|
||||
\title{2245 LVDS-TTL}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2022}
|
||||
\revision{Revision 3}
|
||||
\revision{Revision 2}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -16,47 +35,62 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{16 LVDS-TTL channels.}
|
||||
\item{Input- and output-capable}
|
||||
\item{No galvanic isolation}
|
||||
\item{High speed and low jitter}
|
||||
\item{RJ45 connectors}
|
||||
\item{16 LVDS channels.}
|
||||
\item{Input and output capable.}
|
||||
\item{No galvanic isolation.}
|
||||
\item{High speed and low jitter.}
|
||||
\item{RJ45 connectors.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Serial communication with remote devices}
|
||||
\item{Photon counting.}
|
||||
\item{External equipment trigger.}
|
||||
\item{Optical shutter control.}
|
||||
\item{Serial communication to remote devices.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
The 2245 LVDS-TTL card is a 4hp EEM module.
|
||||
It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
|
||||
Each card provides sixteen digital channels each, controlled through 2 EEM connectors.
|
||||
Each EEM connector controls eight channels independently.
|
||||
Single EEM operation is possible.
|
||||
Each RJ45 connector exposes four digital channels in the LVDS format.
|
||||
The direction (input or output) of each channel can be selected using DIP switches.
|
||||
Outputs are intended to drive 100\textOmega~loads, inputs are 100\textOmega~terminated.
|
||||
This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||
Only shielded Ethernet Cat-6 cables should be connected.
|
||||
|
||||
Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\inputcolorboxminted}[3][4]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#2, gobble=#1]{python}{#3}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{0.88}{
|
||||
\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
|
||||
|
||||
% RJ45 Connectors
|
||||
\draw (0, 2.8) node[twoportshape, t={\twocm{RJ45}{CH 0-3}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth0) {};
|
||||
\draw (0, 1.0) node[twoportshape, t={\twocm{RJ45}{CH 4-7}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth1) {};
|
||||
\draw (0, -1.0) node[twoportshape, t={\twocm{RJ45}{CH 8-11}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth2) {};
|
||||
\draw (0, -2.8) node[twoportshape, t={\twocm{RJ45}{CH 12-15}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth3) {};
|
||||
\draw (0, 2.8) node[twoportshape, t={\MyLabel{RJ45}{CH 0-3}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth0) {};
|
||||
\draw (0, 1.0) node[twoportshape, t={\MyLabel{RJ45}{CH 4-7}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth1) {};
|
||||
\draw (0, -1.0) node[twoportshape, t={\MyLabel{RJ45}{CH 8-11}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth2) {};
|
||||
\draw (0, -2.8) node[twoportshape, t={\MyLabel{RJ45}{CH 12-15}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth3) {};
|
||||
|
||||
% Repeaters for channels
|
||||
|
||||
% Channel 7 repeaters
|
||||
\draw (1.8, 0.4) node[twoportshape, t={\twocm{CH 7}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep7) {};
|
||||
\draw (1.8, 0.4) node[twoportshape, t={\MyLabel{CH 7}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep7) {};
|
||||
|
||||
% Omission dots
|
||||
\node at (1.8, 0.8)[circle,fill,inner sep=0.7pt]{};
|
||||
@ -64,10 +98,10 @@
|
||||
\node at (1.8, 1.2)[circle,fill,inner sep=0.7pt]{};
|
||||
|
||||
% Channel 4 repeaters
|
||||
\draw (1.8, 1.6) node[twoportshape, t={\twocm{CH 4}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep4) {};
|
||||
\draw (1.8, 1.6) node[twoportshape, t={\MyLabel{CH 4}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep4) {};
|
||||
|
||||
% Channel 3 repeaters
|
||||
\draw (1.8, 2.2) node[twoportshape, t={\twocm{CH 3}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep3) {};
|
||||
\draw (1.8, 2.2) node[twoportshape, t={\MyLabel{CH 3}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep3) {};
|
||||
|
||||
% Omission dots
|
||||
\node at (1.8, 2.6)[circle,fill,inner sep=0.7pt]{};
|
||||
@ -75,10 +109,10 @@
|
||||
\node at (1.8, 3.0)[circle,fill,inner sep=0.7pt]{};
|
||||
|
||||
% Channel 0 repeaters
|
||||
\draw (1.8, 3.4) node[twoportshape, t={\twocm{CH 0}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep0) {};
|
||||
\draw (1.8, 3.4) node[twoportshape, t={\MyLabel{CH 0}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep0) {};
|
||||
|
||||
% Channel 8 repeaters
|
||||
\draw (1.8, -0.4) node[twoportshape, t={\twocm{CH 8}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep8) {};
|
||||
\draw (1.8, -0.4) node[twoportshape, t={\MyLabel{CH 8}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep8) {};
|
||||
|
||||
% Omission dots
|
||||
\node at (1.8, -0.8)[circle,fill,inner sep=0.7pt]{};
|
||||
@ -86,10 +120,10 @@
|
||||
\node at (1.8, -1.2)[circle,fill,inner sep=0.7pt]{};
|
||||
|
||||
% Channel 11 repeaters
|
||||
\draw (1.8, -1.6) node[twoportshape, t={\twocm{CH 11}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep11) {};
|
||||
\draw (1.8, -1.6) node[twoportshape, t={\MyLabel{CH 11}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep11) {};
|
||||
|
||||
% Channel 12 repeaters
|
||||
\draw (1.8, -2.2) node[twoportshape, t={\twocm{CH 12}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep12) {};
|
||||
\draw (1.8, -2.2) node[twoportshape, t={\MyLabel{CH 12}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep12) {};
|
||||
|
||||
% Omission dots
|
||||
\node at (1.8, -2.6)[circle,fill,inner sep=0.7pt]{};
|
||||
@ -97,25 +131,25 @@
|
||||
\node at (1.8, -3.0)[circle,fill,inner sep=0.7pt]{};
|
||||
|
||||
% Channel 15 repeaters
|
||||
\draw (1.8, -3.4) node[twoportshape, t={\twocm{CH 15}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep15) {};
|
||||
\draw (1.8, -3.4) node[twoportshape, t={\MyLabel{CH 15}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep15) {};
|
||||
|
||||
% Direction switches
|
||||
\draw (4.6, 0.4) node[twoportshape,t=\fourcm{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch0) {};
|
||||
\draw (4.6, -0.4) node[twoportshape,t=\fourcm{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch1) {};
|
||||
\draw (4.6, 0.4) node[twoportshape,t=\MymyLabel{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch0) {};
|
||||
\draw (4.6, -0.4) node[twoportshape,t=\MymyLabel{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch1) {};
|
||||
\begin{scope}[xshift=5cm, yshift=0.65cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4, 0) to[short,-o](0.75, 0);
|
||||
\draw (0.78, 0)-- +(30: 0.46);
|
||||
\draw (1.25, 0)to[short,o-](1.6, 0);
|
||||
\draw (1.25, 0)to[short,o-](1.6, 0);
|
||||
\end{scope}
|
||||
\begin{scope}[xshift=5cm, yshift=-0.15cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4, 0) to[short,-o](0.75, 0);
|
||||
\draw (0.78, 0)-- +(30: 0.46);
|
||||
\draw (1.25, 0)to[short,o-](1.6, 0);
|
||||
\draw (1.25, 0)to[short,o-](1.6, 0);
|
||||
\end{scope}
|
||||
|
||||
% I2C I/O expanders
|
||||
\draw (4.6, 1.6) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c0) {};
|
||||
\draw (4.6, -1.6) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c1) {};
|
||||
\draw (4.6, 1.6) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c0) {};
|
||||
\draw (4.6, -1.6) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c1) {};
|
||||
|
||||
% 2 Aesthetic EEPROMs
|
||||
\draw (4.6, 2.2) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (eeprom0) {};
|
||||
@ -296,9 +330,9 @@
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[angle=90, height=1.7in]{photo2245.jpg}
|
||||
\includegraphics[angle=90, height=0.4in]{fp2245.pdf}
|
||||
\caption{LVDS-TTL card and front panel}
|
||||
\includegraphics[height=2.1in]{DIO_RJ45_FP.pdf}
|
||||
\includegraphics[height=2.1in]{photo2245.jpg}
|
||||
\caption{LVDS-TTL Card photo}
|
||||
\end{figure}
|
||||
|
||||
|
||||
@ -306,372 +340,335 @@
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{2245 LVDS-TTL}{https://github.com/sinara-hw/DIO_LVDS_RJ45/wiki}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
|
||||
Information in this section is based on the datasheet of the repeaters IC (FIN1101K8X\footnote{\label{repeaters}https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}).
|
||||
|
||||
\begin{table}[h!]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Input Voltage}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Magnitude of differential input & $|V_{ID}|$ & 0.1 & & 3.3 & V \\
|
||||
\hline
|
||||
Common mode input & $V_{IC}$ & $|V_{ID}|/2$ & & $3.3-|V_{ID}|/2$ & V \\
|
||||
\hline
|
||||
Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
|
||||
\hline
|
||||
Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Input Voltage}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Magnitude of differential input & $|V_{ID}|$ & 0.1 & & 3.3 & V \\
|
||||
\hline
|
||||
Common mode input & $V_{IC}$ & $|V_{ID}|/2$ & & $3.3-|V_{ID}|/2$ & V \\
|
||||
\hline
|
||||
Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
|
||||
\hline
|
||||
Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
|
||||
|
||||
All typical values of DC specifications are at $T_A = 25\degree C$.
|
||||
All specifications are in the recommended operating temperature range unless otherwise noted.
|
||||
All typical values of DC specifications are at $T_A = 25\degree C$.
|
||||
|
||||
\begin{table}[h!]
|
||||
\begin{threeparttable}
|
||||
\caption{DC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
|
||||
\cline{0-5}
|
||||
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
|
||||
\cline{0-5}
|
||||
Offset voltage & $V_{OS}$ & 1.125 & 1.23 & 1.375 & V & \\
|
||||
\cline{0-5}
|
||||
$|V_{OS}|$ change (LOW-to-HIGH) & $\Delta V_{OS}$ & & & 25 & mV & \\
|
||||
\hline
|
||||
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
|
||||
\hline
|
||||
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
|
||||
|
||||
\begin{table}[h!]
|
||||
\begin{threeparttable}
|
||||
\caption{AC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
|
||||
(20\% to 80\%) & & & & & \\
|
||||
\cline{0-5}
|
||||
Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
|
||||
(80\% to 20\%) & & & & & \\
|
||||
\cline{0-5}
|
||||
Pulse width distortion & & 0.01 & 0.2 & ns & \\
|
||||
\hline
|
||||
LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
|
||||
deterministic & & & & & 800 Mbps\\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{DC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Output differentiual Voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
|
||||
\cline{0-5}
|
||||
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
|
||||
\cline{0-5}
|
||||
Offset voltage & $V_{OS}$ & 1.125 & 1.23 & 1.375 & V & \\
|
||||
\cline{0-5}
|
||||
$|V_{OS}|$ change (LOW-to-HIGH) & $\Delta V_{OS}$ & & & 25 & mV & \\
|
||||
\hline
|
||||
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
|
||||
\hline
|
||||
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended Input Voltage \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
\begin{table}[h!]
|
||||
\begin{threeparttable}
|
||||
\caption{AC Specifications, cont.}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
|
||||
random (RMS) & & & & & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise specified.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{AC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Differential Output Rise Time & \multirow{2}{*}{$t_{TLHD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & duty Cycle = 50\%.\\
|
||||
(20\% to 80\%) & & & & & & \\
|
||||
\cline{0-5}
|
||||
Differential Output Fall Time & \multirow{2}{*}{$t_{THLD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
|
||||
(80\% to 20\%) & & & & & & \\
|
||||
\cline{0-5}
|
||||
Pulse width distortion & $PWD$ & & 0.01 & 0.2 & ns & \\
|
||||
\hline
|
||||
LVDS data jitter, & \multirow{2}{*}{$t_{DJ}$} & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
|
||||
deterministic & & & & & & 800 Mbps\\
|
||||
\hline
|
||||
LVDS clock jitter, & \multirow{2}{*}{$t_{RJ}$} & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
|
||||
random (RMS) & & & & & & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
|
||||
\begin{multicols}{2}
|
||||
|
||||
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
|
||||
\vspace*{\fill}\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\sysdescsection
|
||||
|
||||
2245 LVDS-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "dio",
|
||||
"board": "DIO_LVDS", // optional
|
||||
"ports": [0],
|
||||
"edge_counter": true, // optional
|
||||
"bank_direction_low": "input", // or "output"
|
||||
"bank_direction_high": "output" // or "input"
|
||||
},
|
||||
{
|
||||
"type": "dio",
|
||||
"board": "DIO_LVDS",
|
||||
"ports": [1],
|
||||
"bank_direction_low": "output",
|
||||
"bank_direction_high": "output"
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Note that due to its high channel account and double EEM connections 2245 LVDS-TTL is entered into a system description as two peripheral entries, each representing two banks.
|
||||
|
||||
The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry.
|
||||
|
||||
For single-EEM operation, use only one of two peripheral entries.
|
||||
The IO direction can be configured by switches, which are found at the top of the card.
|
||||
\begin{multicols}{2}
|
||||
IO direction switches partly decides the IO direction of each bank.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item Closed switch (ON) \\
|
||||
Fix the corresponding channel to output. The direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item Opened switch (OFF) \\
|
||||
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\newpage
|
||||
|
||||
\codesection{2245 LVDS-TTL card}
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
\subsection{Morse code}
|
||||
This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
|
||||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
\subsection{Counting rising edges in a 1ms window}
|
||||
The channel should be configured as input in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
|
||||
\subsection{Counting rising edges in a 1ms window}
|
||||
The channel should be configured as input in both gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
|
||||
\newcommand{\wrapspacer}[1]% #1 = special text
|
||||
{\bgroup
|
||||
\sbox0{\begin{minipage}{\linewidth}\hrule height0pt
|
||||
#1\hrule height0pt
|
||||
\end{minipage}}%
|
||||
\dimen0=\dimexpr \ht0+\dp0\relax
|
||||
\loop\ifdim\dimen0>\baselineskip
|
||||
\strut\vspace{-\baselineskip}\newline
|
||||
\advance\dimen0 by -\baselineskip
|
||||
\repeat
|
||||
\noindent\strut\usebox0\par
|
||||
\egroup}
|
||||
|
||||
\subsection{SPI Master Device}
|
||||
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
|
||||
\begin{enumerate}
|
||||
% The config register can be set using set_config.
|
||||
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
|
||||
% frequency, then translate into the rough frequency divisor for set_config_mu.
|
||||
% It doesn't guarantee such frequency would be set as the SPI frequency
|
||||
|
||||
% In addition, finding clock division is quite easy. set_config_mu seems to be a more
|
||||
% straight-forward & representative of the actual implementation.
|
||||
\item Set the \texttt{config} register (e.g. using \texttt{set\char`_config\char`_mu()}).
|
||||
\item Start the SPI transfer by writing the \texttt{data} register using \texttt{write()}.
|
||||
\item If the data from the SPI slave is to be read (i.e. \texttt{SPI\char`_INPUT} was set in \texttt{config}), invoke \texttt{read()} to read.
|
||||
|
||||
\end{enumerate}
|
||||
|
||||
The list of configurations supported in the gateware are listed as below:
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{tabular}{|c|l|}
|
||||
\hline
|
||||
Flag & Description \\ \hline
|
||||
\texttt{SPI\char`_OFFLINE} & Switch all pins to high impedance mode. \\ \hline
|
||||
\texttt{SPI\char`_END} & Next SPI transfer is the last of the transcation. \\ \hline
|
||||
\texttt{SPI\char`_INPUT} & Submit SPI read data as RTIO input event when the transfer is complete. \\ \hline
|
||||
\texttt{SPI\char`_CS\char`_POLARITY} & Active level of chip select (CS) \\ \hline
|
||||
\texttt{SPI\char`_CLK\char`_POLARITY} & Idle level of serial clock (SCK) \\ \hline
|
||||
\texttt{SPI\char`_CLK\char`_PHASE} & Data is sampled on falling edge \& shifted out on rising edge. \\ \hline
|
||||
\texttt{SPI\char`_LSB\char`_FIRST} & LSB is the first on bit on the wire. \\ \hline
|
||||
\texttt{SPI\char`_HALF\char`_DUPLEX} & Use 3-wire SPI, where MOSI is both input \& output capable. \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves. The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
|
||||
\newcommand{\wrapspacer}[1]% #1 = special text
|
||||
{\bgroup
|
||||
\sbox0{\begin{minipage}{\linewidth}\hrule height0pt
|
||||
#1\hrule height0pt
|
||||
\end{minipage}}%
|
||||
\dimen0=\dimexpr \ht0+\dp0\relax
|
||||
\loop\ifdim\dimen0>\baselineskip
|
||||
\strut\vspace{-\baselineskip}\newline
|
||||
\advance\dimen0 by -\baselineskip
|
||||
\repeat
|
||||
\noindent\strut\usebox0\par
|
||||
\egroup}
|
||||
|
||||
\newpage
|
||||
\subsection{SPI Master Device}
|
||||
If a EEM port is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices.
|
||||
Invocation of an SPI transfer follows this pattern:
|
||||
\begin{enumerate}
|
||||
% The config register can be set using set_config.
|
||||
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
|
||||
% frequency, then translate into the rough frequency divisor for set_config_mu.
|
||||
% It doesn't guarantee such frequency would be set as the SPI frequency
|
||||
|
||||
\begin{center}
|
||||
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
|
||||
% SPI master
|
||||
\draw (0, 1.8) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=2, scale=1] (master) {};
|
||||
\node [label={center:\large{SPI Master}}] at (-0.6, 2.05) {};
|
||||
\node [label={center:\large{(LVDS-TTL)}}] at (-0.6, 1.55) {};
|
||||
\node [label=left:{SCK}] at (2, 2.8) {};
|
||||
\node [label=left:{MOSI}] at (2, 2.4) {};
|
||||
\node [label=left:{MISO}] at (2, 2.0) {};
|
||||
\node [label=left:{CS0}] at (2, 1.6) {};
|
||||
\node [label=left:{CS1}] at (2, 1.2) {};
|
||||
\node [label=left:{CS2}] at (2, 0.8) {};
|
||||
% In addition, finding clock division is quite easy. set_config_mu seems to be a more
|
||||
% straight-forward & representative of the actual implementation.
|
||||
\item Set the \texttt{config} register (e.g. using \texttt{set\char`_config\char`_mu()}).
|
||||
\item Start the SPI transfer by writing the \texttt{data} register using \texttt{write()}.
|
||||
\item If the data from the SPI slave is to be read (i.e. \texttt{SPI\char`_INPUT} was set in \texttt{config}), invoke \texttt{read()} to read.
|
||||
|
||||
% SPI slaves
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, 2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave0) {};
|
||||
\node [label={center:\large{SPI Slave 0}}] at (7.6, 2.2) {};
|
||||
\node [label=right:{SCK}] at (5, 2.8) {};
|
||||
\node [label=right:{MOSI}] at (5, 2.4) {};
|
||||
\node [label=right:{MISO}] at (5, 2.0) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, 1.6) {};
|
||||
\end{enumerate}
|
||||
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, 0) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave1) {};
|
||||
\node [label={center:\large{SPI Slave 1}}] at (7.6, 0) {};
|
||||
\node [label=right:{SCK}] at (5, 0.6) {};
|
||||
\node [label=right:{MOSI}] at (5, 0.2) {};
|
||||
\node [label=right:{MISO}] at (5, -0.2) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -0.6) {};
|
||||
The list of configurations supported in the gateware are listed as below:
|
||||
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, -2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave2) {};
|
||||
\node [label={center:\large{SPI Slave 2}}] at (7.6, -2.2) {};
|
||||
\node [label=right:{SCK}] at (5, -1.6) {};
|
||||
\node [label=right:{MOSI}] at (5, -2.0) {};
|
||||
\node [label=right:{MISO}] at (5, -2.4) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -2.8) {};
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{tabular}{|c|l|}
|
||||
\hline
|
||||
Flag & Description \\ \hline
|
||||
\texttt{SPI\char`_OFFLINE} & Switch all pins to high impedance mode. \\ \hline
|
||||
\texttt{SPI\char`_END} & Next SPI transfer is the last of the transcation. \\ \hline
|
||||
\texttt{SPI\char`_INPUT} & Submit SPI read data as RTIO input event when the transfer is complete. \\ \hline
|
||||
\texttt{SPI\char`_CS\char`_POLARITY} & Active level of chip select (CS) \\ \hline
|
||||
\texttt{SPI\char`_CLK\char`_POLARITY} & Idle level of serial clock (SCK) \\ \hline
|
||||
\texttt{SPI\char`_CLK\char`_PHASE} & Data is sampled on falling edge \& shifted out on rising edge. \\ \hline
|
||||
\texttt{SPI\char`_LSB\char`_FIRST} & LSB is the first on bit on the wire. \\ \hline
|
||||
\texttt{SPI\char`_HALF\char`_DUPLEX} & Use 3-wire SPI, where MOSI is both input \& output capable. \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
% Connect the master to slave 0
|
||||
\draw [-latexslim] (1.95, 2.8) -- (5.05, 2.8);
|
||||
\draw [-latexslim] (1.95, 2.4) -- (5.05, 2.4);
|
||||
\draw [latexslim-] (1.95, 2.0) -- (5.05, 2.0);
|
||||
\draw [-latexslim] (1.95, 1.6) -- (5.05, 1.6);
|
||||
The following ARTIQ example demonstrates the flow of an SPI transcation with a typical SPI setup with 3 homogeneous slaves.
|
||||
The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
|
||||
\begin{center}
|
||||
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
|
||||
% SPI master
|
||||
\draw (0, 1.8) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=2, scale=1] (master) {};
|
||||
\node [label={center:\large{SPI Master}}] at (-0.6, 2.05) {};
|
||||
\node [label={center:\large{(LVDS-TTL)}}] at (-0.6, 1.55) {};
|
||||
\node [label=left:{SCK}] at (2, 2.8) {};
|
||||
\node [label=left:{MOSI}] at (2, 2.4) {};
|
||||
\node [label=left:{MISO}] at (2, 2.0) {};
|
||||
\node [label=left:{CS0}] at (2, 1.6) {};
|
||||
\node [label=left:{CS1}] at (2, 1.2) {};
|
||||
\node [label=left:{CS2}] at (2, 0.8) {};
|
||||
|
||||
% Connect slave 1
|
||||
\draw [-latexslim] (4.2, 2.8) -- (4.2, 0.6) -- (5.05, 0.6);
|
||||
\draw [-latexslim] (3.8, 2.4) -- (3.8, 0.2) -- (5.05, 0.2);
|
||||
\draw [-] (3.4, 2.0) -- (3.4, -0.2) -- (5.05, -0.2);
|
||||
\draw [-latexslim] (1.95, 1.2) -- (3.0, 1.2) -- (3.0, -0.6) -- (5.05, -0.6);
|
||||
% SPI slaves
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, 2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave0) {};
|
||||
\node [label={center:\large{SPI Slave 0}}] at (7.6, 2.2) {};
|
||||
\node [label=right:{SCK}] at (5, 2.8) {};
|
||||
\node [label=right:{MOSI}] at (5, 2.4) {};
|
||||
\node [label=right:{MISO}] at (5, 2.0) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, 1.6) {};
|
||||
|
||||
% Connect slave 2
|
||||
\draw [-latexslim] (4.2, 0.6) -- (4.2, -1.6) -- (5.05, -1.6);
|
||||
\draw [-latexslim] (3.8, 0.2) -- (3.8, -2.0) -- (5.05, -2.0);
|
||||
\draw [-] (3.4, -0.2) -- (3.4, -2.4) -- (5.05, -2.4);
|
||||
\draw [-latexslim] (1.95, 0.8) -- (2.6, 0.8) -- (2.6, -2.8) -- (5.05, -2.8);
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, 0) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave1) {};
|
||||
\node [label={center:\large{SPI Slave 1}}] at (7.6, 0) {};
|
||||
\node [label=right:{SCK}] at (5, 0.6) {};
|
||||
\node [label=right:{MOSI}] at (5, 0.2) {};
|
||||
\node [label=right:{MISO}] at (5, -0.2) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -0.6) {};
|
||||
|
||||
% Add dot to intersection to distinguish from overlaps
|
||||
\node at (4.2, 2.8)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.8, 2.4)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.4, 2.0)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (4.2, 0.6)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.8, 0.2)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.4, -0.2)[circle,fill,inner sep=0.7pt]{};
|
||||
% The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
|
||||
\draw (7, -2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave2) {};
|
||||
\node [label={center:\large{SPI Slave 2}}] at (7.6, -2.2) {};
|
||||
\node [label=right:{SCK}] at (5, -1.6) {};
|
||||
\node [label=right:{MOSI}] at (5, -2.0) {};
|
||||
\node [label=right:{MISO}] at (5, -2.4) {};
|
||||
\node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -2.8) {};
|
||||
|
||||
\end{circuitikz}
|
||||
\end{center}
|
||||
% Connect the master to slave 0
|
||||
\draw [-latexslim] (1.95, 2.8) -- (5.05, 2.8);
|
||||
\draw [-latexslim] (1.95, 2.4) -- (5.05, 2.4);
|
||||
\draw [latexslim-] (1.95, 2.0) -- (5.05, 2.0);
|
||||
\draw [-latexslim] (1.95, 1.6) -- (5.05, 1.6);
|
||||
|
||||
\subsubsection{SPI Configuration}
|
||||
The following examples will assume the SPI communication has the following properties:
|
||||
\begin{itemize}
|
||||
\item Chip select (CS) is active low
|
||||
\item Serial clock (SCK) idle level is low
|
||||
\item Data is sampled on rising edge of SCK \& shifted out on falling edge of SCK
|
||||
\item Most significant bit (MSB) first
|
||||
\item Full duplex
|
||||
\end{itemize}
|
||||
% Connect slave 1
|
||||
\draw [-latexslim] (4.2, 2.8) -- (4.2, 0.6) -- (5.05, 0.6);
|
||||
\draw [-latexslim] (3.8, 2.4) -- (3.8, 0.2) -- (5.05, 0.2);
|
||||
\draw [-] (3.4, 2.0) -- (3.4, -0.2) -- (5.05, -0.2);
|
||||
\draw [-latexslim] (1.95, 1.2) -- (3.0, 1.2) -- (3.0, -0.6) -- (5.05, -0.6);
|
||||
|
||||
% Connect slave 2
|
||||
\draw [-latexslim] (4.2, 0.6) -- (4.2, -1.6) -- (5.05, -1.6);
|
||||
\draw [-latexslim] (3.8, 0.2) -- (3.8, -2.0) -- (5.05, -2.0);
|
||||
\draw [-] (3.4, -0.2) -- (3.4, -2.4) -- (5.05, -2.4);
|
||||
\draw [-latexslim] (1.95, 0.8) -- (2.6, 0.8) -- (2.6, -2.8) -- (5.05, -2.8);
|
||||
|
||||
% Add dot to intersection to distinguish from overlaps
|
||||
\node at (4.2, 2.8)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.8, 2.4)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.4, 2.0)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (4.2, 0.6)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.8, 0.2)[circle,fill,inner sep=0.7pt]{};
|
||||
\node at (3.4, -0.2)[circle,fill,inner sep=0.7pt]{};
|
||||
|
||||
\end{circuitikz}
|
||||
\end{center}
|
||||
|
||||
\newpage
|
||||
\subsubsection{SPI Configuration}
|
||||
The following examples will assume the SPI communication has the following properties:
|
||||
\begin{itemize}
|
||||
\item Chip select (CS) is active low
|
||||
\item Serial clock (SCK) idle level is low
|
||||
\item Data is sampled on rising edge of SCK \& shifted out on falling edge of SCK
|
||||
\item Most significant bit (MSB) first
|
||||
\item Full duplex
|
||||
\end{itemize}
|
||||
The base line configuration for an \texttt{SPIMaster} instance can be defined as such:
|
||||
\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
|
||||
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
|
||||
|
||||
The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
|
||||
\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
|
||||
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
|
||||
\subsubsection{SPI frequency}
|
||||
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor from [2, 257].
|
||||
In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
|
||||
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
|
||||
|
||||
\subsubsection{SPI frequency}
|
||||
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
|
||||
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
|
||||
\subsubsection{SPI write}
|
||||
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves.
|
||||
Suppose the instruction and data are 8 bits and 32 bits respectively.
|
||||
The timing diagram of such write operation is shown in the following.
|
||||
|
||||
\subsubsection{SPI write}
|
||||
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
|
||||
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
[
|
||||
timing/d/background/.style={fill=white},
|
||||
timing/lslope=0.2
|
||||
]
|
||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||
% then print the label from macro. But it turns out tikz-timing will print
|
||||
% the counter value separately, even with an additional macro.
|
||||
% Therefore, it does not work properly.
|
||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}, timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||
UJ{7}8{2I}R{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||
MOSI & 53U \\
|
||||
\end{tikztimingtable}%
|
||||
\end{center}
|
||||
|
||||
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
|
||||
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
[
|
||||
timing/d/background/.style={fill=white},
|
||||
timing/lslope=0.2
|
||||
]
|
||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||
% then print the label from macro. But it turns out tikz-timing will print
|
||||
% the counter value separately, even with an additional macro.
|
||||
% Therefore, it does not work properly.
|
||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}, timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||
UJ{7}8{2I}R{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||
MOSI & 53U \\
|
||||
\end{tikztimingtable}%
|
||||
\end{center}
|
||||
|
||||
\newpage
|
||||
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transcation can be performed by the following code.
|
||||
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
|
||||
|
||||
\subsubsection{SPI read}
|
||||
A 32-bit read is represented by the following timing diagram:
|
||||
\subsubsection{SPI read}
|
||||
A 32-bits read is represented by the following timing diagram.
|
||||
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
[
|
||||
timing/d/background/.style={fill=white},
|
||||
timing/lslope=0.2
|
||||
]
|
||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||
% then print the label from macro. But it turns out tikz-timing will print
|
||||
% the counter value separately, even with an additional macro.
|
||||
% Therefore, it does not work properly.
|
||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}]
|
||||
UJ{7}8{2I}36U \\
|
||||
MOSI & [timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||
17UR{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||
\end{tikztimingtable}%
|
||||
\end{center}
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
[
|
||||
timing/d/background/.style={fill=white},
|
||||
timing/lslope=0.2
|
||||
]
|
||||
$\mathrm{\overline{CS}}$ & H51{L}H \\
|
||||
SCK & LL31{T}; 2{[dotted] T}; 17{T} L \\
|
||||
% The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
|
||||
% then print the label from macro. But it turns out tikz-timing will print
|
||||
% the counter value separately, even with an additional macro.
|
||||
% Therefore, it does not work properly.
|
||||
MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}]
|
||||
UJ{7}8{2I}36U \\
|
||||
MOSI & [timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
|
||||
17UR{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
|
||||
\end{tikztimingtable}%
|
||||
\end{center}
|
||||
|
||||
Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
|
||||
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
|
||||
Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
|
||||
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
|
||||
|
||||
\ordersection{2245 LVDS-TTL}
|
||||
\newpage
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 2245 LVDS-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\finalfootnote
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
830
4410-4412.tex
830
4410-4412.tex
File diff suppressed because it is too large
Load Diff
@ -1,10 +1,30 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/4456-4457}{images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\title{4456 Synthesizer Mirny / 4457 HF Synthesizer Mirny + Almazny}
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfigure}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usepackage{pifont}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\title{4456 Synthesizer Mirny}
|
||||
\author{M-Labs Limited}
|
||||
\date{April 2025}
|
||||
\revision{Revision 3}
|
||||
\date{January 2022}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -13,31 +33,45 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{4-channel wide-band PLL/VCO-based microwave frequency synthesiser}
|
||||
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz for 4456 Mirny only}
|
||||
\item{Up to 12 GHz with 4457 Almazny}
|
||||
\item{Higher frequency resolution than 4410/4412 Urukul}
|
||||
\item{Lower jitter, phase noise than 4410/4412 Urukul}
|
||||
\item{4-channel VCO/PLL.}
|
||||
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz.}
|
||||
\item{Up to 13.6 GHz with Almazny mezzanine.}
|
||||
\item{Higher frequency resolution than Urukul.}
|
||||
\item{Lower jitter and phase noise.}
|
||||
\item{Large frequency changes take several milliseconds.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Low-noise microwave source}
|
||||
\item{Quantum state control}
|
||||
\item{Driving acousto/electro-optic modulators}
|
||||
\item{Low-noise microwave source.}
|
||||
\item{Quantum state control.}
|
||||
\item{Driving acousto/electro-optic modulators.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 4456 Synthesizer Mirny card is a 4hp EEM module; the 4457 HF Synthesizer Mirny + Almazny card, consisting of 4456 Mirny plus the 4-channel Almazny HF mezzanine, is a 8hp EEM module. Both Synthesizer cards add microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
The 4456 Synthesizer Mirny card is a 4hp EEM module part of the ARTIQ Sinara family.
|
||||
It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Both cards provide 4 channels of PLL frequency synthesis. 4456 Synthesizer Mirny supports output frequencies from 53 MHz to \textgreater 4GHz. As 4457 HF Synthesizer with Almazny mezzanine this range is expanded up to 12 GHz.
|
||||
It provides 4 channels of PLL frequency synthesis.
|
||||
Output frequency from 53 MHz to \textgreater 4 GHz are supported.
|
||||
The range can be expanded up to 13.6 GHz with Almazny mezzanine.
|
||||
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator.
|
||||
RF switches on each channel provides at least 50 dB isolation.
|
||||
|
||||
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provide at least 50 dB isolation.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
|
||||
\newcommand{\inputcolorboxminted}[2]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#1, gobble=4]{python}{#2}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{0.95}{
|
||||
@ -98,14 +132,14 @@
|
||||
\draw (0,0) circle(1.5);
|
||||
\clip (-0.8,0) rectangle (0.8,0.8);
|
||||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
\end{scope}
|
||||
\begin{scope}[scale=0.07 , rotate=-90, xshift=45cm, yshift=2cm]
|
||||
\draw (0,0.65) -- (0,3);
|
||||
\clip (-1.5,0) rectangle (1.5,1.5);
|
||||
\draw (0,0) circle(1.5);
|
||||
\clip (-0.8,0) rectangle (0.8,0.8);
|
||||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
\end{scope}
|
||||
\begin{scope}[scale=0.07 , rotate=-90, xshift=55cm, yshift=2cm]
|
||||
\draw (0,0.65) -- (0,3);
|
||||
\clip (-1.5,0) rectangle (1.5,1.5);
|
||||
@ -194,8 +228,8 @@
|
||||
\draw [latexslim-latexslim] (cpld.east) -- (afe.west);
|
||||
|
||||
% Draw LVDS transceivers, EEM
|
||||
\draw (6.2, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
|
||||
\draw (6.2, -1.6) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
|
||||
\draw (6.2, 0) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
|
||||
\draw (6.2, -1.6) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
|
||||
\draw (7.8, -1.5) node[twoportshape, t={EEM Port}, circuitikz/bipoles/twoport/width=3.8, scale=0.7, rotate=-90] (eem) {};
|
||||
|
||||
% Connect LVDS transceiver to CPLD
|
||||
@ -234,7 +268,7 @@
|
||||
\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
|
||||
|
||||
% Attenuators {0, 1, 2, 3} for amplifiers {0, 1, 2, 3}
|
||||
\draw (4.6, 0) node[twoportshape, t=\fourcm{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
|
||||
\draw (4.6, 0) node[twoportshape, t=\MymyLabel{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
|
||||
|
||||
% PLL {0, 1, 2, 3} for attenuators {0, 1, 2, 3}
|
||||
\draw (6.6, 0) node[twoportshape, t={PLL}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (pll) {};
|
||||
@ -273,230 +307,178 @@
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=2in]{photo4457.jpg}
|
||||
\caption{Mirny + Almazny card}
|
||||
\includegraphics[height=2in]{Mirny_FP.pdf}
|
||||
\includegraphics[height=2in]{photo4456.jpg}
|
||||
\caption{Mirny Card photo}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\subfloat[\centering Mirny and Almazny front panels]{{
|
||||
\begin{minipage}[b]{0.5\linewidth}
|
||||
\centering
|
||||
\includegraphics[height=3.4in, angle=90]{fp4457.jpg} \\
|
||||
\vspace{0.1in}
|
||||
\includegraphics[height=3.4in, angle=90]{fp4456.jpg}
|
||||
\vspace{0.3in}
|
||||
\end{minipage}
|
||||
}}
|
||||
\subfloat[\centering Mirny, top-down view]{{
|
||||
\includegraphics[height=2.5in]{photo4456.jpg}
|
||||
}}
|
||||
\end{figure}
|
||||
|
||||
\sourcesectiond{4456 Synthesizer Mirny}{the 4457 Almazny mezzanine}{https://github.com/sinara-hw/mirny}{https://github.com/sinara-hw/Almazny}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
Specifications of parameters are based on the datasheets of the PLL IC
|
||||
(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
|
||||
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
|
||||
and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
|
||||
Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
% Note to future editors, the clk_div signal in gateware is not used.
|
||||
% Input divider was removed (mirny#8)
|
||||
Clock input & & & & & \\
|
||||
\hspace{3mm}Frequency\repeatfootnote{adf5356}
|
||||
& 10 & & 250 & MHz & Single-ended clock input (PLL config.) \\
|
||||
& 10 & & 600 & MHz & Differential clock input (PLL config.) \\
|
||||
\cline{2-6}
|
||||
\hspace{3mm}Differential input swing\repeatfootnote{clock_buffer}
|
||||
& 0.11 & & 1.55 & V\textsubscript{p-p} & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Frequency & 53.125 & & 4000 & MHz & 4456 Mirny only \\
|
||||
& & & 12000 & MHz & With Almazny mezzanine \\
|
||||
\hline
|
||||
Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
|
||||
\hline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
Specifications of parameters are based on the datasheets of the
|
||||
PLL IC(ADF5356\footnote{\label{adf5356}https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}),
|
||||
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}),
|
||||
digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}).
|
||||
Test results are from the Krzysztof Belewicz's thesis ``Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications, cont.}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Lock time\repeatfootnote{adf5356} & & 1.7 & & ms & \\
|
||||
\hline
|
||||
Resolution & & & & \\
|
||||
\hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{3}{c|}{52} & bits & \\
|
||||
\hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{3}{c|}{24} & bits & \\
|
||||
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{3}{c|}{0.5} & dB & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
% Note to future editors, the clk_div signal in gateware is not used.
|
||||
% Input divider was removed (mirny#8)
|
||||
Clock input & & & & & \\
|
||||
\hspace{3mm}Frequency\repeatfootnote{adf5356}
|
||||
& 10 & & 250 & MHz & Single-ended clock input (PLL config.) \\
|
||||
& 10 & & 600 & MHz & Differential clock input (PLL config.) \\
|
||||
\cline{2-6}
|
||||
\hspace{3mm}Differential input swing\repeatfootnote{clock_buffer}
|
||||
& 0.11 & & 1.55 & V\textsubscript{p-p} & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
Phase noise performance of 4456 Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. 4456 Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
|
||||
|
||||
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[height=3in]{mirny_phase_noise_cm_choke.png}
|
||||
\caption{Phase noise measurement at 1 GHz}
|
||||
\end{figure}
|
||||
|
||||
\begin{itemize}
|
||||
\item Red: Before any modifications
|
||||
\item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
|
||||
\end{itemize}
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications}
|
||||
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Frequency & 53.125 & & 4000 & MHz & \\
|
||||
\hline
|
||||
Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
|
||||
\hline
|
||||
Resolution & \multicolumn{4}{c|}{} & \\
|
||||
\hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{4}{c|}{52 bits} & \\
|
||||
\hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{4}{c|}{24 bits} & \\
|
||||
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{4}{c|}{0.5 dB} & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
Phase noise at different output frequencies is then measured:
|
||||
Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}.
|
||||
The SPI signal is driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card.
|
||||
Mirny is then connected to the RSA5100A spectrum analyzer for measurement.
|
||||
|
||||
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
||||
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny.
|
||||
Note that the common-mode choke is not present on the Mirny card.
|
||||
The following is a comparison between 2 setups at 1 GHz output:
|
||||
\begin{itemize}
|
||||
\item Red: Before any modifications
|
||||
\item Blue: Adding a CM choke with an 100 \textmu F capacitor after the CM choke
|
||||
\end{itemize}
|
||||
|
||||
\begin{table}[hbt!]
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Phase noise performance}
|
||||
\begin{tabularx}{0.8\textwidth}{| c | Y | Y | Y | Y | Y |}
|
||||
\thickhline
|
||||
\multirow{2}{*}{\textbf{Output frequency}} &
|
||||
\multicolumn{5}{c|}{\textbf{Phase noise (dBc/Hz) at carrier offset}}\\
|
||||
\cline{2-6} & 1 kHz & 10 kHz & 100 kHz & 1 MHz & 10 MHz \\
|
||||
\hline
|
||||
125 MHz & -114 & -116 & -115 & -132 & -133 \\
|
||||
\hline
|
||||
500 MHz & -107 & -129 & -111 & -130 & -132 \\
|
||||
\hline
|
||||
1 GHz & -102 & -106 & -107 & -125 & -133 \\
|
||||
\hline
|
||||
2 GHz & -102 & -98 & -104 & -123 & -124 \\
|
||||
\hline
|
||||
3.5 GHz & -96 & -101 & -103 & -127 & -128 \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\includegraphics[height=3in]{mirny_phase_noise_cm_choke.png}
|
||||
\caption{Phase noise measurement at 1 GHz}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[height=3in]{mirny_phase_noise_frequency.png}
|
||||
\caption{Phase noise measurement}
|
||||
\end{figure}
|
||||
Phase noise at different output frequencies are then measured.
|
||||
|
||||
\section{Programmable LEDs}
|
||||
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
||||
|
||||
4456 Mirny features several status LEDs, including a two per output channel. One per channel displays RF switch status.
|
||||
|
||||
The 4457 Almazny mezzanine features an additional row of LEDs, one per output channel, without a fixed purpose. The associated ARTIQ module allows programming these directly through the channel \texttt{set} method.
|
||||
\begin{table}[hbt!]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Phase noise performance}
|
||||
\begin{tabularx}{0.8\textwidth}{| c | Y | Y | Y | Y | Y |}
|
||||
\thickhline
|
||||
\multirow{2}{*}{\textbf{Output frequency}} &
|
||||
\multicolumn{5}{c|}{\textbf{Phase noise (dBc/Hz) at carrier offset}}\\
|
||||
\cline{2-6} & 1 kHz & 10 kHz & 100 kHz & 1 MHz & 10 MHz \\
|
||||
\hline
|
||||
125 MHz & -114 & -116 & -115 & -132 & -133 \\
|
||||
\hline
|
||||
500 MHz & -107 & -129 & -111 & -130 & -132 \\
|
||||
\hline
|
||||
1 GHz & -102 & -106 & -107 & -125 & -133 \\
|
||||
\hline
|
||||
2 GHz & -102 & -98 & -104 & -123 & -124 \\
|
||||
\hline
|
||||
3.5 GHz & -96 & -101 & -103 & -127 & -128 \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
\sysdescsection
|
||||
|
||||
4456 Synthesizer Mirny must be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[height=3in]{mirny_phase_noise_frequency.png}
|
||||
\caption{Phase noise measurement}
|
||||
\end{figure}
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "mirny",
|
||||
"ports": 0,
|
||||
"clk_sel": "mmcx", // optional
|
||||
"refclk": 125e6 // optional
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
\newpage
|
||||
|
||||
Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{clk\_sel} field is optional and may be specified as one of either \texttt{xo}, \texttt{mmcx}, or \texttt{sma}. The default is \texttt{xo}. The \texttt{refclk} field is optional and the default is \texttt{100e6}.
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 4456 Synthesizer Mirny card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
For 4457 Mirny + Almazny, one field must be added:
|
||||
\subsection{1 GHz Sinusoidal Wave}
|
||||
Generate a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB.
|
||||
Both the CPLD and the PLL channels should be initialized.
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "mirny",
|
||||
"almazny": true,
|
||||
"ports": 0
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
|
||||
|
||||
\codesection{4456 Synthesizer Mirny and 4457 Mirny + Almazny}
|
||||
\subsection{ADF5356 Power Control}
|
||||
Output power can be controlled be configuring the PLL channels individually, in addition to the digital attenuators.
|
||||
After initialization of the PLL channel (ADF5356), the following line of code can change the output power level.
|
||||
|
||||
\subsection{1 GHz sinusoidal wave}
|
||||
Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
|
||||
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
|
||||
|
||||
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
|
||||
The parameter corresponds to a specific change of output power according to the following table\repeatfootnote{adf5356}.
|
||||
|
||||
\subsection{Almazny paired output}
|
||||
\begin{center}
|
||||
\captionof{table}{Power changes from ADF5356}
|
||||
\begin{tabular}{|c|c|}
|
||||
\hline
|
||||
Parameter & Power \\ \hline
|
||||
0 & -4 dBm \\ \hline
|
||||
1 & -1 dBm \\ \hline
|
||||
2 & +2 dBm \\ \hline
|
||||
3 & +5 dBm \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
Mirny and Almazny output channels are paired, and Almazny output channels output twice the frequency of the main Mirny outputs. To set Almazny HF outputs for 4457 HF Synthesizer, set the Mirny outputs to one-half the desired frequency. The above code, run with 4457 HF Synthesizer, will also output 2GHz from Almazny HF0.
|
||||
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the folowing line.
|
||||
|
||||
\subsection{ADF5356 power control}
|
||||
Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
|
||||
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
|
||||
|
||||
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
|
||||
\newpage
|
||||
\subsection{Periodic 100\textmu s pulses}
|
||||
The output can be toggled on and off periodically using the RF switches.
|
||||
The following code emits a 100\textmu s pulse in every millisecond.
|
||||
A microwave signal should be programmed in prior (such as the 1 GHz wave example).
|
||||
|
||||
The parameter corresponds to a specific change of output power according to the following table\repeatfootnote{adf5356}.
|
||||
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Power changes from ADF5356}
|
||||
\begin{tabular}{|c|c|}
|
||||
\hline
|
||||
Parameter & Power \\ \hline
|
||||
0 & -4 dBm \\ \hline
|
||||
1 & -1 dBm \\ \hline
|
||||
2 & +2 dBm \\ \hline
|
||||
3 & +5 dBm \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 4456 Synthesizer Mirny in the ARTIQ Sinara crate configuration tool.
|
||||
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
|
||||
|
||||
\subsection{Periodic 100\textmu s pulses}
|
||||
The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
|
||||
|
||||
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
|
||||
|
||||
\ordersection{4456 Synthesizer Mirny or 4457 HF Synthesizer Mirny + Almazny}
|
||||
|
||||
\finalfootnote
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
394
5108.tex
394
5108.tex
@ -1,10 +1,29 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/5108}{images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfigure}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\title{5108 ADC Sampler}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2025}
|
||||
\revision{Revision 2}
|
||||
\date{January 2022}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -12,35 +31,48 @@
|
||||
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{8-channel ADC}
|
||||
\item{16-bits resolution}
|
||||
\item{1.5 MSPS simultaneously on all channels}
|
||||
\item{Full scale input voltage, $\pm$10mV to $\pm$10V}
|
||||
\item{BNC connector}
|
||||
\item{SMA breakout with 5528 SMA-IDC adapter}
|
||||
\end{itemize}
|
||||
\begin{itemize}
|
||||
\item{8-channel ADC.}
|
||||
\item{16-bits resolution.}
|
||||
\item{1.5 MSPS simultaneously on all channels.}
|
||||
\item{Full scale input voltage $\pm$10mV to $\pm$10V.}
|
||||
\item{BNC connector.}
|
||||
\item{SMA breakout with 5528 SMA-IDC adapter.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Sample intermediate-frequency (IF) waveform}
|
||||
\item{Monitor laser power with a photodiode}
|
||||
\item{Synchronize laser frequencies with a phase frequency detector}
|
||||
\item{Form a laser intensity servo with 4410 Urukul}
|
||||
\end{itemize}
|
||||
\begin{itemize}
|
||||
\item{Sample intermediate-frequency (IF) waveform.}
|
||||
\item{Monitor laser power with a photodiode.}
|
||||
\item{Synchronize laser frequencies with a phase frequency detector.}
|
||||
\item{Form a laser intensity servo with 4410 Urukul.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 5108 ADC Sampler is a 8hp EEM module part of the ARTIQ Sinara family.
|
||||
It adds analog-digital converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
The 5108 ADC Sampler is an 8hp EEM module, part of the ARTIQ/Sinara family. It adds analog-digital converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. It can also be combined with 4410 DDS Urukul to form the ARTIQ SU-Servo configuration.
|
||||
It provides 8 analog-to-digital channels, each exposed by a BNC connector.
|
||||
Each channel supports input voltage ranges from \textpm 10mV to \textpm 10V.
|
||||
All channels can be sampled simultaneously.
|
||||
Channels can broken out to SMA by adding a 5528 SMA-IDC card.
|
||||
|
||||
It provides eight analog-to-digital channels, exposed by eight BNC connectors. Each channel supports input voltage ranges from \textpm 10mV to \textpm 10V. All channels can be sampled simultaneously. Channels can broken out to SMA by adding a 5528 SMA-IDC card.
|
||||
|
||||
5108 ADC Sampler provides a sample rate of 1.5 MSPS. However, the sample rate in practice is typically limited by the use of ARTIQ-Python kernel code.
|
||||
5108 ADC Sampler provides a sample rate of 1.5 MSPS.
|
||||
However, the sample rate in practice is typically limited by the use of ARTIQ-Python kernel code.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
|
||||
\newcommand{\inputcolorboxminted}[2]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#1, gobble=4]{python}{#2}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{1}{
|
||||
@ -126,11 +158,11 @@
|
||||
\end{scope}
|
||||
|
||||
% Draw termination switches
|
||||
\draw (1.0, 1.925) node[twoportshape,t=\fourcm{100k/50\textOmega}{Switch \phantom{s} x8}, circuitikz/bipoles/twoport/width=1.5, scale=0.5] (termswitch) {};
|
||||
\draw (1.0, 1.925) node[twoportshape,t=\MymyLabel{100k/50\textOmega}{Switch \phantom{s} x8}, circuitikz/bipoles/twoport/width=1.5, scale=0.5] (termswitch) {};
|
||||
\begin{scope}[xshift=1.2cm, yshift=1.925cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% Dwar IDC Port (ADC IN)
|
||||
@ -138,14 +170,14 @@
|
||||
|
||||
% Draw PGIAs
|
||||
% The connections are too complicated for the usual buffer/op-amp symbol
|
||||
\draw (3, 2.45) node[twoportshape,t=\fourcm{CH 0}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia0) {};
|
||||
\draw (3, 1.75) node[twoportshape,t=\fourcm{CH 1}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia1) {};
|
||||
\draw (3, 1.05) node[twoportshape,t=\fourcm{CH 2}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia2) {};
|
||||
\draw (3, 0.35) node[twoportshape,t=\fourcm{CH 3}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia3) {};
|
||||
\draw (3, -0.35) node[twoportshape,t=\fourcm{CH 4}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia4) {};
|
||||
\draw (3, -1.05) node[twoportshape,t=\fourcm{CH 5}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia5) {};
|
||||
\draw (3, -1.75) node[twoportshape,t=\fourcm{CH 6}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia6) {};
|
||||
\draw (3, -2.45) node[twoportshape,t=\fourcm{CH 7}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia7) {};
|
||||
\draw (3, 2.45) node[twoportshape,t=\MymyLabel{CH 0}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia0) {};
|
||||
\draw (3, 1.75) node[twoportshape,t=\MymyLabel{CH 1}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia1) {};
|
||||
\draw (3, 1.05) node[twoportshape,t=\MymyLabel{CH 2}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia2) {};
|
||||
\draw (3, 0.35) node[twoportshape,t=\MymyLabel{CH 3}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia3) {};
|
||||
\draw (3, -0.35) node[twoportshape,t=\MymyLabel{CH 4}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia4) {};
|
||||
\draw (3, -1.05) node[twoportshape,t=\MymyLabel{CH 5}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia5) {};
|
||||
\draw (3, -1.75) node[twoportshape,t=\MymyLabel{CH 6}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia6) {};
|
||||
\draw (3, -2.45) node[twoportshape,t=\MymyLabel{CH 7}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia7) {};
|
||||
|
||||
% Draw termination connection to input lines
|
||||
\draw [-] (0.65, 1.675) -- (0.65, 1.225);
|
||||
@ -178,7 +210,7 @@
|
||||
\draw [-latexslim] (bnc7.east) -- (1.9, -1.225) -- (1.9, -2.45) -- (pgia7.west);
|
||||
|
||||
% Draw shift register & ADC
|
||||
\draw (4.7, 1) node[twoportshape,t=\fourcm{Shift}{Registers}, circuitikz/bipoles/twoport/width=1.6, scale=0.6, rotate=-90] (sr) {};
|
||||
\draw (4.7, 1) node[twoportshape,t=\MymyLabel{Shift}{Registers}, circuitikz/bipoles/twoport/width=1.6, scale=0.6, rotate=-90] (sr) {};
|
||||
\draw (4.7, -1) node[twoportshape,t={ADC}, circuitikz/bipoles/twoport/width=1.6, scale=0.6, rotate=-90] (adc) {};
|
||||
|
||||
% Connect PGIA -> ADC paths
|
||||
@ -202,7 +234,7 @@
|
||||
\draw [latexslim-] (3.45, -1.85) -- ++ (0.35, 0);
|
||||
|
||||
% Draw LVDS transceivers & repeaters
|
||||
\draw (6.3, 1) node[twoportshape,t=\fourcm{LVDS}{Transceivers}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (lvds) {};
|
||||
\draw (6.3, 1) node[twoportshape,t=\MymyLabel{LVDS}{Transceivers}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (lvds) {};
|
||||
\draw (6.3, -1) node[twoportshape,t={Repeaters}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (rep) {};
|
||||
|
||||
% ADC & SR connection lines
|
||||
@ -250,19 +282,17 @@
|
||||
\caption{Simplified Block Diagram}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[height=2.3in]{photo5108.jpg}
|
||||
\includegraphics[height=2.5in, angle=90]{Sampler_FP.jpg}
|
||||
\caption{Sampler card and front panel}
|
||||
\includegraphics[height=1.9in]{Sampler_FP.jpg}
|
||||
\includegraphics[height=1.9in]{photo5108.jpg}
|
||||
\caption{Sampler Card photo}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{5108 ADC Sampler}{https://github.com/sinara-hw/Sampler}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
\begin{table}[h]
|
||||
@ -290,9 +320,9 @@
|
||||
\end{table}
|
||||
|
||||
|
||||
The electrical characteristics are based on various test results\footnote{\label{sinara226}\url{https://github.com/sinara-hw/sinara/issues/226}}\textsuperscript{,}
|
||||
\footnote{\label{sinara489}\url{https://github.com/sinara-hw/sinara/issues/489}}\textsuperscript{,}
|
||||
\footnote{\label{sampler2}\url{https://github.com/sinara-hw/Sampler/issues/2}}.
|
||||
The electrical characteristics are based on various test results\footnote{\label{sinara226}https://github.com/sinara-hw/sinara/issues/226}\textsuperscript{,}
|
||||
\footnote{\label{sinara489}https://github.com/sinara-hw/sinara/issues/489}\textsuperscript{,}
|
||||
\footnote{\label{sampler2}https://github.com/sinara-hw/Sampler/issues/2}.
|
||||
|
||||
\begin{table}[hbt!]
|
||||
\centering
|
||||
@ -320,18 +350,6 @@ The electrical characteristics are based on various test results\footnote{\label
|
||||
& & 206.3 & & LSB RMS & Termination off \\
|
||||
% \hline
|
||||
DC cross-talk\repeatfootnote{sinara226} & & & -96 & dB & 1x gain\\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics (cont.)}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions / Comments} \\
|
||||
\hline
|
||||
% AC cross-talk data on wiki is also outdated (when it was still novo)
|
||||
% sinara-hw/sinara #489 is a better source of info
|
||||
@ -341,33 +359,49 @@ The electrical characteristics are based on various test results\footnote{\label
|
||||
& & -51 & & dBc & 0.1 V\textsubscript{pp} (-48dBFS), limited by ADC (-100dBFS) \\
|
||||
& & -69 & & dBc & 1 V\textsubscript{pp} (-28dBFS) \\
|
||||
& & -58.8 & & dBc & 10 V\textsubscript{pp} (-8dBFS) \\
|
||||
\hline
|
||||
Common-mode rejection ratio\repeatfootnote{sinara226} & & & & & 2 V\textsubscript{pp} sine wave as CM input, termination on\\
|
||||
\hspace{12mm} 1x gain & & & -98 & dB & $f=0.01,0.1,1$ kHz \\
|
||||
& & -87 & & dB & $f=10$ kHz \\
|
||||
& & -55 & & dB & $f=100$ kHz \\
|
||||
& & -83 & & dB & $f=1$ MHz \\
|
||||
& & -85 & & dB & $f=10$ MHz \\
|
||||
\cline{2-6}
|
||||
\hspace{12mm} 100x gain & & & -118 & dB & $f=0.01$ kHz \\
|
||||
& & -98 & & dB & $f=0.1$ kHz \\
|
||||
& & -88 & & dB & $f=1$ kHz \\
|
||||
& & -70 & & dB & $f=10$ kHz \\
|
||||
& & -50 & & dB & $f=100$ kHz \\
|
||||
& & -80 & & dB & $f=1$ MHz \\
|
||||
& & & -118 & dB & $f=10$ MHz \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\subsection{Channel crosstalk}
|
||||
\newpage
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics (cont.)}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions / Comments} \\
|
||||
\hline
|
||||
Common-mode rejection ratio\repeatfootnote{sinara226} & CMRR & & & & & 2 V\textsubscript{pp} sine wave as CM input, termination on\\
|
||||
\hspace{12mm} 1x gain & & & & -98 & dB & $f=0.01,0.1,1$ kHz \\
|
||||
& & & -87 & & dB & $f=10$ kHz \\
|
||||
& & & -55 & & dB & $f=100$ kHz \\
|
||||
& & & -83 & & dB & $f=1$ MHz \\
|
||||
& & & -85 & & dB & $f=10$ MHz \\
|
||||
\cline{3-7}
|
||||
\hspace{12mm} 100x gain & & & & -118 & dB & $f=0.01$ kHz \\
|
||||
& & & -98 & & dB & $f=0.1$ kHz \\
|
||||
& & & -88 & & dB & $f=1$ kHz \\
|
||||
& & & -70 & & dB & $f=10$ kHz \\
|
||||
& & & -50 & & dB & $f=100$ kHz \\
|
||||
& & & -80 & & dB & $f=1$ MHz \\
|
||||
& & & & -118 & dB & $f=10$ MHz \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
Crosstalk between ADC channels of 5108 ADC Sampler is shown below\repeatfootnote{sinara489}.
|
||||
|
||||
A 10 V\textsubscript{pp} signal was used as the input. The aggressor channel always has 1x gain. All channels have 50 \textOmega~termination enabled.
|
||||
A 10 V\textsubscript{pp} signal is the input.
|
||||
The aggressor channel always has 1x gain.
|
||||
All channels have 50 \textOmega~termination enabled.
|
||||
|
||||
Data was acquired by taking 512 samples at 80 kHz sampling rate 20 times to average out the FFT.
|
||||
Data is acquired by taking 512 samples at 80 kHz sampling rate 20 times to average out the FFT.
|
||||
|
||||
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
||||
|
||||
@ -421,7 +455,7 @@ Data was acquired by taking 512 samples at 80 kHz sampling rate 20 times to aver
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\clearpage
|
||||
\newpage
|
||||
|
||||
% The plots are quite small given that it is 8-plots-in-1, but the numbers should give a better picture
|
||||
\begin{figure}[hbt!]
|
||||
@ -459,7 +493,7 @@ Data was acquired by taking 512 samples at 80 kHz sampling rate 20 times to aver
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\clearpage
|
||||
\newpage
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
@ -467,14 +501,38 @@ Data was acquired by taking 512 samples at 80 kHz sampling rate 20 times to aver
|
||||
\caption{Crosstalk with 300 kHz input frequency, 1x gain on victim, channel 3 as the aggressor}
|
||||
\end{figure}
|
||||
|
||||
\subsection{Bandwidth}
|
||||
Noise density is measured using the following configuration\repeatfootnote{sampler2}:
|
||||
\begin{enumerate}
|
||||
\item 1/12\textmu s sampling rate
|
||||
\item 10k samples per measurement, averaging over 100 measurements
|
||||
\item Measured at channels 6 \& 7. Channel 6 has the 50\textOmega~termination on, channel 7 has it off
|
||||
\end{enumerate}
|
||||
Noise density with respect to different gain settings with termination on/off are plotted below.
|
||||
|
||||
Bandwidth of small signal and large signal input is shown below\repeatfootnote{sampler2}. The setup is as follows:
|
||||
\begin{multicols}{2}
|
||||
|
||||
\begin{figure}[H]
|
||||
\includegraphics[width=3.3in]{sampler_noise_term.png}
|
||||
\caption{Noise density with termination enabled}
|
||||
\end{figure}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{figure}[H]
|
||||
\includegraphics[width=3.3in]{sampler_noise_no_term.png}
|
||||
\caption{Noise density with termination disabled}
|
||||
\end{figure}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\newpage
|
||||
|
||||
Bandwidth of small signal and large signal input is shown below\repeatfootnote{sampler2}. The setup is as the following:
|
||||
\begin{enumerate}
|
||||
\itemsep0em
|
||||
\item 10k samples, sampled at 79.37 kHz
|
||||
\item Driven by sinusoid from Keysight 33500B generator; sampled using channel 7 without termination
|
||||
\item Small signal measured using 2V\textsubscript{pp}/gain; large signal measured using 15V\textsubscript{pp}/gain
|
||||
\item Driven by sinusoid from Keysight 33500B generator; Sampled using channel 7 without termination
|
||||
\item Small signal measured using 2V\textsubscript{pp}/gain; Large signal measured using 15V\textsubscript{pp}/gain
|
||||
\end{enumerate}
|
||||
\begin{multicols}{2}
|
||||
|
||||
@ -494,52 +552,160 @@ Bandwidth of small signal and large signal input is shown below\repeatfootnote{s
|
||||
|
||||
\newpage
|
||||
|
||||
\begin{multicols}{2}
|
||||
\section{Front Panel Drawings}
|
||||
\begin{multicols}{2}
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.7in]{sampler_drawings.pdf}
|
||||
\captionof{figure}{5108 ADC Sampler front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.7in]{sampler_assembly.pdf}
|
||||
\captionof{figure}{5108 ADC Sampler front panel assembly}
|
||||
\end{center}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90504202 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
|
||||
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (Assembled)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90504202 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
|
||||
2 & 3033098 & 0.04 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
|
||||
3 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
4 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
5 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
6 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
|
||||
7 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
|
||||
8 & 3207076 & 0.01 & SCR M2.5*12 PAN 100 21101-222 \\ \hline
|
||||
9 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT (100PCS) \\ \hline
|
||||
10 & 3211232 & 1 & SCR M2.5*14 PAN PHL SS \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\section{Configuring Termination}
|
||||
\begin{multicols}{2}
|
||||
The input termination can be configured by switches.
|
||||
The per-channel termination switches are found at the middle left part of the card.
|
||||
|
||||
The input termination must be configured by setting physical switches on the board. The termination switches are found at the middle left part of the card and by-channel. Setting these switches to \texttt{on} adds a 50\textOmega~termination between the differential input signals.
|
||||
Switching on the termination switch adds a 50\textOmega~termination between the differential input signals.
|
||||
|
||||
Regardless of switch configurations, the differential input signals are separately terminated with 100k\textOmega~to the PCB ground.
|
||||
|
||||
\vspace*{\fill}
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.7in]{sampler_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\sysdescsection
|
||||
|
||||
5108 Sampler should be entered into the peripherals list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "sampler",
|
||||
"ports": [0, 1]
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Replace 0 and 1 with the EEM port numbers used on the core device. Any ports can be used.
|
||||
Regardless of the switch configurations, the differential input signals are separately terminated with 100k\textOmega~to the PCB ground.
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.7in]{sampler_switches.jpg}
|
||||
\captionof{figure}{Position of switches}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\newpage
|
||||
|
||||
\codesection{5108 ADC Sampler}
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 5108 ADC Sampler card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
\subsection{Get input voltage}
|
||||
The following example initializes the Sampler card with 1x gain on all ADC channels. At the end all ADC channels are sampled.
|
||||
\subsection{Get input voltage}
|
||||
The following example initializes the Sampler card with 1x gain on all ADC channels.
|
||||
Sample all ADC channels at the end.
|
||||
|
||||
\inputcolorboxminted{firstline=9,lastline=21}{examples/sampler.py}
|
||||
\inputcolorboxminted{firstline=9,lastline=21}{examples/sampler.py}
|
||||
|
||||
% Direct input to avoid issues with minted
|
||||
\input{shared/suservo.tex}
|
||||
\subsection{Voltage-controlled DDS Amplitude (SU-Servo Only)}
|
||||
The SU-Servo feature can be enabled by integrating the 5108 ADC Sampler with 4410 DDS Urukuls.
|
||||
Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function.
|
||||
\[H(s)=k_p+\frac{k_i}{s+\frac{k_i}{g}}\]
|
||||
In the following example, the amplitude of DDS is proportional to the ADC input from Sampler.
|
||||
First, initialize the RTIO, SU-Servo and its channel with 1x gain.
|
||||
|
||||
\ordersection{5108 ADC Sampler}
|
||||
\inputcolorboxminted{firstline=10,lastline=17}{examples/suservo.py}
|
||||
|
||||
\finalfootnote
|
||||
Next, setup the PI control as an IIR filter. It has -1 proportional gain $k_p$ and no integrator gain $k_i$.
|
||||
|
||||
\inputcolorboxminted{firstline=18,lastline=25}{examples/suservo.py}
|
||||
|
||||
Then, configure the DDS frequency to 10 MHz with 3V input offset.
|
||||
When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
|
||||
|
||||
\inputcolorboxminted{firstline=26,lastline=30}{examples/suservo.py}
|
||||
|
||||
SU-Servo encodes the ADC voltage in a linear scale [-1, 1].
|
||||
Therefore, 3V is converted to 0.3.
|
||||
Note that the ASF of all DDS channels are capped at 1.0, the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
|
||||
|
||||
Finally, enable the SU-Servo channel with the IIR filter programmed beforehand.
|
||||
|
||||
\inputcolorboxminted{firstline=32,lastline=33}{examples/suservo.py}
|
||||
|
||||
A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC.
|
||||
The RMS voltage of the DDS channel against the ADC voltage is plotted.
|
||||
The DDS channel is terminated with 50\textOmega.
|
||||
|
||||
\begin{center}
|
||||
\begin{tikzpicture}[
|
||||
declare function={
|
||||
func(\x)= and(\x>=-10, \x<-7) * (160) +
|
||||
and(\x>=-7, \x<3) * (16*(3-x)) +
|
||||
and(\x>=3, \x<10) * (0);
|
||||
}
|
||||
]
|
||||
\begin{axis}[
|
||||
axis x line=middle, axis y line=middle,
|
||||
every axis x label/.style={
|
||||
at={(axis description cs:0.5,-0.1)},
|
||||
anchor=north,
|
||||
},
|
||||
every axis y label/.style={
|
||||
at={(ticklabel* cs:1.05)},
|
||||
anchor=south,
|
||||
},
|
||||
minor x tick num=3,
|
||||
grid=both,
|
||||
height=8cm,
|
||||
width=12cm,
|
||||
ymin=-5, ymax=180, ytick={0,16,...,160}, ylabel=DDS RMS Voltage ($mV_{rms}$),
|
||||
xmin=-10, xmax=10, xtick={-10,-8,...,10}, xlabel=Sampler Voltage ($V$),
|
||||
]
|
||||
|
||||
\addplot[very thick, blue, samples=21, domain=-10:10]{func(x)};
|
||||
\end{axis}
|
||||
\end{tikzpicture}
|
||||
\end{center}
|
||||
|
||||
DDS signal should be attenuated.
|
||||
High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power.
|
||||
15 dB attenuation at the digital attenuator was applied in this example.
|
||||
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 5108 ADC Sampler in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
362
5432.tex
362
5432.tex
@ -1,11 +1,29 @@
|
||||
\input{preamble.tex}
|
||||
\input{shared/dactino.tex}
|
||||
\graphicspath{{images/5432}, {images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfig}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\title{5432 DAC Zotino}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2025}
|
||||
\revision{Revision 3}
|
||||
\date{January 2022}
|
||||
\revision{Revision 2}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -13,28 +31,44 @@
|
||||
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{32-channel DAC}
|
||||
\item{16-bit resolution}
|
||||
\item{1 MSPS shared between all channels}
|
||||
\item{Output voltage ±10V}
|
||||
\item{HD68 connector}
|
||||
\item{Can be broken out to BNC/SMA/MCX}
|
||||
\end{itemize}
|
||||
\begin{itemize}
|
||||
\item{32-channel DAC.}
|
||||
\item{16-bits resolution.}
|
||||
\item{1 MSPS shared between all channels.}
|
||||
\item{Output voltage $\pm$10V.}
|
||||
\item{HD68 connector.}
|
||||
\item{Can be broken out to BNC/SMA/MCX.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Low-frequency arbitrary waveform generation}
|
||||
\item{Driving coil amplifiers for magnetic field control}
|
||||
\item{Driving DC electrodes in ion traps}
|
||||
\end{itemize}
|
||||
\begin{itemize}
|
||||
\item{Controlling setpoints of PID controllers for laser power stabilization.}
|
||||
\item{Low-frequency arbitrary waveform generation.}
|
||||
\item{Driving DC electrodes in ion traps.}
|
||||
\end{itemize}
|
||||
|
||||
\generaldescription{5432 DAC Zotino}{high-speed 5632 DAC Fastino}
|
||||
\section{General Description}
|
||||
The 5432 Zotino is a 4hp EEM module part of the ARTIQ Sinara family.
|
||||
It adds digital-analog converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
It provides 4 groups of 8 analog channels each, exposed by 1 HD68 connector.
|
||||
Each channel supports output voltage from -10 V to 10 V.
|
||||
All channels can be updated simultaneously.
|
||||
Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
|
||||
\newcommand{\inputcolorboxminted}[2]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#1, gobble=4]{python}{#2}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{0.88}{
|
||||
@ -44,20 +78,20 @@
|
||||
\draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
|
||||
|
||||
% IDC Connectors to IDC cards
|
||||
\draw (2.2, 1.2) node[twoportshape, t={\twocm{IDC}{DAC 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) {};
|
||||
\draw (1.4, 1.2) node[twoportshape, t={\twocm{IDC}{DAC 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) {};
|
||||
\draw (2.2, -1.2) node[twoportshape, t={\twocm{IDC}{DAC 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) {};
|
||||
\draw (1.4, -1.2) node[twoportshape, t={\twocm{IDC}{DAC 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) {};
|
||||
\draw (2.2, 1.2) node[twoportshape, t={\MyLabel{IDC}{DAC 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) {};
|
||||
\draw (1.4, 1.2) node[twoportshape, t={\MyLabel{IDC}{DAC 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) {};
|
||||
\draw (2.2, -1.2) node[twoportshape, t={\MyLabel{IDC}{DAC 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) {};
|
||||
\draw (1.4, -1.2) node[twoportshape, t={\MyLabel{IDC}{DAC 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) {};
|
||||
|
||||
% Op-amp x32
|
||||
\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
|
||||
|
||||
% DAC AD5372
|
||||
\draw (4.6, 0.2) node[twoportshape, t=\twocm{32-CH}{DAC}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (dac) {};
|
||||
\draw (4.6, 0.2) node[twoportshape, t=\MyLabel{32-CH}{DAC}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (dac) {};
|
||||
|
||||
% LVDS Transceivers
|
||||
\draw (6.6, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
|
||||
\draw (6.6, -1.6) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
|
||||
\draw (6.6, 0) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
|
||||
\draw (6.6, -1.6) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
|
||||
|
||||
% Aesthetic EEPROM
|
||||
\draw (6.6, 1.6) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eeprom) {};
|
||||
@ -88,15 +122,15 @@
|
||||
|
||||
% TEC Cooler on top of the DAC
|
||||
% To make it more obvious that it is cooling the DAC
|
||||
\draw (4.6, 1.45) node[twoportshape, t=\fourcm{TEC}{Cooler}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (tec_cooler) {};
|
||||
\draw (4.6, 1.45) node[twoportshape, t=\MymyLabel{TEC}{Cooler}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (tec_cooler) {};
|
||||
|
||||
% TEC Controller lined up with EEM IN
|
||||
\draw (8.2, 3.5) node[twoportshape, t=\fourcm{TEC Controller}{Connector}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (tec_conn) {};
|
||||
\draw (8.2, 3.5) node[twoportshape, t=\MymyLabel{TEC Controller}{Connector}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (tec_conn) {};
|
||||
|
||||
% Thermistor for TEC controller
|
||||
\draw (6.6, 3.3) node[thermistorshape, scale=0.7, rotate=-90] (thermistor) {};
|
||||
\draw [latexslim-] (7.85, 3.3) -- (6.75, 3.3);
|
||||
|
||||
|
||||
% Connect the controller to the cooler
|
||||
\draw [-latexslim] (7.85, 4.2) -- (4.6, 4.2) -- (tec_cooler.north);
|
||||
|
||||
@ -109,145 +143,193 @@
|
||||
\caption{Simplified Block Diagram}
|
||||
\end{figure}
|
||||
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[height=2in]{Zotino_FP.jpg}
|
||||
\includegraphics[height=2in]{photo5432.jpg}
|
||||
\caption{Zotino card photograph}
|
||||
\end{figure}
|
||||
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=2.3in, angle=90]{Zotino_FP.jpg}
|
||||
\caption{Zotino front panel}
|
||||
\caption{Zotino Card photo}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{5432 DAC Zotino}{https://github.com/sinara-hw/Zotino/}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
% \hypersetup{hidelinks}
|
||||
% \urlstyle{same}
|
||||
These specifications are based on the datasheet of the DAC IC
|
||||
(AD5372\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}}),
|
||||
and various information from the Sinara wiki\footnote{\label{zotino_wiki}\url{https://github.com/sinara-hw/Zotino/wiki}}.
|
||||
% \hypersetup{hidelinks}
|
||||
% \urlstyle{same}
|
||||
The specifications are based on the datasheet of the DAC IC
|
||||
(AD5372BCPZ\footnote{\label{dac}https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}),
|
||||
and various information from Sinara wiki\footnote{\label{zotino_wiki}https://github.com/sinara-hw/Zotino/wiki}.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
Sampling rate & & 1 & & MSPS & shared across channels \\
|
||||
\hline
|
||||
Output voltage & -10 & & 10 & V & \\
|
||||
\hline
|
||||
Output impedance\repeatfootnote{zotino_wiki} & \multicolumn{4}{c|}{470 $\Omega$ $||$ 2.2nF} & \\
|
||||
\hline
|
||||
Resolution\repeatfootnote{dac} & & 16 & & bits & \\
|
||||
\hline
|
||||
3dB bandwidth\repeatfootnote{zotino_wiki} & & 75 & & kHz & \\
|
||||
\hline
|
||||
Power consumption\repeatfootnote{zotino_wiki} & 3 & & 8.7 & W & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Output voltage & -10 & & 10 & V & \\
|
||||
\hline
|
||||
Output impedance\repeatfootnote{zotino_wiki} & \multicolumn{4}{c|}{470 $\Omega$ $||$ 2.2nF} & \\
|
||||
\hline
|
||||
Resolution\repeatfootnote{dac} & & 16 & & bits & \\
|
||||
\hline
|
||||
3dB bandwidth\repeatfootnote{zotino_wiki} & & 75 & & kHz & \\
|
||||
\hline
|
||||
Power consumption\repeatfootnote{zotino_wiki} & 3 & & 8.7 & W & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
The following table records the cross-talk and transient behavior of Zotino\footnote{\label{zotino21}\url{https://github.com/sinara-hw/Zotino/issues/21}}. In terms of output noise, measurements were made after a 15-cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF\footnote{\label{zotino27}\url{https://github.com/sinara-hw/Zotino/issues/27}}. DAC output during noise measurement was 3.5 V.
|
||||
The following are cross-talk and transient behavior of Zotino\footnote{\label{zotino21}https://github.com/sinara-hw/Zotino/issues/21}.
|
||||
In terms of output noise, it was measured after 15 cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF\footnote{\label{zotino27}https://github.com/sinara-hw/Zotino/issues/27}.
|
||||
The DAC output during noise measurement is 3.5 V.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions / Comments} \\
|
||||
\hline
|
||||
DC cross-talk\repeatfootnote{zotino21} & & -116 & & dB & \\
|
||||
\hline
|
||||
Fall-time\repeatfootnote{zotino21} & & 18.5 & & $\mu$s & 10\% to 90\% fall-time \\
|
||||
& & 25 & & $\mu$s & 1\% to 99\% fall-time \\
|
||||
\hline
|
||||
Negative overshoot\repeatfootnote{zotino21} & & 0.5\% & & - & \\
|
||||
\hline
|
||||
Rise-time\repeatfootnote{zotino21} & & 30 & & $\mu$s & 1\% to 99\% rise-time \\
|
||||
\hline
|
||||
Positive overshoot\repeatfootnote{zotino21} & & 0.65\% & & - & \\
|
||||
\hline
|
||||
Output noise\repeatfootnote{zotino27} & & & & & \\
|
||||
\hspace{18mm} @ 100 Hz & & 500 & & nV/rtHz & 6.9 Hz bandwidth \\
|
||||
\hspace{18mm} @ 300 Hz & & 300 & & nV/rtHz & 6.9 Hz bandwidth \\
|
||||
\hspace{18mm} @ 50 kHz & & 210 & & nV/rtHz & 6.9 kHz bandwidth \\
|
||||
\hspace{18mm} @ 1 MHz & & 4.6 & & nV/rtHz & 6.9 kHz bandwidth \\
|
||||
\hspace{18mm} $>$ 4 MHz & & & 1 & nV/rtHz & 6.9 kHz bandwidth \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions / Comments} \\
|
||||
\hline
|
||||
DC cross-talk\repeatfootnote{zotino21} & & -116 & & dB & \\
|
||||
\hline
|
||||
Fall-time\repeatfootnote{zotino21} & & 18.5 & & $\mu$s & 10\% to 90\% fall-time \\
|
||||
& & 25 & & $\mu$s & 1\% to 99\% fall-time \\
|
||||
\hline
|
||||
Negative overshoot\repeatfootnote{zotino21} & & 0.5\% & & - & \\
|
||||
\hline
|
||||
Rise-time\repeatfootnote{zotino21} & & 30 & & $\mu$s & 1\% to 99\% rise-time \\
|
||||
\hline
|
||||
Positive overshoot\repeatfootnote{zotino21} & & 0.65\% & & - & \\
|
||||
\hline
|
||||
Output noise\repeatfootnote{zotino27} & & & & & \\
|
||||
\hspace{18mm} @ 100 Hz & & 500 & & nV/rtHz & 6.9 Hz bandwidth \\
|
||||
\hspace{18mm} @ 300 Hz & & 300 & & nV/rtHz & 6.9 Hz bandwidth \\
|
||||
\hspace{18mm} @ 50 kHz & & 210 & & nV/rtHz & 6.9 kHz bandwidth \\
|
||||
\hspace{18mm} @ 1 MHz & & 4.6 & & nV/rtHz & 6.9 kHz bandwidth \\
|
||||
\hspace{18mm} $>$ 4 MHz & & & 1 & nV/rtHz & 6.9 kHz bandwidth \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
Step response was found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observing the waveform\repeatfootnote{zotino21}.
|
||||
Step response are found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observe the waveform\repeatfootnote{zotino21}.
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\subfloat[\centering Switching from -10V to +10V]{{
|
||||
\includegraphics[height=1.8in]{zotino_step_response_rising.png}
|
||||
}}%
|
||||
\subfloat[\centering Switching from +10V to -10V]{{
|
||||
\includegraphics[height=1.8in]{zotino_step_response_falling.png}
|
||||
}}%
|
||||
\caption{Step response}%
|
||||
\end{figure}
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\subfloat[\centering Switching from -10V to +10V]{{
|
||||
\includegraphics[height=1.8in]{zotino_step_response_rising.png}
|
||||
}}%
|
||||
\subfloat[\centering Switching from +10V to -10V]{{
|
||||
\includegraphics[height=1.8in]{zotino_step_response_falling.png}
|
||||
}}%
|
||||
\caption{Step response}%
|
||||
\end{figure}
|
||||
|
||||
Far-end crosstalk was measured using the following setup\repeatfootnote{zotino21}:
|
||||
Far-end crosstalk is measured using the following setup\repeatfootnote{zotino21}.
|
||||
|
||||
\begin{enumerate}
|
||||
\item CH1 as aggressor, CH0 as victim
|
||||
\item CH0, 2-7 terminated, CH 8-31 open
|
||||
\item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables and connectors.
|
||||
\end{enumerate}
|
||||
\begin{enumerate}
|
||||
\item CH1 as aggressor, CH0 as victim
|
||||
\item CH0, 2-7 terminated, CH 8-31 open
|
||||
\item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables \& connectors.
|
||||
\end{enumerate}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[width=3.3in]{zotino_fext.png}
|
||||
\caption{Step crosstalk}
|
||||
\end{figure}
|
||||
|
||||
\section{LEDs}
|
||||
|
||||
5432 DAC Zotino provides eight user LEDs in the front panel. These are directly accessible in ARTIQ RTIO.
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[width=3.3in]{zotino_fext.png}
|
||||
\caption{Step crosstalk}
|
||||
\end{figure}
|
||||
|
||||
\newpage
|
||||
|
||||
\sysdescsection
|
||||
\section{Front Panel Drawings}
|
||||
\begin{multicols}{2}
|
||||
|
||||
5432 DAC Zotino should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=3in]{zotino_drawings.pdf}
|
||||
\captionof{figure}{5432 DAC Zotino front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "zotino",
|
||||
"ports": [0]
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90503572 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
|
||||
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
Replace 0 with the EEM port used on the core device. Any port may be used.
|
||||
\columnbreak
|
||||
|
||||
\codesectiondactino{5432 DAC Zotino}{Zotino}{zotino.py}
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=3in]{zotino_assembly.pdf}
|
||||
\captionof{figure}{5432 DAC Zotino front panel assembly}
|
||||
\end{center}
|
||||
|
||||
\ordersection{5432 DAC Zotino}
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (Assembled)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90503572 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
|
||||
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
|
||||
5 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
|
||||
6 & 3040012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
|
||||
7 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
|
||||
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\finalfootnote
|
||||
\end{multicols}
|
||||
\newpage
|
||||
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 5432 DAC Zotino card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
\subsection{Set output voltage}
|
||||
The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channel 0, 1, 2, 3 respectively.
|
||||
Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
|
||||
|
||||
\inputcolorboxminted{firstline=11,lastline=22}{examples/zotino.py}
|
||||
|
||||
\newpage
|
||||
|
||||
\subsection{Triangular Wave}
|
||||
A triangular waveform at 10 Hz, 16 V peak-to-peak.
|
||||
Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
|
||||
|
||||
Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.
|
||||
|
||||
\inputcolorboxminted{firstline=30,lastline=49}{examples/zotino.py}
|
||||
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 5432 DAC Zotino in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
198
5518-5528.tex
198
5518-5528.tex
@ -1,5 +1,25 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/5518-5528}{images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfig}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usepackage{pifont}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\title{5518 BNC-IDC / 5528 SMA-IDC}
|
||||
\author{M-Labs Limited}
|
||||
@ -13,31 +33,44 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{8 channels}
|
||||
\item{Internal IDC connector}
|
||||
\item{External BNC or SMA connectors}
|
||||
\item{8 channels.}
|
||||
\item{Internal IDC connector.}
|
||||
\item{External BNC or SMA connectors.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Break out analog signals}
|
||||
\item{Breaks out analog signals.}
|
||||
\item{BNC or SMA adapters for: \begin{itemize}
|
||||
\item{5432 DAC Zotino}
|
||||
\item{5632 DAC Fastino}
|
||||
\end{itemize}}
|
||||
\item{(5528 only) SMA adapter for 5108 Sampler}
|
||||
\item{Convert from/to HD68 with 5568 HD68-IDC}
|
||||
\item{(5528 only) SMA adapter for 5108 Sampler.}
|
||||
\item{Convert from/to HD68 with 5568 HD68-IDC.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 5518 BNC-IDC card is a 8hp EEM module; the 5528 SMA-IDC card is a 4hp EEM module. Both adapter cards break out analog signals from IDC connectors to BNC (5518) or SMA (5528). IDC connectors can be found on 5108 Sampler, 5432 DAC Zotino, 5632 DAC Fastino and 5568 HD68-IDC.
|
||||
The 5518 BNC-IDC card is a 8hp EEM module, while the 5528 SMA-IDC card is a 4hp EEM module.
|
||||
Both adapter cards break out analog signal from IDC connectors to BNC (5518) or SMA (5528).
|
||||
IDC connectors can be found on 5108 Sampler, 5432 DAC Zotino, 5632 DAC Fastino \& 5568 HD68-IDC.
|
||||
|
||||
Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking out all 32 channels of 5432 DAC Zotino, 5632 DAC Fastino or 5568 HD68-IDC requires four BNC/SMA-IDC cards. Breaking out all 8 ADC channels of 5108 Sampler requires only one BNC/SMA-IDC card.
|
||||
Each card provides 8 channels, with BNC (5518) or SMA (5528) connectors.
|
||||
Breaking out all 32 channels from 5432 DAC Zotino, 5632 DAC Fastino or 5568 HD68-IDC requires 4 BNC/SMA-IDC cards.
|
||||
Only 1 BNC/SMA-IDC is required to break out all 8 ADC channels from a 5108 Sampler.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
|
||||
\newcommand{\inputcolorboxminted}[2]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#1, gobble=4]{python}{#2}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{0.95}{
|
||||
@ -93,14 +126,14 @@ Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking
|
||||
\draw (0,0) circle(1.5);
|
||||
\clip (-0.8,0) rectangle (0.8,0.8);
|
||||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
\end{scope}
|
||||
\begin{scope}[scale=0.07 , rotate=-90, xshift=-5cm, yshift=2cm]
|
||||
\draw (0,0.65) -- (0,3);
|
||||
\clip (-1.5,0) rectangle (1.5,1.5);
|
||||
\draw (0,0) circle(1.5);
|
||||
\clip (-0.8,0) rectangle (0.8,0.8);
|
||||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
\end{scope}
|
||||
\begin{scope}[scale=0.07 , rotate=-90, xshift=-15cm, yshift=2cm]
|
||||
\draw (0,0.65) -- (0,3);
|
||||
\clip (-1.5,0) rectangle (1.5,1.5);
|
||||
@ -124,9 +157,9 @@ Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking
|
||||
\end{scope}
|
||||
|
||||
% Draw CH0, CH1 & CH7 CM chokes
|
||||
\draw (3, 1.2) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm0) {};
|
||||
\draw (3, 0.4) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm1) {};
|
||||
\draw (3, -1.1) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm7) {};
|
||||
\draw (3, 1.2) node[twoportshape, t=\MymyLabel{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm0) {};
|
||||
\draw (3, 0.4) node[twoportshape, t=\MymyLabel{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm1) {};
|
||||
\draw (3, -1.1) node[twoportshape, t=\MymyLabel{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm7) {};
|
||||
|
||||
% Omission dots for other channels
|
||||
\node at (3, -0.15)[circle,fill,inner sep=0.7pt]{};
|
||||
@ -167,12 +200,15 @@ Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\subfloat[\centering BNC-IDC]{{
|
||||
\includegraphics[height=2.5in]{BNC_IDC_FP.jpg}
|
||||
\includegraphics[height=2.5in]{photo5518.jpg}
|
||||
}}%
|
||||
\subfloat[\centering SMA-IDC]{{
|
||||
\includegraphics[height=2.6in]{photo5528.jpg}
|
||||
\quad
|
||||
\includegraphics[height=2.5in]{SMA_IDC_FP.pdf}
|
||||
\quad
|
||||
}}%
|
||||
\caption{BNC-IDC/SMA-IDC card photos}%
|
||||
\caption{BNC-IDC/SMA-IDC Card photos}%
|
||||
\label{fig:example}%
|
||||
\end{figure}
|
||||
|
||||
@ -180,41 +216,39 @@ Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesectiond{5518 BNC-IDC}{5528 SMA-IDC}{https://github.com/sinara-hw/BNC\_IDC}{https://github.com/sinara-hw/SMA\_IDC\_Adapter}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
Specifications of parameters are based on the datasheet of the
|
||||
common mode line filter\footnote{\label{cm_choke}\url{https://www.we-online.com/catalog/datasheet/744229.pdf}}.
|
||||
common mode line filter\footnote{\label{cm_choke}https://www.we-online.com/catalog/datasheet/744229.pdf}.
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Specifications}
|
||||
\begin{tabularx}{0.65\textwidth}{l | c | c | X}
|
||||
\begin{tabularx}{0.65\textwidth}{l | c | c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Max. Value} & \textbf{Unit} & \textbf{Conditions} \\
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Max. Value} & \textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Rated voltage & 80 & V & \\
|
||||
Rated voltage & $V_{R}$ & 80 & V & \\
|
||||
\hline
|
||||
Rated current & 400 & mA & $\Delta T^{*}=40K$ \\
|
||||
Rated current & $I_{R}$ & 400 & mA & $\Delta T^{*}=40K$ \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
*$\Delta T$ refers to the temperature of the CM line filter minus the ambient.
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
Impedance characteristics of common mode \& differential mode signal at different frequencies are shown in the following graph:
|
||||
Impedance characteristics of common mode \& differential mode signal at different frequencies are shown in the following graph.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[height=4.8in]{idc_cm_choke.jpg}
|
||||
\includegraphics[]{idc_cm_choke.pdf}
|
||||
\caption{Common Mode Line Filter Impedance Characteristics}
|
||||
\end{figure}
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Channel Mapping}
|
||||
The following table shows the corresponding channel numbers of the BNC/SMA-IDC adapter IO ports when connected to Sinara cards that support IDC connections.
|
||||
The following table shows the corresponding channel number of the BNC/SMA-IDC adapter IO ports, when it is connected to Sinara cards that support IDC connections.
|
||||
\begin{table}[h]
|
||||
\caption{Channel Mapping of BNC/SMA-IDC to Zotino, Fastino \& HD68-IDC}
|
||||
\centering
|
||||
@ -233,14 +267,118 @@ The following table shows the corresponding channel numbers of the BNC/SMA-IDC a
|
||||
\centering
|
||||
\begin{tabular}{|l|l|l|l|l|l|l|l|l|}
|
||||
\hline
|
||||
& IO 0 & IO 1 & IO 2 & IO 3 & IO 4 & IO 5 & IO 6 & IO 7 \\ \hline
|
||||
& IO 0 & IO 1 & IO 2 & IO 3 & IO 4 & IO 5 & IO 6 & IO 7 \\ \hline
|
||||
Sampler Ch. & \multicolumn{1}{c|}{7} & \multicolumn{1}{c|}{6} & \multicolumn{1}{c|}{5} & \multicolumn{1}{c|}{4} & \multicolumn{1}{c|}{3} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{0} \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
\ordersection{5518 BNC-IDC/5528 SMA-IDC}
|
||||
\section{Front Panel Drawings}
|
||||
|
||||
\finalfootnote
|
||||
\begin{multicols}{2}
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.7in]{bnc_idc_drawings.pdf}
|
||||
\captionof{figure}{5518 BNC-IDC front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (5518 Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90506946 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
|
||||
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.7in]{bnc_idc_assembly.pdf}
|
||||
\captionof{figure}{5518 BNC-IDC front panel assembly}
|
||||
\end{center}
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (5518 Assembled)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90506946 & 1 & FP-LYKJ 3U8HP PANEL \\ \hline
|
||||
2 & 3033098 & 0.04 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
|
||||
3 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
4 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
5 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
6 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI (100EA) \\ \hline
|
||||
7 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
|
||||
8 & 3207076 & 0.01 & SCR M2.5*16 PAN 100 21101-222 \\ \hline
|
||||
9 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT (100PCS) \\ \hline
|
||||
10 & 3211232 & 1 & SCR M2.5*14 PAN PHL SS \\ \hline
|
||||
11 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=3in]{sma_idc_drawings.pdf}
|
||||
\captionof{figure}{5528 SMA-IDC front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (5528 Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90506946 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
|
||||
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=3in]{sma_idc_assembly.pdf}
|
||||
\captionof{figure}{5528 SMA-IDC front panel assembly}
|
||||
\end{center}
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (5528 Assembled)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90506949 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
|
||||
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
|
||||
5 & 3040012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
|
||||
6 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
7 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI (100EA) \\ \hline
|
||||
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
|
||||
9 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 5518 BNC-IDC/5528 SMA-IDC in the ARTIQ Sinara crate configuration tool.
|
||||
The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
86
5568.tex
86
5568.tex
@ -1,10 +1,30 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/5568}{images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfig}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usepackage{pifont}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\title{5568 HD68-IDC}
|
||||
\author{M-Labs Limited}
|
||||
\date{April 2025}
|
||||
\revision{Revision 2}
|
||||
\date{January 2022}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -13,9 +33,9 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{32 channels}
|
||||
\item{Internal IDC connector}
|
||||
\item{External HD68 connectors}
|
||||
\item{32 channels.}
|
||||
\item{Internal IDC connector.}
|
||||
\item{External HD68 connectors.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
@ -32,13 +52,25 @@
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 5568 HD68-IDC card is an 8hp EEM module, part of the ARTIQ/Sinara family. It is an adapter card that converts IDC connections to or from HD68 connections. It can be connected via external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
|
||||
The 5568 HD68-IDC card is a 4hp EEM module part of the ARTIQ Sinara family.
|
||||
It is an adapter that converts IDC connection from/to HD68 connection.
|
||||
It connects to an external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
|
||||
|
||||
Each card supports 32 channels, with one HD68 connector and four IDC connectors. Each IDC connector supports 8 channels. All 32 channels can be accessed using an external HD68 cable.
|
||||
Each card support 32 channels, with 1 HD68 connector and 4 IDC connectors.
|
||||
Each IDC connector supports 8 channels, while all 32 channels are accessible using an external HD68 cable.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
|
||||
\newcommand{\inputcolorboxminted}[2]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#1, gobble=4]{python}{#2}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{1}{
|
||||
@ -48,10 +80,10 @@ Each card supports 32 channels, with one HD68 connector and four IDC connectors.
|
||||
\draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
|
||||
|
||||
% IDC Connectors to IDC cards
|
||||
\draw (3.0, 1.8) node[twoportshape, t={\twocm{IDC}{CH 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem2) {};
|
||||
\draw (1.8, 1.8) node[twoportshape, t={\twocm{IDC}{CH 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem3) {};
|
||||
\draw (3.0, -1.8) node[twoportshape, t={\twocm{IDC}{CH 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem1) {};
|
||||
\draw (1.8, -1.8) node[twoportshape, t={\twocm{IDC}{CH 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem0) {};
|
||||
\draw (3.0, 1.8) node[twoportshape, t={\MyLabel{IDC}{CH 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem2) {};
|
||||
\draw (1.8, 1.8) node[twoportshape, t={\MyLabel{IDC}{CH 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem3) {};
|
||||
\draw (3.0, -1.8) node[twoportshape, t={\MyLabel{IDC}{CH 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem1) {};
|
||||
\draw (1.8, -1.8) node[twoportshape, t={\MyLabel{IDC}{CH 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem0) {};
|
||||
|
||||
% Connect Op-amp to EEM OUT and HD68
|
||||
\draw [-latexslim] (3.0, 0) -- (hd68.east);
|
||||
@ -68,30 +100,36 @@ Each card supports 32 channels, with one HD68 connector and four IDC connectors.
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[height=3.1in, angle=90]{photo5568.jpg}
|
||||
\includegraphics[height=2.5in, angle=90]{fp5568.jpg}
|
||||
\caption{Card and front panel}
|
||||
\includegraphics[height=2.1in]{HD68_IDC_FP.pdf}
|
||||
\includegraphics[height=2.1in]{photo5568.jpg}
|
||||
\caption{HD68-IDC Card photo}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{5568 HD68-IDC}{https://github.com/sinara-hw/IDC_HD68_Adapter}
|
||||
|
||||
\section{Cable Connection Diagram}
|
||||
The 5568 HD68-IDC card can convert signals from HD68 format to IDC format. Within the Sinara family, the analog output of 5432 DAC Zotino \& 5632 DAC Fastino cards is exported using HD68 connectors. To break out the analog signal into a different crate, connect 5568 HD68-IDC with the DAC card using an external SCSI cable. Then plug in IDC cables to the appropriate IDC connectors to break out the signal to e.g. 5518 BNC-IDC, 5528 SMA-IDC, or 5538 MCX-IDC.
|
||||
|
||||
The 5568 HD68-IDC card can convert signal from HD68 format to IDC format.
|
||||
In the Sinara family, analog output of 5432 DAC Zotino \& 5632 DAC Fastino cards are exported using HD68 connectors.
|
||||
To break out the analog signal in a different crate, connect 5568 HD68-IDC with the DAC card using an external SCSI cable.
|
||||
Then, plug in IDC cables to the appropriate IDC connectors to break out the signal to 5518 BNC-IDC or 5528 SMA-IDC cards.
|
||||
The cable connections for 5568 HD68-IDC can be seen in the diagram below.
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[height=4in]{hd68_idc_connection.pdf}
|
||||
\includegraphics[height=5in]{hd68_idc_connection.pdf}
|
||||
\caption{HD68-IDC connection diagram}
|
||||
\end{figure}
|
||||
|
||||
\ordersection{5568 HD68-IDC}
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 5568 HD68-IDC in the ARTIQ Sinara crate configuration tool.
|
||||
The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\finalfootnote
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
166
5632.tex
166
5632.tex
@ -1,166 +0,0 @@
|
||||
\input{preamble.tex}
|
||||
\input{shared/dactino.tex}
|
||||
\graphicspath{{images/5632}, {images}}
|
||||
|
||||
\title{5632 DAC Fastino}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2025}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
\maketitle
|
||||
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{32-channel fast DAC}
|
||||
\item{16-bit resolution}
|
||||
\item{3 MSPS per channel}
|
||||
\item{Output voltage ±10V}
|
||||
\item{Gateware CIC interpolation}
|
||||
\item{HD68 connector}
|
||||
\item{Can be broken out to BNC/SMA/MCX}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Low-frequency arbitrary waveform generation}
|
||||
\item{Driving DC electrodes in ion traps}
|
||||
\end{itemize}
|
||||
|
||||
\generaldescription{5632 DAC Fastino}{slower 5432 DAC Zotino}
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
%\begin{figure}[h]
|
||||
% \centering
|
||||
% \scalebox{1.15}{
|
||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
||||
% \begin{scope}[]
|
||||
% % if applicable
|
||||
% \end{scope}
|
||||
% \end{circuitikz}
|
||||
% }
|
||||
|
||||
% \caption{Simplified Block Diagram}
|
||||
%\end{figure}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=2.25in]{photo5632.jpg}
|
||||
\caption{Fastino card}
|
||||
\includegraphics[height=3in, angle=90]{fp5632.pdf}
|
||||
\caption{Fastino front panel}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{5632 DAC Fastino}{https://github.com/sinara-hw/Fastino}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
% \hypersetup{hidelinks}
|
||||
% \urlstyle{same}
|
||||
These specifications are based on the datasheet of the DAC IC
|
||||
(AD5542\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5512A_5542A.pdf}}),
|
||||
and various information from the Sinara wiki\footnote{\label{fastino_wiki}\url{https://github.com/sinara-hw/Fastino/wiki}}.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
Sampling rate & & 3\dag & & MSPS & per channel \\
|
||||
\hline
|
||||
Output voltage & -10 & & 10 & V & \\
|
||||
\hline
|
||||
Resolution\repeatfootnote{dac} & & 16 & & bits & \\
|
||||
\hline
|
||||
Settling time\repeatfootnote{dac} & & 1 & & \textmu s & \\
|
||||
\hline
|
||||
Temperature coefficient\repeatfootnote{fastino_wiki} & & & 7 & ppm & \\
|
||||
\hline
|
||||
3dB bandwidth & & 500 & & kHz & \\
|
||||
\hline
|
||||
Power consumption & 7 & & 13 & W & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\dag Note that current QUARTIQ gateware supports 2.55 MSPS maximum.
|
||||
|
||||
The following table records cross-talk and transient behavior by Fastino, collected in various Sinara issues, see spur analysis\footnote{\label{fastino56}\url{https://github.com/sinara-hw/Fastino/issues/56}}, cross-talk\footnote{\url{https://github.com/sinara-hw/Fastino/issues/85}}, and noise summary\footnote{\url{https://github.com/sinara-hw/Fastino/issues/51}}. DAC output during output noise measurement was 6.875 V, updating continuously, channel 27 used for recording.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions / Comments} \\
|
||||
\hline
|
||||
DC cross-talk & & & -65 & dBmV & \\
|
||||
\hline
|
||||
Output noise & & & & & over 1kHz bandwidth \\
|
||||
\hspace{18mm} @ 500 kHz & & 60 & 80 & nV/rtHz & \\
|
||||
\hspace{18mm} @ 2 MHz & & & 12 & nV/rtHz & \\
|
||||
\hspace{18mm} @ 10 MHz & & & 4 & nV/rtHz & \\
|
||||
\hline
|
||||
Broadband noise & & & & & over 6.9kHz bandwidth \\
|
||||
\hspace{18mm} @ 100 kHz & & 56 & & nV/rtHz & \\
|
||||
\hspace{18mm} @ 1 MHz & & 14 & & nV/rtHz & \\
|
||||
\hline
|
||||
Spur-free range & 0.1 & & 5 & MHz & Correctly configured\repeatfootnote{fastino56} \\
|
||||
Digital update spurs & & 560 & & nVrm & @ 2.55MHz \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
% Is it worth recounting spur summary issue here?
|
||||
|
||||
\newpage
|
||||
|
||||
\section{LEDs}
|
||||
|
||||
5632 DAC Fastino provides eight user LEDs in the front panel. These are directly accessible with ARTIQ RTIO. Four additional LEDs indicate, respectively, power good (\texttt{PG}), FPGA done (\texttt{FD}), overtemperature (\texttt{OT}), and gateware or initialization error (\texttt{ERR}).
|
||||
|
||||
\sysdescsection
|
||||
|
||||
5632 DAC Fastino should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "fastino",
|
||||
"ports": [0],
|
||||
"log2_width": 0 // select 0 to 5, default is 0
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Replace 0 with the EEM port used on the core device. Any port may be used on the core device side. Fastino provides two EEM ports, of which ARTIQ always requires the first, \texttt{EEM0}. The second, \texttt{EEM1}, should not be used.
|
||||
|
||||
The \texttt{log2\_width} field accepts a number from 0 to 5 inclusive and represents (in powers of two) the number of DAC channels packed into a single RTIO write (1 to 32). This allows and defines the use of \texttt{set\_group()} functions rather than \texttt{set\_dac()} as in examples given below.
|
||||
|
||||
\codesectiondactino{5632 DAC Fastino}{Fastino}{fastino.py}
|
||||
|
||||
\subsection{CIC interpolators}
|
||||
|
||||
Fastino gateware features dynamically configurable CIC (cubic B-spline) interpolators, defined individually by channel, with interpolation rates from 1 (2.55 MSPS) to 65536 (39 SPS). For more details, see manual documentation on ARTIQ driver functions \texttt{stage\_cic} and \texttt{apply\_cic}.
|
||||
|
||||
\ordersection{5632 DAC Fastino}
|
||||
|
||||
\finalfootnote
|
||||
|
||||
\end{document}
|
||||
111
5633.tex
111
5633.tex
@ -1,111 +0,0 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/5633}, {images}}
|
||||
|
||||
\title{5633 HV Amplifier}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2025}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
\maketitle
|
||||
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{32-channel amplifier}
|
||||
\item{5x gain, ±50V output voltage}
|
||||
\item{12MHz/gain bandwidth}
|
||||
\item{21V/µs slew rate}
|
||||
\item{Overtemperature protection}
|
||||
\item{Connectors compatible with 5432 Zotino and 5632 Fastino}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Amplified low-frequency arbitrary waveform generation}
|
||||
\item{High-voltage driving DC electrodes in ion traps}
|
||||
\item{Can be used as mezzanine for \begin{itemize}
|
||||
\item{5432 Zotino}
|
||||
\item{5632 Fastino}
|
||||
\end{itemize}}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
|
||||
The 5633 HV Amplifier card is a 4hp EEM module and part of the Sinara open hardware family. It acts as a mezzanine to compatible Sinara cards, amplifying the output of cards such as 5432 DAC Zotino and 5632 DAC Fastino by ±50V (5x gain).
|
||||
|
||||
5633 HV Amplifier provides 32 channels of amplification. It uses the same connectors as 5432 Zotino and 5632 Fastino, allowing for direct mezzanine attachment, and for ease of use provides the same output interface, four internal IDC connectors and a front-panel HD68 connector.
|
||||
|
||||
5633 HV Amplifier features overtemperature protection both for individual channels and entire board. If safe thresholds are crossed, channels will be disabled individually or board at a whole disabled as necessary.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
%\begin{figure}[h]
|
||||
% \centering
|
||||
% \scalebox{1.15}{
|
||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
||||
% \begin{scope}[]
|
||||
% % if applicable
|
||||
% \end{scope}
|
||||
% \end{circuitikz}
|
||||
% }
|
||||
|
||||
% \caption{Simplified Block Diagram}
|
||||
%\end{figure}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=2.25in]{photo5633.jpg}
|
||||
\caption{HV Amplifier card}
|
||||
\includegraphics[height=3in, angle=90]{fp5633.pdf}
|
||||
\caption{HV Amplifier front panel}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{5633 HV Amplifier}{https://github.com/sinara-hw/HVAMP_32}
|
||||
|
||||
\section{Electrical specifications}
|
||||
|
||||
%LTC6090 datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/6090fe.pdf
|
||||
|
||||
These specifications are based on the datasheet of the amplifier (LTC6090\footnote{\label{amp}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/6090fe.pdf}}) and various information from the Sinara wiki\footnote{\label{wiki}\url{https://github.com/sinara-hw/HVAMP_32/wiki}}.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Gain & & 5 & & V/V & \\
|
||||
\hline
|
||||
Output voltage & - 50 & & 50 & V & \\
|
||||
\hline
|
||||
Slew rate & & 21 & & V/µs & \\
|
||||
\hline
|
||||
Bandwidth & & 12 & & MHz/gain & \\
|
||||
& & 2.4 & & MHz & at 5x gain \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
5633 HV Amplifier requires a 12V power supply, accepted through either Molex or barrel connectors at the back of the board.
|
||||
|
||||
\section{LEDs}
|
||||
|
||||
5633 HV Amplifier provides four indicator LEDs in the front panel, respectively \texttt{3V} (3.3V power status) \texttt{HV} (high voltage power status) \texttt{COT} (channel overtemperature, channel disabled), and \texttt{BOT} (board overtemperature, board shut down).
|
||||
|
||||
\ordersection{5633 HV Amplifier}
|
||||
|
||||
\finalfootnote
|
||||
|
||||
\end{document}
|
||||
205
5716.tex
205
5716.tex
@ -1,205 +0,0 @@
|
||||
\input{preamble.tex}
|
||||
\input{shared/coredevice.tex}
|
||||
\graphicspath{{images}{images/5716}}
|
||||
|
||||
\title{5716 DAC Shuttler}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2025}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
\maketitle
|
||||
|
||||
\section{Features}
|
||||
\begin{itemize}
|
||||
\item{16-channel DAC}
|
||||
\item{14-bit resolution, $<1$ LSB DNL}
|
||||
\item{125 MSPS sample rate}
|
||||
\item{Output voltage ±10 V}
|
||||
\item{EEM FMC carrier with Artix-7 FPGA core}
|
||||
\item{Remote analog front end card}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Driving DC electrodes in ion traps}
|
||||
\item{Ion chain splitting, ion shuttling}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
|
||||
The 5716 DAC Shuttler is an 8hp EEM module, shipped with associated remote analog front-end (AFE), part of the ARTIQ/Sinara family. It consists of the Shuttler FMC paired with an 8hp Sinara EEM FMC Carrier, which is capable of running as an ARTIQ satellite core through DRTIO-over-EEM. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
ARTIQ gateware implements NIST PDQ-style waveform synthesizer which supports the use of sigma-delta modulation to increase effective resolution to 16 bits.
|
||||
|
||||
Digital communication between FMC and remote AFE is provided through mini-SAS HD cables. The AFE supports ±10 V output and 50 MHz 3dB bandwidth, using onboard 24-bit ADC for calibration.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
%\begin{figure}[h]
|
||||
% \centering
|
||||
% \scalebox{1.15}{
|
||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
||||
% \begin{scope}[]
|
||||
% % if applicable
|
||||
% \end{scope}
|
||||
% \end{circuitikz}
|
||||
% }
|
||||
%
|
||||
% \caption{Simplified Block Diagram}
|
||||
%\end{figure}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=1.7in, angle=-90]{photo5716.jpg}
|
||||
\caption{Shuttler FMC}
|
||||
\includegraphics[height=1.5in]{shuttler_afe.jpg}
|
||||
\caption{Shuttler AFE}
|
||||
\includegraphics[height=1.5in]{fmc_side.jpg}
|
||||
\caption{Sinara EEM FMC carrier}
|
||||
\includegraphics[height=2.5in, angle=90]{fp5716.jpg}
|
||||
\caption{Shuttler front panel}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{5716 DAC Shuttler}{https://github.com/sinara-hw/FMC_Shuttler} Files for the AFE card are stored at \url{https://github.com/sinara-hw/AFE_DAC_External}. Files for the Sinara EEM FMC Carrier can be found at \url{https://github.com/sinara-hw/EEM_FMC_Carrier}.
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
These specifications are based on the datasheet of the DAC IC (AD9117\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9114_9115_9116_9117.pdf}}), board measurements\footnote{\label{shuttler36}\url{https://github.com/sinara-hw/FMC_Shuttler/issues/36}}, and various information from the Sinara wiki\footnote{\label{wiki}\url{https://github.com/sinara-hw/FMC_Shuttler/wiki}}.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Output Specifications}
|
||||
\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
Sampling rate\repeatfootnote{wiki} & & 125 & & MSPS & \\
|
||||
\hline
|
||||
Output voltage\repeatfootnote{wiki} & -10 & & +10 & V & \\
|
||||
\hline
|
||||
Resolution\repeatfootnote{wiki} & & 14 & & bits & Raw \\
|
||||
& & 16 & & bits & With sigma-delta modulation \\
|
||||
\hline
|
||||
Settling time\repeatfootnote{dac} & & 11.5 & & ns & \\
|
||||
\hline
|
||||
Analog bandwidth\repeatfootnote{shuttler36} & & 12 & & MHz & \\
|
||||
\hline
|
||||
3dB bandwidth\repeatfootnote{wiki} & & 50 & & MHz & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
Power to Shuttler is supplied over EEM. Power to the AFE is to be supplied over a 4-pin circular M8 connector placed between the mini-SAS HD ports. The AFE output port is 25-pin DSUB.
|
||||
|
||||
\artiqsection
|
||||
|
||||
The Sinara EEM FMC Carrier features an XC7A200T-3FBG484E Xilinx Artix-7 FPGA, usually configured as an ARTIQ satellite core. Firmware and gateware for the Sinara EEM FMC Carrier is closely related to that used for 1124 Kasli 2.0 satellites. The specific binary generation target can be found in the module \texttt{artiq.gateware.targets.efc} of the ARTIQ repository.
|
||||
|
||||
\newpage
|
||||
|
||||
\sysdescsection
|
||||
|
||||
5716 Shuttler should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "shuttler",
|
||||
"ports": 0
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Replace 0 with the EEM port number used on the core device. Any port can be used. On the other side, the Sinara EEM FMC Carrier possesses two EEM ports, but only one is necessary for Shuttler. This should always be \texttt{EEM0}.
|
||||
|
||||
Since Shuttler acts as a DRTIO satellite, the DRTIO type of the core device should be specified as master, not standalone, even if no other satellite cores are used. DRTIO-over-EEM for Shuttler is automatically assigned a destination number, \#4 on Kasli 2.0, \#5 on Kasli-SoC\footnote{i.e., in both cases, first available destination number after those associated with the core device's downstream SFP slots.}. Destination numbers count up correspondingly for additional Shuttlers. See the ARTIQ manual\footnote{\url{https://m-labs.hk/artiq/manual/using_drtio_subkernels.html}} for instructions on configuring a routing table, for cases where you need one (for example, a Shuttler on a DRTIO satellite).
|
||||
|
||||
\section{Clocking}
|
||||
|
||||
Clock input should be provided to Shuttler through the EEM FMC Carrier. The EEM FMC Carrier \textit{must} share a clock source with the associated core device. Clocks must be aligned to utilize DRTIO-over-EEM. Clock input can be provided to EEM FMC Carrier via SMA connector on front panel or MMCX connector at back of board (top right, above \texttt{EEM0}). The Shuttler FMC features a front panel MCX connector labeled for clock input; this is currently unused by ARTIQ firmware/gateware.
|
||||
|
||||
\begin{multicols}{2}
|
||||
FMC Carrier clock source must be configured by setting the DIP switches on back of the board, under the following schema:
|
||||
|
||||
\begin{center}
|
||||
\begin{tabular}{ | c | c | c | } \thickhline
|
||||
\textbf{Clock Source} & \textbf{CLK\_SEL0} & \textbf{CLK\_SEL1} \\
|
||||
\thickhline
|
||||
Front panel SMA & 0 & 0 \\ \hline
|
||||
Internal oscillator & 1 & 0 \\ \hline
|
||||
Back MMCX & 0 & 1 \\ \hline
|
||||
PE CLK & 1 & 1 \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\vspace*{\fill}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.7in]{shuttler_dip_switches.jpg}
|
||||
\captionof{figure}{Position of DIP switches}
|
||||
\end{center}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
Users should note that PE CLK and internal oscillator are not valid source choices for Shuttler.
|
||||
|
||||
At first power-up, FMC Carrier and connected core device will determine the clock skew over EEM transceiver and store the result in configuration memory. It can be accessed in ARTIQ under the key \texttt{eem\_drtio\_delay0} (where \texttt{0} is a counter that will be incremented for further DRTIO-over-EEM connections.)
|
||||
|
||||
If EEM cable or clocking cables are changed, or if either device is reflashed for any reason, this value must be manually erased in order to force a reevaluation of the clock skew. Either \texttt{artiq\_coremgmt config remove} (for original ARTIQ) or direct access to the SD card (on Zynq) should be used.
|
||||
|
||||
\newpage
|
||||
|
||||
\section{LEDs}
|
||||
|
||||
The EEM FMC Carrier provides two user LEDs, \texttt{L0} and \texttt{L1}, located on the front panel, which are accessible in ARTIQ gateware and can be used for testing.
|
||||
|
||||
The Shuttler AFE provides twenty LEDs in two banks. The four-LED bank to the right of the mini-SAS connectors indicate power status. The sixteen-LED bank to the left of the mini-SAS connectors indicate output relay status. DAC output is only valid when corresponding relay LEDs are on.
|
||||
|
||||
\codesection{5716 DAC Shuttler}
|
||||
|
||||
Shuttler is capable of generating a waveform in the following equation:
|
||||
|
||||
\[ w(t) = a(t) + b(t) * cos(c(t)) \]
|
||||
|
||||
where $a(t)$ and $b(t)$ are cubic splines and $c(t)$ is a quadratic spline\footnote{See also the PDQ documentation hosted at the following link: \url{https://pdq.readthedocs.io/}}.
|
||||
|
||||
The following code initializes relay and ADC and resets all channels.
|
||||
|
||||
\inputcolorboxminted{firstline=21,lastline=42}{examples/shuttler.py}
|
||||
|
||||
\newpage
|
||||
|
||||
\inputcolorboxminted{firstline=43,lastline=65}{examples/shuttler.py}
|
||||
|
||||
\subsection{Generating a basic waveform}
|
||||
|
||||
The following code generates a basic sine wave of approx 10 MHz on the \texttt{DAC0 I} channel. The value of \texttt{0x147AE148} used for $c_1$ sets the frequency as $c_1 / 2^{32} * 125$ MHz.
|
||||
|
||||
\inputcolorboxminted{firstline=67,lastline=85}{examples/shuttler.py}
|
||||
|
||||
\begin{figure}[!hbt]
|
||||
\centering
|
||||
\includegraphics[height=3in]{sine_wave.jpg}
|
||||
\caption{Produced waveform, measured at \texttt{AFE0} output resistor R36A, R39A.}
|
||||
\end{figure}
|
||||
|
||||
For more example waveforms see also the folder \texttt{kasli\_shuttler} in the ARTIQ \texttt{examples} directory.
|
||||
|
||||
\ordersection{5716 DAC Shuttler}
|
||||
|
||||
\finalfootnote
|
||||
|
||||
\end{document}
|
||||
120
6302.tex
120
6302.tex
@ -1,120 +0,0 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/6302}, {images}}
|
||||
|
||||
\title{6302 Grabber}
|
||||
\author{M-Labs Limited}
|
||||
\date{April 2025}
|
||||
\revision{Revision 1}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
\maketitle
|
||||
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{CameraLink input interface for ARTIQ}
|
||||
\item{Support for several EMCCD cameras}
|
||||
\item{Low-latency image processing on-FPGA}
|
||||
\item{Stack retrieves data sum over rectangular ROIs}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Ion fluorescence detection}
|
||||
\item{Cold atom fluorescence detection}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
|
||||
The 6302 Grabber card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds frame grabber capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. 6302 Grabber targets (EM)CCD scientific cameras using the CameraLink protocol standard. Using ARTIQ gateware, incoming camera signal is immediately transferred to the carrier card, where it can be processed with low latency on-FPGA .
|
||||
|
||||
The Sinara/ARTIQ stack supports defining rectangular ROIs (regions of interest); pixel value sums over these ROIs are reported to and can be used directly by ARTIQ kernels.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
%\begin{figure}[h]
|
||||
% \centering
|
||||
% \scalebox{1.15}{
|
||||
% \begin{circuitikz}[european, every label/.append style={align=center}]
|
||||
% \begin{scope}[]
|
||||
% % if applicable
|
||||
% \end{scope}
|
||||
% \end{circuitikz}
|
||||
% }
|
||||
|
||||
% \caption{Simplified Block Diagram}
|
||||
%\end{figure}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=3in, angle=-90]{photo6302.jpg}
|
||||
\caption{Grabber card}
|
||||
\includegraphics[height=3in, angle=90]{fp6302.jpg}
|
||||
\caption{Grabber front panel}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{6302 Grabber}{https://github.com/sinara-hw/Grabber}
|
||||
|
||||
\section{Grabber I/O}
|
||||
|
||||
6302 Grabber features two front-panel 26-pin MDR connectors, commonly used by CameraLink connections. Properly shielded and twisted cables intended for CameraLink should be used. For Base CameraLink, only one MDR connection (and one EEM) is necessary; higher-speed Medium CameraLink requires two.
|
||||
|
||||
Power over CameraLink (PoCL) is not supported.
|
||||
|
||||
\subsection{Grabber Single-/Double-/Triple-EEM Modes}
|
||||
|
||||
6302 Grabber can operate with either a single, double, or triple EEM connection to a core device. The following table specifies the connections to use and the highest CameraLink configuration supported.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\begin{tabularx}{0.4\textwidth}{|l|c|c| X}
|
||||
\hline
|
||||
\textbf{EEMs} & \textbf{Ports} & \textbf{CameraLink} \\
|
||||
\thickhline
|
||||
1 & \texttt{0} & Base CameraLink\\
|
||||
2 & \texttt{0, 1} & Medium CameraLink \\
|
||||
3 & \texttt{0, 1, 2} & Full CameraLink \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\captionof{table}{Grabber EEM modes}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
Note that current ARTIQ gateware only supports Base Cameralink.
|
||||
|
||||
\sysdescsection
|
||||
|
||||
6302 Grabber should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
{
|
||||
"type": "grabber",
|
||||
"ports": [0, 1]
|
||||
}
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
Replace 0 and 1 with the EEM port numbers used on the core device. Any port numbers can be used. Specifying a second port is optional. If using Grabber in single-EEM mode, specify only \texttt{[0]}.
|
||||
|
||||
\newpage
|
||||
|
||||
\codesectionshort{6302 Grabber card}
|
||||
|
||||
The following code specifies two ROIs (Regions of Interest), enables both, retrieves their accumulated data for a single frame, and disables the ROI engines.
|
||||
|
||||
\inputcolorboxminted{firstline=9,lastline=31}{examples/grabber.py}
|
||||
|
||||
\ordersection{6302 Grabber}
|
||||
|
||||
\finalfootnote
|
||||
|
||||
\end{document}
|
||||
143
7210.tex
143
7210.tex
@ -1,10 +1,29 @@
|
||||
\input{preamble.tex}
|
||||
\graphicspath{{images/7210}{images}}
|
||||
\documentclass[10pt]{datasheet}
|
||||
\usepackage{palatino}
|
||||
\usepackage{textgreek}
|
||||
\usepackage{minted}
|
||||
\usepackage{tcolorbox}
|
||||
\usepackage{etoolbox}
|
||||
|
||||
\usepackage[justification=centering]{caption}
|
||||
|
||||
\usepackage[utf8]{inputenc}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage[english]{isodate}
|
||||
|
||||
\usepackage{graphicx}
|
||||
\usepackage{subfig}
|
||||
|
||||
\usepackage{tikz}
|
||||
\usepackage{pgfplots}
|
||||
\usepackage{circuitikz}
|
||||
\usetikzlibrary{calc}
|
||||
\usetikzlibrary{fit,backgrounds}
|
||||
|
||||
\title{7210 Clocker}
|
||||
\author{M-Labs Limited}
|
||||
\date{April 2025}
|
||||
\revision{Revision 4}
|
||||
\date{January 2022}
|
||||
\revision{Revision 2}
|
||||
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
||||
|
||||
\begin{document}
|
||||
@ -13,18 +32,18 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Low-jitter clock signal distribution}
|
||||
\item{SMA \& MMCX input}
|
||||
\item{4 SMA \& 6 MMCX output}
|
||||
\item{\textless100 fs RMS jitter}
|
||||
\item{Distribute a low jitter clock signal.}
|
||||
\item{SMA \& MMCX clock input.}
|
||||
\item{4 SMA \& 6 MMCX output.}
|
||||
\item{\textless100 fs RMS clock jitter.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Distribute clock signals}
|
||||
\item{Amplify clock signals}
|
||||
\item{Drive clock input for:\begin{itemize}
|
||||
\item{Distribute clock signal.}
|
||||
\item{Clock distribution amplifier.}
|
||||
\item{Drive clocks input for:\begin{itemize}
|
||||
\item{4410/4412 DDS Urukul}
|
||||
\item{4456 Synthesizer Mirny}
|
||||
\item{4624 Phaser}
|
||||
@ -32,17 +51,30 @@
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 7210 Clocker card is a 4hp EEM module, capable of distributing clock signals with \textless100 fs RMS jitter.
|
||||
The 7210 Clocker card is a 4hp EEM module.
|
||||
It distrubites clock signal with \textless100 fs RMS jitter.
|
||||
|
||||
Clock input can be supplied to Clocker through the external SMA connector or the internal MMCX connector. The input source is selected using an SPDT switch.
|
||||
Clock input can be supplied to Clocker through the external SMA connector or the internal MMCX connector.
|
||||
The input source can be selected using an SPDT switch.
|
||||
Each card distributes the input to 10 outputs.
|
||||
4 outputs are interfaced with SMA connectors, the other 6 are with MMCX connectors.
|
||||
|
||||
Each Clocker card distributes an input to 10 outputs. 4 outputs are interfaced with SMA connectors, the other 6 with MMCX connectors.
|
||||
|
||||
Clocker can be powered externally or internally. To provide external power, connect an external 12V power source either through front panel power jack or rear connector. Alternatively, connect it to a carrier card (e.g. 1124 Kasli, 1125 Kasli-SoC) using the EEM port.
|
||||
Clocker can be powered externally or internally.
|
||||
To provide external power, connect an external 12V power source through the front panel power jack.
|
||||
Otherwise, connect it to a carrier card (1124 Kasli or 1125 Kasli-SoC) using the EEM port.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
|
||||
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
|
||||
\newcommand{\inputcolorboxminted}[2]{%
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\inputminted[#1, gobble=4]{python}{#2}
|
||||
\end{tcolorbox}
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\scalebox{0.95}{
|
||||
@ -61,7 +93,7 @@ Clocker can be powered externally or internally. To provide external power, conn
|
||||
\draw[color=white, text=black] (-0.1, -1.4) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx7) {};
|
||||
\draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx8) {};
|
||||
\draw[color=white, text=black] (-0.1, -2.1) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx9) {};
|
||||
|
||||
|
||||
% Labels for all IO symbols
|
||||
\node [label=center:\tiny{OUT 0}] at (sma0) {};
|
||||
\node [label=center:\tiny{OUT 1}] at (sma1) {};
|
||||
@ -102,14 +134,14 @@ Clocker can be powered externally or internally. To provide external power, conn
|
||||
\draw (0,0) circle(1.5);
|
||||
\clip (-0.8,0) rectangle (0.8,0.8);
|
||||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
\end{scope}
|
||||
\begin{scope}[scale=0.07 , rotate=-90, xshift=5cm, yshift=2cm]
|
||||
\draw (0,0.65) -- (0,3);
|
||||
\clip (-1.5,0) rectangle (1.5,1.5);
|
||||
\draw (0,0) circle(1.5);
|
||||
\clip (-0.8,0) rectangle (0.8,0.8);
|
||||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
\end{scope}
|
||||
\begin{scope}[scale=0.07 , rotate=-90, xshift=10cm, yshift=2cm]
|
||||
\draw (0,0.65) -- (0,3);
|
||||
\clip (-1.5,0) rectangle (1.5,1.5);
|
||||
@ -179,11 +211,11 @@ Clocker can be powered externally or internally. To provide external power, conn
|
||||
\node [label=right:\tiny{SMA CLK IN}] at (sma_clkin) {};
|
||||
|
||||
% Draw the SPDT switch
|
||||
\draw (2.6, -2) node[twoportshape,t=\fourcm{Input Clock \phantom{spac} }{Selection Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.6] (clk_sel) {};
|
||||
\draw (2.6, -2) node[twoportshape,t=\MymyLabel{Input Clock \phantom{spac} }{Selection Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.6] (clk_sel) {};
|
||||
\begin{scope}[xshift=3cm, yshift=-1.78cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% Connect CLKINs to the clock buffer
|
||||
@ -214,24 +246,24 @@ Clocker can be powered externally or internally. To provide external power, conn
|
||||
\caption{Simplified Block Diagram}
|
||||
\end{figure}
|
||||
|
||||
\vspace{5mm}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=3.5in]{photo7210.jpg}
|
||||
\includegraphics[height=3.5in]{fp7210.jpg}
|
||||
\caption{Clocker card and front panel}
|
||||
\includegraphics[height=3in]{Clocker_FP.jpg}
|
||||
\includegraphics[height=3in]{photo7210.jpg}
|
||||
\caption{Clocker Card photo}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{7210 Clocker}{https://github.com/sinara-hw/Clocker}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
Specifications are derived based on the datasheets of the clock buffer (ADCLK950BCPZ\footnote{\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADCLK950.pdf}}) and the RF transformer (TCM2-43X+\footnote{\url{https://www.minicircuits.com/pdfs/TCM2-43X+.pdf}}) used. Clock output specifications are tested by supplying a 100 MHz DDS signal to the SMA input connector\footnote{\label{clocker6}\url{https://github.com/sinara-hw/Clocker/issues/6\#issuecomment-414048168}}. The output is connected to an oscilloscope with 50\textOmega~termination.
|
||||
Specifications are derived based on the datasheets of
|
||||
the clock buffer (ADCLK950BCPZ\footnote{\label{clock_buffer}https://www.analog.com/media/en/technical-documentation/data-sheets/ADCLK950.pdf}) \&
|
||||
the RF transformer (TCM2-43X+\footnote{\label{rf_transformer}https://www.minicircuits.com/pdfs/TCM2-43X+.pdf}).
|
||||
Clock output specifications is tested by supplying a 100 MHz DDS signal to the SMA input connector.\footnote{\label{clocker6}https://github.com/sinara-hw/Clocker/issues/6\#issuecomment-414048168}
|
||||
The output is connected to an oscilloscope with 50\textOmega~termination.
|
||||
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
@ -242,13 +274,13 @@ Specifications are derived based on the datasheets of the clock buffer (ADCLK950
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Clock input & & & & & \\
|
||||
Clock input\repeatfootnote{clock_buffer}\textsuperscript{,}\repeatfootnote{rf_transformer} & & & & & \\
|
||||
\hspace{3mm} Peak-to-peak voltage & 0.40 & & 2.40 & V\textsubscript{p-p} & \\
|
||||
\hspace{3mm} Frequency & 10 & & 4000 & MHz & \\
|
||||
\hline
|
||||
Clock output & & & & & \\
|
||||
\hspace{3mm} Peak-to-peak voltage & & 0.8 & & V\textsubscript{p-p} & \multirow{3}{*}{50\textOmega~load, 100 MHz} \\
|
||||
\hspace{3mm} Power & & 5 & & dBm & \\
|
||||
Clock output
|
||||
& & 0.8 & & V\textsubscript{p-p} & \multirow{3}{*}{50\textOmega~load, 100 MHz} \\
|
||||
& & 5 & & dBm & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
@ -256,44 +288,41 @@ Specifications are derived based on the datasheets of the clock buffer (ADCLK950
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=6in]{clocker_waveform.png}
|
||||
\includegraphics[width=5in]{clocker_waveform.png}
|
||||
\caption{Waveform of Clocker at 100 MHz\repeatfootnote{clocker6}}
|
||||
\end{figure}
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Phase-Noise Performance}
|
||||
|
||||
Performance measured against 100 MHz Wenzel Quartz, phase-locked to 10MHz Wenzel Blue Top oscillator\footnote{\label{clockerpn}\url{https://github.com/sinara-hw/Clocker/issues/4\#issuecomment-1310591042}}. Blue trace represents measurement against itself for reference.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=6.5in]{clocker_phase_noise.png}
|
||||
\caption{Absolute phase noise of Clocker measured @ 100 MHz (pink trace)\repeatfootnote{clockerpn}}
|
||||
\end{figure}
|
||||
|
||||
\section{Selecting Clock Source}
|
||||
Clock input can be supplied to 7210 Clocker using either the internal MMCX connector or the external SMA connector on the front panel. The selection of clock input is configurable by an SPDT switch, located between the MMCX input connector (\texttt{INT CLK IN}) and the MMCX output connectors. See Figure 5.
|
||||
Clock input can be supplied to the 7210 Clocker using either the internal MMCX connector or the external SMA connector on the front panel.
|
||||
The selection of clock input is configurable by a SPDT switch.
|
||||
It is located between the MMCX input connector (\texttt{INT CLK IN}) and the MMCX output connectors.
|
||||
\begin{multicols}{2}
|
||||
|
||||
Either \texttt{INT} or \texttt{EXT} can be selected.
|
||||
Either INT or EXT can be selected.
|
||||
\begin{itemize}
|
||||
\item Internal MMCX (\texttt{INT}) \\
|
||||
Clock signal from the MMCX connector \texttt{INT CLK IN} is distributed to all outputs.
|
||||
\item External SMA (\texttt{EXT}) \\
|
||||
Clock signal from the SMA connector \texttt{CLK IN} on the front panel is distributed to all outputs.
|
||||
\itemsep0em
|
||||
\item Internal MMCX (INT) \\
|
||||
Clock signal from the MMCX connector \texttt{INT CLK IN} is distributed to all MMCX outputs.
|
||||
\item External SMA (EXT) \\
|
||||
Clock signal from the SMA connector \texttt{CLK IN} on the front panel is distributed to all MMCX outputs.
|
||||
\end{itemize}
|
||||
|
||||
\vspace*{\fill}\columnbreak
|
||||
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.5in]{clocker_spdt_switch.jpg}
|
||||
\includegraphics[height=1.7in]{clocker_spdt_switch.jpg}
|
||||
\captionof{figure}{Position of the SPDT switch}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\ordersection{7210 Clocker}
|
||||
\finalfootnote{}
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 7210 Clocker in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
|
||||
\end{document}
|
||||
|
||||
|
Before Width: | Height: | Size: 60 KiB After Width: | Height: | Size: 60 KiB |
|
Before Width: | Height: | Size: 61 KiB After Width: | Height: | Size: 61 KiB |
|
Before Width: | Height: | Size: 60 KiB After Width: | Height: | Size: 60 KiB |
|
Before Width: | Height: | Size: 31 KiB After Width: | Height: | Size: 31 KiB |
BIN
HD68_IDC_FP.pdf
Normal file
BIN
HD68_IDC_FP.pdf
Normal file
Binary file not shown.
BIN
Kasli_FP.pdf
Normal file
BIN
Kasli_FP.pdf
Normal file
Binary file not shown.
13
Makefile
13
Makefile
@ -1,13 +0,0 @@
|
||||
inputs = 1008 1106 1124 1125 2118-2128 2238 2245 4410-4412 4456-4457 4624 5108 5432 5632 5633 5518-5528 5538 5568 6302 7210
|
||||
dir = build
|
||||
|
||||
all: $(inputs)
|
||||
|
||||
$(inputs) : % : %.tex
|
||||
latexmk -pdf -pdflatex="pdflatex -shell-escape" $@.tex
|
||||
if ! test -d "$(dir)"; then mkdir build; fi
|
||||
mv $@.pdf build/
|
||||
rm $@.log
|
||||
|
||||
clean:
|
||||
rm -rf _minted* *.aux *.out *.fls *.fdb_latexmk
|
||||
20
README.md
20
README.md
@ -1,20 +0,0 @@
|
||||
# sinara-hw/datasheets
|
||||
|
||||
Repository for Sinara hardware datasheets.
|
||||
|
||||
## Build all
|
||||
|
||||
```shell
|
||||
nix build .#all-pdfs
|
||||
```
|
||||
|
||||
Output files will be in `result`.
|
||||
|
||||
### Build individual sheets
|
||||
|
||||
```shell
|
||||
nix develop
|
||||
make 1124
|
||||
```
|
||||
|
||||
Output files will be in `build`. Run make twice in a row to get correct output for all LaTeX features, i.e. in particular correct "page x of y" footnotes, which require two passes of the compiler. (`#all-pdfs` already does this automatically). Auxiliary files and clutter can be removed with `make clean`.
|
||||
|
Before Width: | Height: | Size: 60 KiB After Width: | Height: | Size: 60 KiB |
|
Before Width: | Height: | Size: 30 KiB After Width: | Height: | Size: 30 KiB |
|
Before Width: | Height: | Size: 32 KiB After Width: | Height: | Size: 32 KiB |
|
Before Width: | Height: | Size: 30 KiB After Width: | Height: | Size: 30 KiB |
|
Before Width: | Height: | Size: 42 KiB After Width: | Height: | Size: 42 KiB |
BIN
bnc_idc_assembly.pdf
Normal file
BIN
bnc_idc_assembly.pdf
Normal file
Binary file not shown.
BIN
bnc_idc_drawings.pdf
Normal file
BIN
bnc_idc_drawings.pdf
Normal file
Binary file not shown.
BIN
bnc_ttl_assembly.pdf
Normal file
BIN
bnc_ttl_assembly.pdf
Normal file
Binary file not shown.
BIN
bnc_ttl_drawings.pdf
Normal file
BIN
bnc_ttl_drawings.pdf
Normal file
Binary file not shown.
|
Before Width: | Height: | Size: 33 KiB After Width: | Height: | Size: 33 KiB |
BIN
bnc_ttl_switches.jpg
Normal file
BIN
bnc_ttl_switches.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 80 KiB |
|
Before Width: | Height: | Size: 26 KiB After Width: | Height: | Size: 26 KiB |
BIN
clocker_spdt_switch.jpg
Normal file
BIN
clocker_spdt_switch.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 81 KiB |
|
Before Width: | Height: | Size: 64 KiB After Width: | Height: | Size: 64 KiB |
@ -5,7 +5,7 @@
|
||||
%% https://github.com/PetteriAimonen/latex-datasheet-template/
|
||||
%%
|
||||
%% --------------------------------------------------------------------------
|
||||
%%
|
||||
%%
|
||||
%% This work may be distributed and/or modified under the
|
||||
%% conditions of the LaTeX Project Public License, either version 1.3
|
||||
%% of this license or (at your option) any later version.
|
||||
@ -13,11 +13,11 @@
|
||||
%% http://www.latex-project.org/lppl.txt
|
||||
%% and version 1.3 or later is part of all distributions of LaTeX
|
||||
%% version 2003/12/01 or later.
|
||||
%%
|
||||
%%
|
||||
%% This work has the LPPL maintenance status "maintained".
|
||||
%%
|
||||
%%
|
||||
%% This Current Maintainer of this work is Petteri Aimonen.
|
||||
%%
|
||||
%%
|
||||
%% This work consists of the file datasheet.cls and the example
|
||||
%% document example.tex.
|
||||
|
||||
@ -40,12 +40,17 @@
|
||||
\RequirePackage{threeparttable}
|
||||
|
||||
% Align figure and table captions to left.
|
||||
\RequirePackage[font=bf,
|
||||
skip=5pt,
|
||||
justification=raggedright,
|
||||
format=hang,
|
||||
singlelinecheck=off,
|
||||
hypcap=false]{caption}
|
||||
\RequirePackage[font=bf, skip=5pt, justification=raggedright, format=hang, singlelinecheck=off]{caption}
|
||||
|
||||
% Format hyperlinks as blue and set PDF title based on \title{} in the document.
|
||||
\RequirePackage[pdfusetitle]{hyperref}
|
||||
\hypersetup{
|
||||
pdftex,
|
||||
breaklinks=true,
|
||||
colorlinks=true,
|
||||
linkcolor=.,
|
||||
urlcolor=blue
|
||||
}
|
||||
|
||||
% Configure page margins
|
||||
\RequirePackage{geometry}
|
||||
@ -119,17 +124,6 @@
|
||||
% No numbering for section titles
|
||||
\setcounter{secnumdepth}{0}
|
||||
|
||||
% Section and subsection spacing
|
||||
\usepackage{titlesec}
|
||||
\titlespacing*{\section}{0pt}{.2ex}{.2ex}
|
||||
\titlespacing*{\subsection}{0pt}{.2ex}{.2ex}
|
||||
|
||||
% Format hyperlinks as blue and set PDF title based on \title{} in the document.
|
||||
% Hyperref must be loaded last (in particular after titlesec)
|
||||
\RequirePackage[pdfusetitle]{hyperref}
|
||||
\hypersetup{
|
||||
breaklinks=true,
|
||||
colorlinks=true,
|
||||
linkcolor=.,
|
||||
urlcolor=blue
|
||||
}
|
||||
BIN
dds_assembly.pdf
Normal file
BIN
dds_assembly.pdf
Normal file
Binary file not shown.
BIN
dds_drawings.pdf
Normal file
BIN
dds_drawings.pdf
Normal file
Binary file not shown.
@ -1,50 +0,0 @@
|
||||
from artiq.experiment import *
|
||||
from scipy import signal
|
||||
import numpy
|
||||
|
||||
|
||||
class Voltage(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.fastino = self.get_device("fastino")
|
||||
|
||||
def prepare(self):
|
||||
self.channels = [0, 1, 2, 3]
|
||||
self.voltages = [1.0, 2.0, 3.0, 4.0]
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.reset()
|
||||
self.core.break_realtime()
|
||||
self.fastino.init()
|
||||
|
||||
delay(1*ms)
|
||||
self.fastino.set_dac(self.voltages, self.channels)
|
||||
|
||||
|
||||
class TriangularWave(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.fastino = self.get_device("fastino")
|
||||
|
||||
def prepare(self):
|
||||
self.period = 0.1*s
|
||||
self.sample = 128
|
||||
t = numpy.linspace(0, 1, self.sample)
|
||||
self.voltages = 8*signal.sawtooth(2*numpy.pi*t, 0.5)
|
||||
self.interval = self.period/self.sample
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.reset()
|
||||
self.core.break_realtime()
|
||||
self.fastino.init()
|
||||
|
||||
delay(1*ms)
|
||||
|
||||
counter = 0
|
||||
while True:
|
||||
self.fastino.set_dac([self.voltages[counter]], [0])
|
||||
counter = (counter + 1) % self.sample
|
||||
delay(self.interval)
|
||||
|
||||
@ -1,27 +0,0 @@
|
||||
from artiq.experiment import *
|
||||
|
||||
|
||||
class Grabber(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.grabber = self.get_device("grabber")
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.break_realtime()
|
||||
delay(100*us)
|
||||
# setup ROI boundaries
|
||||
grabber.setup_roi(0, 0, 0, 2, 2)
|
||||
grabber.setup_roi(1, 0, 0, 2048, 2048)
|
||||
# enable through bitwise mask
|
||||
mask = 0b11
|
||||
grabber.gate_roi(mask)
|
||||
|
||||
# trigger the camera
|
||||
|
||||
# retrieves data from enabled ROIs
|
||||
n = [0] * 2
|
||||
grabber.input_mu(n)
|
||||
# disable ROIs
|
||||
self.core.break_realtime()
|
||||
grabber.gate_roi(0)
|
||||
@ -1,85 +0,0 @@
|
||||
from artiq.experiment import *
|
||||
|
||||
class SineWave(EnvExperiment):
|
||||
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.shuttler0_leds = (
|
||||
[ self.get_device("shuttler0_led{}".format(i)) for i in range(2) ]
|
||||
)
|
||||
self.setattr_device("shuttler0_config")
|
||||
self.setattr_device("shuttler0_trigger")
|
||||
self.shuttler0_dcbias = (
|
||||
[ self.get_device("shuttler0_dcbias{}".format(i)) for i in range(16) ]
|
||||
)
|
||||
self.shuttler0_dds = (
|
||||
[ self.get_device("shuttler0_dds{}".format(i)) for i in range(16) ]
|
||||
)
|
||||
self.setattr_device("shuttler0_relay")
|
||||
self.setattr_device("shuttler0_adc")
|
||||
|
||||
@kernel
|
||||
def relay_init(self):
|
||||
self.shuttler0_relay.init()
|
||||
self.shuttler0_relay.enable(0x0000)
|
||||
|
||||
@kernel
|
||||
def adc_init(self):
|
||||
delay_mu(int64(self.core.ref_multiplier))
|
||||
self.shuttler0_adc.power_up()
|
||||
|
||||
delay_mu(int64(self.core.ref_multiplier))
|
||||
assert self.shuttler0_adc.read_id() >> 4 == 0x038d
|
||||
|
||||
delay_mu(int64(self.core.ref_multiplier))
|
||||
# The actual output voltage is limited by the hardware,
|
||||
# the calculated calibration gain and offset.
|
||||
# For example, if the system has a calibration gain of
|
||||
# 1.06, then the max output voltage = 10 / 1.06 = 9.43V.
|
||||
# Setting a value larger than 9.43V will result in overflow.
|
||||
self.shuttler0_adc.calibrate(
|
||||
self.shuttler0_dcbias, self.shuttler0_trigger, self.shuttler0_config)
|
||||
|
||||
@kernel
|
||||
def shuttler_channel_reset(self, ch):
|
||||
self.shuttler0_dcbias[ch].set_waveform(
|
||||
a0=0, a1=0, a2=0, a3=0,
|
||||
)
|
||||
self.shuttler0_dds[ch].set_waveform(
|
||||
b0=0, b1=0, b2=0, b3=0,
|
||||
c0=0, c1=0, c2=0,
|
||||
)
|
||||
self.shuttler0_trigger.trigger(1 << ch)
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.reset()
|
||||
self.core.break_realtime()
|
||||
|
||||
self.relay_init()
|
||||
self.adc_init()
|
||||
|
||||
for i in range(16):
|
||||
self.shuttler_channel_reset(i)
|
||||
# To avoid RTIO Underflow
|
||||
delay(50*us)
|
||||
|
||||
@kernel
|
||||
def sine(self):
|
||||
for i in range(2):
|
||||
self.shuttler0_dcbias[i].set_waveform(
|
||||
a0=0,
|
||||
a1=0,
|
||||
a2=0,
|
||||
a3=0,
|
||||
)
|
||||
self.shuttler0_dds[i].set_waveform(
|
||||
b0=0x0FFF,
|
||||
b1=0,
|
||||
b2=0,
|
||||
b3=0,
|
||||
c0=0,
|
||||
c1=0x147AE148, # Frequency = 10MHz
|
||||
c2=0,
|
||||
)
|
||||
self.shuttler0_trigger.trigger(0xFFFF)
|
||||
@ -1,99 +0,0 @@
|
||||
from artiq.experiment import *
|
||||
|
||||
class SineWave(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
|
||||
self.leds = dict()
|
||||
self.ttl_outs = dict()
|
||||
|
||||
self.dacs_config = dict()
|
||||
self.dac_volt = dict()
|
||||
self.dac_dds = dict()
|
||||
self.dac_trigger = dict()
|
||||
|
||||
ddb = self.get_device_db()
|
||||
for name, desc in ddb.items():
|
||||
if isinstance(desc, dict) and desc["type"] == "local":
|
||||
module, cls = desc["module"], desc["class"]
|
||||
if (module, cls) == ("artiq.coredevice.ttl", "TTLOut"):
|
||||
dev = self.get_device(name)
|
||||
if "led" in name:
|
||||
self.leds[name] = dev
|
||||
else:
|
||||
self.ttl_outs[name] = dev
|
||||
|
||||
if (module, cls) == ("artiq.coredevice.shuttler", "Config"):
|
||||
dev = self.get_device(name)
|
||||
self.dacs_config[name] = dev
|
||||
|
||||
if (module, cls) == ("artiq.coredevice.shuttler", "Volt"):
|
||||
dev = self.get_device(name)
|
||||
self.dac_volt[name] = dev
|
||||
|
||||
if (module, cls) == ("artiq.coredevice.shuttler", "Dds"):
|
||||
dev = self.get_device(name)
|
||||
self.dac_dds[name] = dev
|
||||
|
||||
if (module, cls) == ("artiq.coredevice.shuttler", "Trigger"):
|
||||
dev = self.get_device(name)
|
||||
self.dac_trigger[name] = dev
|
||||
|
||||
|
||||
self.leds = sorted(self.leds.items(), key=lambda x: x[1].channel)
|
||||
self.ttl_outs = sorted(self.ttl_outs.items(), key=lambda x: x[1].channel)
|
||||
|
||||
self.dacs_config = sorted(self.dacs_config.items(), key=lambda x: x[1].channel)
|
||||
self.dac_volt = sorted(self.dac_volt.items(), key=lambda x: x[1].channel)
|
||||
self.dac_dds = sorted(self.dac_dds.items(), key=lambda x: x[1].channel)
|
||||
self.dac_trigger = sorted(self.dac_trigger.items(), key=lambda x: x[1].channel)
|
||||
|
||||
|
||||
@kernel
|
||||
def set_dac_config(self, config):
|
||||
config.set_config(0xFFFF)
|
||||
|
||||
@kernel
|
||||
def set_test_dac_volt(self, volt):
|
||||
a0 = 0
|
||||
a1 = 0
|
||||
a2 = 0
|
||||
a3 = 0
|
||||
volt.set_waveform(a0, a1, a2, a3)
|
||||
|
||||
|
||||
@kernel
|
||||
def set_test_dac_dds(self, dds):
|
||||
b0 = 0x0FFF
|
||||
b1 = 0
|
||||
b2 = 0
|
||||
b3 = 0
|
||||
c0 = 0
|
||||
c1 = 0x147AE148 # Frequency = 10MHz
|
||||
c2 = 0
|
||||
dds.set_waveform(b0, b1, b2, b3, c0, c1, c2)
|
||||
|
||||
@kernel
|
||||
def set_dac_trigger(self, trigger):
|
||||
trigger.trigger(0xFFFF)
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.reset()
|
||||
|
||||
self.core.break_realtime()
|
||||
t = now_mu() - self.core.seconds_to_mu(0.2)
|
||||
while self.core.get_rtio_counter_mu() < t:
|
||||
pass
|
||||
|
||||
for dac_config_name, dac_config_dev in self.dacs_config:
|
||||
self.set_dac_config(dac_config_dev)
|
||||
|
||||
for dac_volt_name, dac_volt_dev in self.dac_volt:
|
||||
self.set_test_dac_volt(dac_volt_dev)
|
||||
|
||||
for dac_dds_name, dac_dds_dev in self.dac_dds:
|
||||
self.set_test_dac_dds(dac_dds_dev)
|
||||
|
||||
for dac_trigger_name, dac_trigger_dev in self.dac_trigger:
|
||||
self.set_dac_trigger(dac_trigger_dev)
|
||||
@ -6,7 +6,7 @@ import numpy
|
||||
class Voltage(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.zotino = self.get_device("zotino")
|
||||
self.zotino = self.get_device("zotino0")
|
||||
|
||||
def prepare(self):
|
||||
self.channels = [0, 1, 2, 3]
|
||||
@ -25,7 +25,7 @@ class Voltage(EnvExperiment):
|
||||
class TriangularWave(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.zotino = self.get_device("zotino")
|
||||
self.zotino = self.get_device("zotino0")
|
||||
|
||||
def prepare(self):
|
||||
self.period = 0.1*s
|
||||
@ -44,6 +44,6 @@ class TriangularWave(EnvExperiment):
|
||||
|
||||
counter = 0
|
||||
while True:
|
||||
self.zotino.write_dac([self.voltages[counter]], [0])
|
||||
self.zotino.set_dac([self.voltages[counter]], [0])
|
||||
counter = (counter + 1) % self.sample
|
||||
delay(self.interval)
|
||||
delay(self.interval)
|
||||
|
||||
27
flake.lock
generated
27
flake.lock
generated
@ -1,27 +0,0 @@
|
||||
{
|
||||
"nodes": {
|
||||
"nixpkgs": {
|
||||
"locked": {
|
||||
"lastModified": 1744440957,
|
||||
"narHash": "sha256-FHlSkNqFmPxPJvy+6fNLaNeWnF1lZSgqVCl/eWaJRc4=",
|
||||
"owner": "NixOS",
|
||||
"repo": "nixpkgs",
|
||||
"rev": "26d499fc9f1d567283d5d56fcf367edd815dba1d",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
"owner": "NixOS",
|
||||
"ref": "nixos-24.11",
|
||||
"repo": "nixpkgs",
|
||||
"type": "github"
|
||||
}
|
||||
},
|
||||
"root": {
|
||||
"inputs": {
|
||||
"nixpkgs": "nixpkgs"
|
||||
}
|
||||
}
|
||||
},
|
||||
"root": "root",
|
||||
"version": 7
|
||||
}
|
||||
41
flake.nix
41
flake.nix
@ -1,41 +0,0 @@
|
||||
{
|
||||
description = "Sinara datasheets";
|
||||
|
||||
inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.11;
|
||||
|
||||
outputs = { self, nixpkgs }:
|
||||
let
|
||||
pkgs = import nixpkgs { system = "x86_64-linux";};
|
||||
|
||||
latex-pkgs = pkgs.texlive.combine {
|
||||
inherit (pkgs.texlive)
|
||||
scheme-small collection-latexextra collection-fontsextra
|
||||
collection-fontsrecommended cbfonts-fd cbfonts palatino textgreek helvetic
|
||||
greek-inputenc maths-symbols mathpazo babel isodate tcolorbox etoolbox
|
||||
pgfplots visualtikz quantikz tikz-feynman circuitikz
|
||||
minted pst-graphicx;
|
||||
};
|
||||
|
||||
python-pkgs = with pkgs.python3Packages; [ pygments ];
|
||||
|
||||
in rec {
|
||||
|
||||
all-pdfs = pkgs.stdenvNoCC.mkDerivation rec {
|
||||
name = "datasheets-pdfs";
|
||||
src = self;
|
||||
buildInputs = [ latex-pkgs ] ++ python-pkgs;
|
||||
buildPhase = ''
|
||||
make all
|
||||
'';
|
||||
installPhase = ''
|
||||
mkdir $out
|
||||
cp build/*.pdf $out
|
||||
'';
|
||||
};
|
||||
|
||||
devShells.x86_64-linux.default = pkgs.mkShell {
|
||||
name = "datasheet-dev-shell";
|
||||
buildInputs = [ latex-pkgs ] ++ python-pkgs;
|
||||
};
|
||||
};
|
||||
}
|
||||
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idc_cm_choke.pdf
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lvds_ttl_switches.jpg
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|
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Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user