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216
1124.tex
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\include{preamble.tex}
\graphicspath{{images/1124}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfigure}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usepackage{pifont}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{1124 Carrier Kasli 2.0}
\author{M-Labs Limited}
\date{October 2024}
\revision{Revision 2}
\date{January 2022}
\revision{Revision 1}
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
\begin{document}
@ -13,32 +33,46 @@
\section{Features}
\begin{itemize}
\item{4 SFP 6Gb/s slots for Ethernet and DRTIO}
\item{12 EEM ports for daughtercards}
\item{4 MMCX clock outputs}
\item{Xilinx Artix-7 FPGA core}
\item{DDR3 SDRAM}
\item{4 SFP 6Gb/s slots for Ethernet or DRTIO.}
\item{12 EEM Connectors.}
\item{4 MMCX clock outputs.}
\item{FPGA core device.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Run ARTIQ kernels}
\item{Communicate with the host}
\item{Control other Sinara EEM cards}
\item{Distributed Real-Time I/O}
\item{Runs ARTIQ kernels.}
\item{Control the EEMs.}
\item{Communication with the host.}
\end{itemize}
\section{General Description}
The 1124 Kasli 2.0 Carrier card is an 8hp EEM module, designed to run ARTIQ kernels sent from a host machine over the network. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections, used for comunications with other carriers and/or Ethernet.
The 1124 Carrier Kasli 2.0 card is a 8hp EEM module.
It controls the EEMs by running ARTIQ kernels sent from the host.
Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
It supports 12 EEM connections to other EEM cards in the ARTIQ Sinara family.
Real-time control of the EEMs are implemented using the RTIO system.
1ns temporal resolution can be achieved for TTL events.
4 SFP 6Gb/s slots are provided. One may be used for Ethernet, which supports communication with a host machine. Remaining slots can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the \mbox{DRTIO} master.
4 SFP 6Gb/s slots are supported for Ethernet or DRTIO.
Communication with the host is supported by the Ethernet, while the
Distributed Real Time Input/Output (DRTIO) system allows inclusion of
additional core devices (e.g. Kasli 2.0) as DRTIO satellites,
indirectly controlled by the DRTIO Master.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{1.15}{
@ -63,7 +97,7 @@ Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO syste
% USB Mirco B port with USB-UART converter, north west of the FPGA
\draw (-3.2, 1.2) node[twoportshape, t={USB Micro B}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (usb) {};
\draw (-2, 1.2) node[twoportshape, t={\fourcm{USB-UART}{Converter}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (uart) {};
\draw (-2, 1.2) node[twoportshape, t={\MymyLabel{USB-UART}{Converter}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (uart) {};
\draw [latexslim-latexslim] (usb.north) -- (uart.south);
\draw [latexslim-latexslim] (uart.north) -- (-1.3, 1.2) -- (-1.3, 0.4) -- (-0.85, 0.4);
@ -76,8 +110,8 @@ Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO syste
% Clock signal cleaning path, south of the FPGA,
% clock signal loop from the south west to the south east
\draw (-0.8, -2.1) node[twoportshape, t={\fourcm{Clock}{Multiplier}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_mul) {};
\draw (0.8, -2.1) node[twoportshape, t={\fourcm{Clock}{Buffer}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_buf) {};
\draw (-0.8, -2.1) node[twoportshape, t={\MymyLabel{Clock}{Multiplier}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_mul) {};
\draw (0.8, -2.1) node[twoportshape, t={\MymyLabel{Clock}{Buffer}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_buf) {};
\draw [-latexslim] (-0.85, -0.8) -- (-1.6, -0.8) -- (-1.6, -1.9) -- (-1.05, -1.9);
% % A dashed path from EXT CLK to CDR CLK
\draw [dashed, -latexslim] (fpga.west) -- (-0.6, 0) -- (-0.6, -0.8) -- (-0.85, -0.8);
@ -130,7 +164,7 @@ Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO syste
\draw [-latexslim] (1.6, -2.1) -- (mmcx3);
% Memory modules, north of the FPGA
\draw (-0.55, 2.4) node[twoportshape, t={\fourcm{SPI}{Flash}}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (spi_flash) {};
\draw (-0.55, 2.4) node[twoportshape, t={\MymyLabel{SPI}{Flash}}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (spi_flash) {};
\draw (0.55, 2.4) node[twoportshape, t={SDRAM}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (sdram) {};
\draw [latexslim-latexslim] (spi_flash.south) -- (-0.55, 1.05);
\draw [latexslim-latexslim] (sdram.south) -- (0.55, 1.05);
@ -152,28 +186,19 @@ Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO syste
\begin{figure}[hbt!]
\centering
\includegraphics[height=2in]{Kasli_FP.pdf}
\includegraphics[height=2in]{photo1124.jpg}
\caption{Kasli 2.0 card}
\end{figure}
\begin{figure}[hbt!]
\centering
\includegraphics[angle=90,height=0.9in]{Kasli_FP.pdf}
\caption{Kasli 2.0 front panel}
\caption{Kasli 2.0 Card photo}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{Kasli 2.0}{https://github.com/sinara-hw/Kasli}
\section{Electrical Specifications}
External clock parameters are derived based on the internal termination specified in
UG471\footnote{\label{ug471}\url{https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO}}
and the voltage range specified in
DS181\footnote{\label{ds181}\url{https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
External clock parameters are derived based on the internal termination specified in UG471\footnote{\label{ug471}https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO},
and the voltage range specified in DS181\footnote{\label{ds181}https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}.
The figure had accounted for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}).
\begin{table}[h]
\centering
\begin{threeparttable}
@ -187,7 +212,7 @@ DS181\footnote{\label{ds181}\url{https://docs.xilinx.com/v/u/en-US/ds181\_Artix\
\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
\cline{2-6}
% 100R termination & 100/350/600 mV differential input after the transformer.
& \multicolumn{3} {c|}{10/100/125} & MHz & RTIO clock synthesized from input \\
& \multicolumn{4}{c|}{10/100/125 MHz} & RTIO clock synthesized from input \\
\cline{2-6}
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
\hline
@ -197,49 +222,41 @@ DS181\footnote{\label{ds181}\url{https://docs.xilinx.com/v/u/en-US/ds181\_Artix\
\end{threeparttable}
\end{table}
Power is to be supplied through the barrel connector in the front panel, size 5.5 mm OD, 2.5 mm ID, and is passed on to daughtercards through the EEM connections. Locking barrel connectors are supported.
\section{FPGA}
Kasli 2.0 features an XC7A100T-3FGG484E Xilinx Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.
ARTIQ is open-source and can be found in the repository \url{https://github.com/m-labs/artiq}. Orders of Sinara hardware are normally accompanied with precompiled binaries. Long-term support for ARTIQ systems can also be purchased.
A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
\subsection{Note on distributed RTIO (DRTIO)}
DRTIO is the time and data transfer system that allows ARTIQ RTIO channels to be distributed among several core device carrier boards, synchronized and controlled by a central core device. The system itself is more fully described in the ARTIQ documentation\footnote{\label{manual-drtio}\url{https://m-labs.hk/artiq/manual/drtio.html}}. With ARTIQ firmware/gateware, supported core devices, including Kasli 2.0, can take one of three roles:
\section{Distributed RTIO (DRTIO)}
DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central core device.
Multiple core devices (e.g. Kasli 2.0) can be interconnected through DRTIO. All core devices in the DRTIO system are classified as 1 of the 2 roles:
\begin{enumerate}
\item \textbf{Master} \\
The DRTIO master is unique in a DRTIO system. It requires a direct network connection to the host machine. It may make downstream connections to satellites. It controls its own local RTIO channels and the downstream DRTIO satellite(s).
\item \textbf{Satellite} \\
Any other core devices in a DRTIO system are DRTIO satellites. They require an upstream connection to one other core device, master or satellite, through which communications will ultimately be chained to the master. They may make further downstream connections to other satellites. They may control RTIO channels through subkernels or simply pass on communications from the master.
\item \textbf{Standalone}\\
When run in a non-distributed ARTIQ configuration, with a single central core device but no satellites, that core device is instead known as standalone.
\item DRTIO Master \\
The DRTIO master is unique in a DRTIO system. It controls the DRTIO satellites(s) and local RTIO channels.
\item DRTIO Satellite \\
The rest of the core devices are DRTIO satellites. DRTIO satellites need an upstream connection to one other core devices (master or satellite).
It may provide downstream conenction to other DRTIO satellties.
\end{enumerate}
\section{Communication Interfaces}
Communication between devices is implemented using 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on the Kasli 2.0. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
\subsection{Upstream connection}
A Kasli 2.0 board must acquire an upstream connection through the \texttt{SFP0} slot.
\section{Network Interface}
Communication between the host and the core device(s) is implemented using small form-factor pluggable (SFP) interfaces.
Approprate SFP transceivers must be plugged inside the corresponding SFP cages to enable communication between core devices.
\subsection{Upstream Connection}
A core device (e.g. Kasli 2.0) must acquire an upstream network connection through the \texttt{SFP0} slot.
\begin{itemize}
\item \textbf{Standalone/Master} \\
An Ethernet-capable SFP transceiver should be inserted into the \texttt{SFP0} slot. Typically, a 10000Base-X RJ45 SFP module is used, with an network-connected Ethernet cable attached to the module.
\item \textbf{Satellite} \\
The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable connection with SFP transceivers.
\item Standalone/DRTIO master \\
An Ethernet capable SFP transceiver must be inserted to the \texttt{SFP0} slot.
Typically, a RJ45 SFP module is inserted to the slot with an Ethernet cable with network connection attached to the module.
\item DRTIO Satellite \\
The \texttt{SFP0} port of DRTIO satellite should be connected to an appropriate SFP slot of the upstream core device (DRTIO master or satellite) with cable connection with SFP transceivers.
\end{itemize}
\subsection{Downstream connection}
Kasli 2.0 supports up to 3 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be used.
\subsection{Downstream Connection}
The 1124 Carrier Kasli 2.0 supports up to 3 DRTIO satellite connections per device.
DRTIO satellites can be connected using any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) through cable connections with SFP transceivers.
\section{Clock Routing}
\subsection{Standalone/Master}
The RTIO clock is typically synthesized by the Si5324 clock multiplier and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors. Alternatively, an external reference can be supplied through the front panel SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis. Kasli 2.0 supports a set of RTIO clock options:
\subsection{DRTIO Master/Standalone}
The RTIO clock is typically synthesized by the Si5324 clock multiplier, and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors.
An external reference can be supplied to synthesize the clock, which is supplied to the SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis.
Kasli 2.0 supports a set of clock systhesizing options for the (D)RTIO system:
\begin{table}[H]
\centering
\begin{tabular}{|c|c|c|}
@ -253,55 +270,60 @@ The RTIO clock is typically synthesized by the Si5324 clock multiplier and distr
150 MHz & \texttt{int\char`_150} & internal crystal oscillator using PLL, 150 MHz output \\ \hline
\end{tabular}
\end{table}
Alternatively, the clock synthesizer can be bypassed using the \texttt{ext0\char`_bypass} clocking option, where the RTIO clock is directly supplied to the SMA connector.
The resulting clock signal is then routed to both the RTIO system and downstream DRTIO satellites.
The clock synthesizer may also be bypassed, using the \texttt{ext0\char`_bypass} option, which will accept a RTIO clock directly supplied to the SMA connector. The resulting signal is then routed to both the RTIO system and downstream satellites.
Clocking options in a running system should be configured by setting the value of the \texttt{rtio\char`_clock} key to the desired configuration through \texttt{artiq\char`_coremgmt}. For example, a RTIO frequency of 125MHz will be synthesized from an external 10 MHz signal after issuing the following command:
Clocking options should be configured by setting the value of the \texttt{rtio} key to the desired configuration through \texttt{artiq\char`_coremgmt}.
For example, the RTIO frequency is synthesized from the external 10 MHz from the SMA connector after issuing the following command.
\begin{minted}{bash}
artiq_coremgmt config write -s rtio_clock ext0_synth0_10to125
artiq_coremgmt config write -s rtio ext0_synth0_10to125
\end{minted}
and rebooting.
\subsection{Satellite}
The RTIO clock is recovered from the SFP transceiver connected to the upstream device. The resulting signal is then cleaned up by the Si5324 and routed to both the RTIO system and downstream satellites.
\subsection{WRPLL}
Kasli 2.0 can be configured to use WRPLL, a clock recovery method making use of White Rabbit's DDMTD (Digital Dual Mixer Time Difference) and the card's Si549 oscillators, both to lock the main RTIO clock and to lock satellite clocks to master.
\section{User LEDs}
Kasli 2.0 supplies three user LEDs for debugging purposes. Two are located on the front panel. The third is located on the PCB itself, beside the SFP cage. An additional ERR LED on the front panel is used by ARTIQ firmware to indicate a runtime panic.
\subsection{DRTIO Satellite}
The RTIO clock is first recovered from the SFP transceiver connected to the upstream device. The signal is then cleaned by Si5324 clock synthesizer.
The resulting clock signal is then routed to the RTIO system and downstream DRTIO satellties.
\newpage
\codesection{Kasli 2.0 1124 carrier}
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the system extensions of the ARTIQ control system.
These extensions make use of the resources on 1124 Carrier Kasli 2.0.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\subsection{Direct Memory Access (DMA)}
Instead of directly emitting RTIO events, sequences of RTIO events can be recorded in advance and stored in the local SDRAM. The event sequence can then be replayed at a specified timestamp. This is of special advantage in cases where RTIO events are too closely placed to be generated as they are executed, as events can be replayed at a higher speed than the on-FPGA CPU alone is capable of.
The following example records an LED event sequence and replays it twice consecutively using \texttt{CoreDMA}. When run, the LED should blink twice.
Instead of directly emitting RTIO events, a sequence of RTIO events can be recorded in advance and stored in the local SDRAM.
The event sequence can be replayed at another specified timestamp at a higher speed compared to the CPU alone.
The following example records an LED blinking sequence, and replayed twice consecutively using \texttt{CoreDMA}.
\texttt{led0} blinked twice in this example.
\inputcolorboxminted{firstline=10,lastline=29}{examples/dma.py}
Stored waveforms can be referenced and replayed in different kernels, but cannot be retrieved and must be regenerated if the core device is rebooted.
The stored waveform can be referenced and replayed in different kernels.
However, the waveform is no longer retrievable once core device is rebooted.
\newpage
\subsection{Dataset manipulation with core device cache}
Experiments may require values computed or found in previously executed kernels. To avoid invoking an RPC or sacrificing the pre-computation in \texttt{prepare()} stage, data can be stored in the core device cache.
The following code snippets describe two experiments, in which the data from the first experiment is cached. The data is then retrieved and printed in hexadecimal form in the second experiment.
\subsection{Dataset Manipulation with Core Device Cache}
Experiments may require values computed/found in previously executed kernels.
To avoid invoking an RPC/sacrificing the pre-computation in \texttt{prepare()} stage, data can be cached in the core device cache.
The following code snippets consists of 2 experiments, where the data from the first experiement is cached.
The same data is retrieved and printed as hexadecimal in the second experiment.
\inputcolorboxminted{firstline=9,lastline=16}{examples/cache.py}
\inputcolorboxminted{firstline=24,lastline=35}{examples/cache.py}
Similar to DMA, cached data is no longer retrievable once the core device has been rebooted.
Similar to DMA, the cached data is no longer retrievable once the core device is rebooted.
\ordersection{1124 Carrier Kasli 2.0}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 1124 Carrier Kasli 2.0 in the ARTIQ Sinara crate configuration tool.
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\finalfootnote
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

330
2118-2128.tex
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@ -1,5 +1,25 @@
\input{preamble.tex}
\graphicspath{{images/2118-2128}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfig}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usepackage{pifont}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{2118 BNC-TTL / 2128 SMA-TTL}
\author{M-Labs Limited}
@ -13,34 +33,45 @@
\section{Features}
\begin{itemize}
\item{8 TTL channels}
\item{Input- and output-capable}
\item{Galvanically isolated}
\item{3ns minimum pulse width}
\item{BNC or SMA connectors}
\item{8 channels.}
\item{Input and output capable.}
\item{Galvanically isolated.}
\item{3ns minimum pulse width.}
\item{BNC or SMA connectors.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Photon counting}
\item{External equipment trigger}
\item{Optical shutter control}
\item{Photon counting.}
\item{External equipment trigger.}
\item{Optical shutter control.}
\end{itemize}
\section{General Description}
The 2118 BNC-TTL card is a 8hp EEM module, while the 2128 SMA-TTL card is a 4hp EEM module.
Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides two banks of four digital channels each, with BNC (2118) or SMA (2128) connectors.
Each bank has individual ground isolation.
The direction (input or output) of each bank can be selected using DIP switches.
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
Outputs tolerate short circuits indefinitely.
The card support a minimum pulse width of 3ns.
Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely.
Both cards are capable of a minimum pulse width of 3ns.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{0.88}{
@ -88,6 +119,8 @@ Both cards are capable of a minimum pulse width of 3ns.
\draw (0,0) circle(0.8);
\end{scope}
\draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus1) {};
\draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso1) {};
@ -96,36 +129,36 @@ Both cards are capable of a minimum pulse width of 3ns.
\draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso4) {};
\draw (3.05,-2.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso1) {};
\draw (4.5,-1.15) node[twoportshape,t=\fourcm{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds1) {};
\draw (4.5,-1.15) node[twoportshape,t=\MymyLabel{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds1) {};
\draw (6.8,-0.9) -- ++(0.00001,0) node[twoportshape, anchor=left, t={EEM port}, circuitikz/bipoles/twoport/width=6, scale=0.6, rotate=-90] (kasli) {} ;
\draw (0.8,-3.5) node[twoportshape,t=\fourcm{Per-bank \phantom{spac} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
\draw (3.05,-3.5) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
\draw (0.8,-3.5) node[twoportshape,t=\MymyLabel{Per-bank \phantom{spac} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
\draw (3.05,-3.5) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
\draw (5.68,-2.3) node[twoportshape,t=EEPROM, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom) {};
\draw (0.8,-2.7) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
\draw (0.8,-2.7) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
% Termination Switch 1,2,3,4
\begin{scope}[xshift=0.9cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.2cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\end{scope}
@ -134,36 +167,36 @@ Both cards are capable of a minimum pulse width of 3ns.
\begin{scope}[xshift=1.2cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.32cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\draw (0.8,-3.05) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
\draw (0.8,-3.05) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
% Termination Switch 5,6,7,8
\begin{scope}[xshift=0.9cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.2cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
% channel 5,6,7,8
@ -217,7 +250,7 @@ Both cards are capable of a minimum pulse width of 3ns.
\draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso8) {};
\draw (3.05,0.6) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso2) {};
\draw (4.5,-1.05) node[twoportshape,t=\fourcm{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds2) {};
\draw (4.5,-1.05) node[twoportshape,t=\MymyLabel{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds2) {};
\end{scope}
@ -294,41 +327,47 @@ Both cards are capable of a minimum pulse width of 3ns.
\begin{figure}[hbt!]
\centering
\includegraphics[height=1.8in]{photo2118-2128.jpg }
\caption{BNC-TTL and SMA-TTL cards}%
\includegraphics[angle=90, height=0.7in]{DIO_BNC_FP.jpg}
\includegraphics[angle=90, height=0.4in]{DIO_SMA_FP.jpg}
\caption{BNC-TTL and SMA-TTL front panels}%
\subfloat[\centering BNC-TTL]{{
\includegraphics[height=1.8in]{DIO_BNC_FP.jpg}
\includegraphics[height=1.8in]{photo2118.jpg}
}}%
\subfloat[\centering SMA-TTL]{{
\includegraphics[height=1.8in]{DIO_SMA_FP.jpg}
\includegraphics[height=1.8in]{photo2128.jpg}
}}%
\caption{BNC-TTL/SMA-TTL Card photos}%
\label{fig:example}%
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesectiond{2118 BNC-TTL}{2128 SMA-TTL}{https://github.com/sinara-hw/DIO_BNC}{https://github.com/sinara-hw/DIO_SMA}
\section{Electrical Specifications}
All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
Specifications are based on the bus transceivers IC (SN74BCT25245DW\footnote{\label{transceiver}https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf})
and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}).
The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}https://github.com/sinara-hw/sinara/issues/187}.
\begin{table}[h]
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
High-level input voltage\repeatfootnote{transceiver} & $V_{IH}$ & 2 & & 5.5* & V & \\
\hline
Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
Low-level input voltage\repeatfootnote{transceiver} & $V_{IL}$ & -0.5 & & 0.8 & V & \\
\hline
Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
Input clamp current\repeatfootnote{transceiver} & $I_{OH}$ & & & -18 & mA & termination disabled \\
\hline
High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
High-level output current\repeatfootnote{transceiver} & $I_{OH}$ & & & -160 & mA & \\
\hline
Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
Low-level output current\repeatfootnote{transceiver} & $I_{OL}$ & & & 376 & mA & \\
\thickhline
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\end{tabularx}
\end{threeparttable}
\end{table}
@ -336,52 +375,165 @@ Specifications were derived based on the datasheets of the bus transceiver IC (S
\begin{table}[h]
\begin{threeparttable}
\caption{Electrical Characteristics}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
High-level output voltage\repeatfootnote{transceiver} & 2 & & & V & $I_{OH}$=-160mA \\
& 2.7 & & & V & $I_{OH}$=-6mA \\
High-level output voltage\repeatfootnote{transceiver} & $V_{OH}$ & 2 & & & V & $I_{OH}$=-160mA \\
& & 2.7 & & & V & $I_{OH}$=-6mA \\
\hline
Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
& & & 0.7 & V & $I_{OL}$=376mA \\
Low-level output voltage\repeatfootnote{transceiver} & $V_{OL}$ & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
& & & & 0.7 & V & $I_{OL}$=376mA \\
\hline
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & & 3 & 5 & ns & \\
\hline
Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns & \\
Pulse width distortion\repeatfootnote{isolator} & $PWD$ & & 0.2 & 4.5 & ns & \\
\hline
Peak jitter\repeatfootnote{isolator} & & 350 & & ps & \\
Peak jitter\repeatfootnote{isolator} & $T_{JIT(PK)}$ & & 350 & & ps & \\
\hline
Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
Data rate\repeatfootnote{isolator} & & 0 & & 150 & Mbps & \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
\newpage
\begin{figure}[ht]
Minimum pulse width was measured\repeatfootnote{sinara187}.
Pulses were generated from a DDS generator as an input of a BNC-TTL card.
The input BNC-TTL card is connected to another BNC-TTL card as an output.
The output signal is measured and shown.
\begin{figure}[h]
\centering
\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
\caption{Minimum pulse width required for BNC-TTL card}
\label{fig:pulsewidth}
\end{figure}
The red trace refers to the input pulses from the DDS generator, while the blue trace is the measured signal from the output BNC-TTL card.
Note that the first input (red) pulse could not propagate through the signal chain.
The first output (blue) pulse is the result of the second input (red, 3ns width) pulse.
\newpage
The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly.
\section{Front Panel Drawings}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=2.8in]{bnc_ttl_drawings.pdf}
\captionof{figure}{2118 BNC-TTL front panel drawings}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=2.8in]{bnc_ttl_assembly.pdf}
\captionof{figure}{2118 BNC-TTL front panel assembly}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\captionof{table}{Bill of Material (2118 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90560220 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\captionof{table}{Bill of Material (2118 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90457987 & 4 & CSCR M2.5*12.3 PAN PHL SS \\ \hline
2 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
3 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
4 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
5 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
6 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
7 & 3207076 & 0.01 & SCR M2.5*16 PAN 100 21101-222 \\ \hline
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
9 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
10 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT(100PCS) \\ \hline
11 & 90560220 & 1 & FP-LYKJ 3U8HP PANEL \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=3in]{sma_ttl_drawings.pdf}
\captionof{figure}{2128 SMA-TTL front panel drawings}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=3in]{sma_ttl_assembly.pdf}
\captionof{figure}{2128 SMA-TTL front panel assembly}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\captionof{table}{Bill of Material (2128 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90531967 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\captionof{table}{Bill of Material (2128 Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90531967 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3001012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
6 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
7 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
8 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\section{Configuring IO Direction \& Termination}
The termination and IO direction can be configured by switches.
The per-channel termination and per-bank IO direction switches are found at the middle-left and middle-right of both cards respectively.
IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank.
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
IO direction switches partly decides the IO direction of each bank.
\begin{itemize}
\itemsep0em
\item IO direction switch closed (\texttt{ON}) \\
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
\item IO direction switch open (OFF) \\
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
\item Closed switch (ON) \\
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
\item Opened switch (OFF) \\
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
\end{itemize}
\begin{figure}[hbt!]
@ -396,9 +548,12 @@ IO direction and termination must be configured by setting physical switches on
\end{figure}
\newpage
\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 2118 BNC-TTL/2128 SMA-TTL card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
\subsection{One pulse per second}
The channel should be configured as output in both the gateware and hardware.
@ -410,13 +565,15 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
\newpage
\subsection{Sub-coarse-RTIO-cycle pulse}
With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
With the use of the ARTIQ RTIO, only 1 event can be enqueued per coarse RTIO cycle, which is typically 8ns.
Therefore, to emit a pulse that is less than 8ns, additional delay is needed such that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted at different coarse RTIO cycles.
The TTL pulse must satisfy the minimum pulse width stated in the electircal specifications.
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
\subsection{Edge counting in a 1ms window}
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
The channel should be configured as input in both the gateware and hardware. Invoke one of the 3 methods to start edge detection.
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
@ -424,34 +581,41 @@ The detected edges are registered to the RTIO input FIFO. By default, the FIFO c
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
The RTIO system can report at most 1 edge detection event for every coarse RTIO cycle.
For example, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is 1 coarse RTIO cycle (typically 8 ns) with consideration of the RTIO specification alone.
However, both the electircal specifications and the possibility of triggering \texttt{RTIOOverflow} should be considered.
\newpage
\subsection{Edge counting using \texttt{EdgeCounter}}
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
This example code uses the gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second.
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle.
Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
\subsection{Responding to an external trigger}
One channel needs to be configured as input, and the other as output.
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
\subsection{62.5 MHz clock signal generation}
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal.
Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle.
Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2. \\
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
\newpage
\subsection{Minimum sustained event separation}
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
\subsection{Minimum Sustained Event Separation}
The minimum sustained event separation is the least amount of time separation between input gated events, in which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions.
The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
\begin{center}
\begin{table}[H]
\captionof{table}{Minimum sustained event separation of different carriers}
\captionof{table}{Minimum sustained event separation of different carrier}
\centering
\begin{tabular}{|c|c|c|}
\hline
@ -461,8 +625,14 @@ The minimum sustained event separation is the least time separation between inpu
\end{table}
\end{center}
\ordersection{2118 BNC-TTL/2128 SMA-TTL}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\finalfootnote
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

208
2238.tex
View File

@ -1,5 +1,24 @@
\input{preamble.tex}
\graphicspath{{images/2238}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfig}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{2238 MCX-TTL}
\author{M-Labs Limited}
@ -13,32 +32,43 @@
\section{Features}
\begin{itemize}
\item{16 MCX-TTL channels}
\item{Input and output capable}
\item{No galvanic isolation}
\item{High speed and low jitter}
\item{MCX connectors}
\item{16 channels.}
\item{Input and output capable.}
\item{No galvanic isolation.}
\item{High speed and low jitter.}
\item{MCX connectors.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Photon counting}
\item{External equipment trigger}
\item{Optical shutter control}
\item{Photon counting.}
\item{External equipment trigger.}
\item{Optical shutter control.}
\end{itemize}
\section{General Description}
The 2238 MCX-TTL card is a 4hp EEM module.
It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
Each card provides four banks of four digital channels each, with MCX connectors, controlled through 2 EEM connectors.
Each EEM connector controls two banks independently.
Single EEM operation is possible.
The direction (input or output) of each bank can be selected using DIP switches.
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{0.88}{
@ -211,100 +241,100 @@ Each channel supports 50\textOmega~terminations individually controllable using
\node[fill=white, scale=0.7, rotate=-90] at (bank3.west) {Bank 3};
% Draw bus transceivers
\draw (3.25, -0.7) node[twoportshape,t=\fourcm{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus0) {};
\draw (3.25, -5.6) node[twoportshape,t=\fourcm{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus1) {};
\draw (3.25, -0.7) node[twoportshape,t=\MymyLabel{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus0) {};
\draw (3.25, -5.6) node[twoportshape,t=\MymyLabel{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus1) {};
% Draw termination switches
% Bus transceiver 0
\draw (1.7, 1.2) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch0) {};
\draw (1.7, 1.2) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch0) {};
\begin{scope}[xshift=1.8cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.9cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=2.0cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=2.1cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
% Bus transceiver 1
\draw (1.5, -2.6) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
\draw (1.5, -2.6) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
\begin{scope}[xshift=1.6cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.7cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.8cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.9cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
% Bus transceiver 2
\draw (1.7, -3.7) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
\draw (1.7, -3.7) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
\begin{scope}[xshift=1.8cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.9cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=2cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=2.1cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
% Bus transceiver 3
\draw (1.5, -7.5) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch3) {};
\draw (1.5, -7.5) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch3) {};
\begin{scope}[xshift=1.6cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.7cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.8cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=1.9cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
% Connection termination switches to each IO line
@ -354,39 +384,39 @@ Each channel supports 50\textOmega~terminations individually controllable using
\draw [latexslim-latexslim] (mcx15) -- (2.9, -7);
% Draw LVDS transceivers
\draw (5.05, -0.025) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds0) {};
\draw (5.05, -1.675) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds1) {};
\draw (5.05, -4.625) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds2) {};
\draw (5.05, -6.275) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds3) {};
\draw (5.05, -0.025) node[twoportshape,t={\MymyLabel{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds0) {};
\draw (5.05, -1.675) node[twoportshape,t={\MymyLabel{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds1) {};
\draw (5.05, -4.625) node[twoportshape,t={\MymyLabel{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds2) {};
\draw (5.05, -6.275) node[twoportshape,t={\MymyLabel{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds3) {};
% Aesthetic EEPROM at each end of LVDS transceivers
\draw (5.05, 1.1) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom0) {};
\draw (5.05, -7.4) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom1) {};
% I/O expander
\draw (6.65, -3.5) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
\draw (6.65, -3.5) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
% I/O direction switches
\draw (5.05, -2.8) node[twoportshape,t=\fourcm{Per-bank \phantom{space} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
\draw (5.05, -2.8) node[twoportshape,t=\MymyLabel{Per-bank \phantom{space} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
\begin{scope}[xshift=5.3cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=5.4cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=5.5cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
\begin{scope}[xshift=5.6cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
% EEM Ports
@ -437,66 +467,65 @@ Each channel supports 50\textOmega~terminations individually controllable using
\begin{figure}[hbt!]
\centering
\includegraphics[height=1.8in]{DIO_MCX_FP.pdf}
\includegraphics[height=2in]{photo2238.jpg}
\caption{MCX-TTL card}
\includegraphics[angle=90, height=0.6in]{DIO_MCX_FP.pdf}
\caption{MCX-TTL front panel}
\caption{MCX-TTL Card photo}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{2238 MCX-TTL}{https://github.com/sinara-hw/DIO_MCX/wiki}
\section{Electrical Specifications}
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
Both recommended operating conditions and electrical characteristics are based on the datasheet of the bus transceivers IC (74LVT162245MTD\footnote{\label{transceiver}https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}).
\begin{table}[h]
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Input voltage & 0 & & 5.5* & V \\
Input voltage & $V_{I}$ & 0 & & 5.5* & V \\
\hline
High-level output current & & & -24 & mA \\
High-level output current & $I_{OH}$ & & & -24 & mA \\
\hline
Low-level output current & & & 24 & mA \\
Low-level output current & $I_{OL}$ & & & 24 & mA \\
\hline
Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
Input edge rate & $\frac{\Delta t}{\Delta V}$ & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
\thickhline
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\end{tabularx}
\end{threeparttable}
\end{table}
The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
All specifications are in the recommended operating temperature range unless otherwise noted.
\begin{table}[h]
\begin{threeparttable}
\caption{Electrical Characteristics}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
Input clamp diode voltage & $V_{IK}$ & & & -1.2 & V & $I_I =-36 mA$ \\
\hline
Input high voltage & 2.0 & & & V & \\
Input high voltage & $V_{IH}$ & 2.0 & & & V & \\
\hline
Input low voltage & & & 0.8 & V & \\
Input low voltage & $V_{IL}$ & & & 0.8 & V & \\
\hline
Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
& 3.1 & & & V & $I_{OH}=-200\mu A$ \\
Output high voltage & $V_{OH}$ & 2.0 & & & V & $I_{OH}=-24mA$ \\
& & 3.1 & & & V & $I_{OH}=-200\mu A$ \\
\hline
Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
& & & 0.2 & V & $I_{OL}=-200\mu A$ \\
Output low voltage & $V_{OL}$ & & & 0.8 & V & $I_{OL}=-24mA$ \\
& & & & 0.2 & V & $I_{OL}=-200\mu A$ \\
\hline
Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
& & & 2 & \textmu A & $V_I=3.3V$ \\
& & & -10 & \textmu A & $V_I=0V$ \\
Input current & $I_I$ & & & 20 & \textmu A & $V_I=5.5V$ \\
& & & & 2 & \textmu A & $V_I=3.3V$ \\
& & & & -10 & \textmu A & $V_I=0V$ \\
\thickhline
\end{tabularx}
\end{threeparttable}
@ -505,16 +534,18 @@ All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherw
\newpage
\section{Configuring IO Direction \& Termination}
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
The termination and IO direction can be configured by switches.
The per-channel termination and per-bank IO direction switches are found at the top and middle of the card respectively.
\begin{multicols}{2}
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
IO direction switches partly decides the IO direction of each bank.
\begin{itemize}
\itemsep0em
\item IO direction switch closed (\texttt{ON}) \\
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
\item IO direction switch open (OFF) \\
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
\item Closed switch (ON) \\
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
\item Opened switch (OFF) \\
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
\end{itemize}
\columnbreak
\begin{center}
@ -525,9 +556,12 @@ Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note th
\end{multicols}
\newpage
\codesection{2238 MCX-TTL card}
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
\subsection{One pulse per second}
The channel should be configured as output in both the gateware and hardware.
@ -538,8 +572,8 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
\newpage
\subsection{Edge counting in an 1ms window}
The channel should be configured as input in both gateware and hardware.
\subsection{Counting rising edges in a 1ms window}
The channel should be configured as input in both the gateware and hardware.
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
@ -550,8 +584,14 @@ If the gateware counter is enabled on the TTL channel, it can typically count up
One channel needs to be configured as input, and the other as output.
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
\ordersection{2238 MCX-TTL}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2238 MCX-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\finalfootnote
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

219
2245.tex
View File

@ -1,5 +1,24 @@
\input{preamble.tex}
\graphicspath{{images/2245}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfig}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\usepackage{tikz-timing}
\usetikztiminglibrary{counters}
@ -16,47 +35,62 @@
\section{Features}
\begin{itemize}
\item{16 LVDS-TTL channels.}
\item{Input- and output-capable}
\item{No galvanic isolation}
\item{High speed and low jitter}
\item{RJ45 connectors}
\item{16 LVDS channels.}
\item{Input and output capable.}
\item{No galvanic isolation.}
\item{High speed and low jitter.}
\item{RJ45 connectors.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Photon counting}
\item{External equipment trigger}
\item{Optical shutter control}
\item{Serial communication with remote devices}
\item{Photon counting.}
\item{External equipment trigger.}
\item{Optical shutter control.}
\item{Serial communication to remote devices.}
\end{itemize}
\section{General Description}
The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 2245 LVDS-TTL card is a 4hp EEM module.
It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
Each card provides sixteen digital channels each, controlled through 2 EEM connectors.
Each EEM connector controls eight channels independently.
Single EEM operation is possible.
Each RJ45 connector exposes four digital channels in the LVDS format.
The direction (input or output) of each channel can be selected using DIP switches.
Outputs are intended to drive 100\textOmega~loads, inputs are 100\textOmega~terminated.
This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
Only shielded Ethernet Cat-6 cables should be connected.
Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\inputcolorboxminted}[3][4]{%
\begin{tcolorbox}[colback=white]
\inputminted[#2, gobble=#1]{python}{#3}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{0.88}{
\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
% RJ45 Connectors
\draw (0, 2.8) node[twoportshape, t={\twocm{RJ45}{CH 0-3}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth0) {};
\draw (0, 1.0) node[twoportshape, t={\twocm{RJ45}{CH 4-7}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth1) {};
\draw (0, -1.0) node[twoportshape, t={\twocm{RJ45}{CH 8-11}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth2) {};
\draw (0, -2.8) node[twoportshape, t={\twocm{RJ45}{CH 12-15}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth3) {};
\draw (0, 2.8) node[twoportshape, t={\MyLabel{RJ45}{CH 0-3}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth0) {};
\draw (0, 1.0) node[twoportshape, t={\MyLabel{RJ45}{CH 4-7}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth1) {};
\draw (0, -1.0) node[twoportshape, t={\MyLabel{RJ45}{CH 8-11}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth2) {};
\draw (0, -2.8) node[twoportshape, t={\MyLabel{RJ45}{CH 12-15}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth3) {};
% Repeaters for channels
% Channel 7 repeaters
\draw (1.8, 0.4) node[twoportshape, t={\twocm{CH 7}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep7) {};
\draw (1.8, 0.4) node[twoportshape, t={\MyLabel{CH 7}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep7) {};
% Omission dots
\node at (1.8, 0.8)[circle,fill,inner sep=0.7pt]{};
@ -64,10 +98,10 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
\node at (1.8, 1.2)[circle,fill,inner sep=0.7pt]{};
% Channel 4 repeaters
\draw (1.8, 1.6) node[twoportshape, t={\twocm{CH 4}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep4) {};
\draw (1.8, 1.6) node[twoportshape, t={\MyLabel{CH 4}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep4) {};
% Channel 3 repeaters
\draw (1.8, 2.2) node[twoportshape, t={\twocm{CH 3}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep3) {};
\draw (1.8, 2.2) node[twoportshape, t={\MyLabel{CH 3}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep3) {};
% Omission dots
\node at (1.8, 2.6)[circle,fill,inner sep=0.7pt]{};
@ -75,10 +109,10 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
\node at (1.8, 3.0)[circle,fill,inner sep=0.7pt]{};
% Channel 0 repeaters
\draw (1.8, 3.4) node[twoportshape, t={\twocm{CH 0}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep0) {};
\draw (1.8, 3.4) node[twoportshape, t={\MyLabel{CH 0}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep0) {};
% Channel 8 repeaters
\draw (1.8, -0.4) node[twoportshape, t={\twocm{CH 8}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep8) {};
\draw (1.8, -0.4) node[twoportshape, t={\MyLabel{CH 8}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep8) {};
% Omission dots
\node at (1.8, -0.8)[circle,fill,inner sep=0.7pt]{};
@ -86,10 +120,10 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
\node at (1.8, -1.2)[circle,fill,inner sep=0.7pt]{};
% Channel 11 repeaters
\draw (1.8, -1.6) node[twoportshape, t={\twocm{CH 11}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep11) {};
\draw (1.8, -1.6) node[twoportshape, t={\MyLabel{CH 11}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep11) {};
% Channel 12 repeaters
\draw (1.8, -2.2) node[twoportshape, t={\twocm{CH 12}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep12) {};
\draw (1.8, -2.2) node[twoportshape, t={\MyLabel{CH 12}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep12) {};
% Omission dots
\node at (1.8, -2.6)[circle,fill,inner sep=0.7pt]{};
@ -97,11 +131,11 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
\node at (1.8, -3.0)[circle,fill,inner sep=0.7pt]{};
% Channel 15 repeaters
\draw (1.8, -3.4) node[twoportshape, t={\twocm{CH 15}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep15) {};
\draw (1.8, -3.4) node[twoportshape, t={\MyLabel{CH 15}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep15) {};
% Direction switches
\draw (4.6, 0.4) node[twoportshape,t=\fourcm{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch0) {};
\draw (4.6, -0.4) node[twoportshape,t=\fourcm{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch1) {};
\draw (4.6, 0.4) node[twoportshape,t=\MymyLabel{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch0) {};
\draw (4.6, -0.4) node[twoportshape,t=\MymyLabel{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch1) {};
\begin{scope}[xshift=5cm, yshift=0.65cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4, 0) to[short,-o](0.75, 0);
\draw (0.78, 0)-- +(30: 0.46);
@ -114,8 +148,8 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
\end{scope}
% I2C I/O expanders
\draw (4.6, 1.6) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c0) {};
\draw (4.6, -1.6) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c1) {};
\draw (4.6, 1.6) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c0) {};
\draw (4.6, -1.6) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c1) {};
% 2 Aesthetic EEPROMs
\draw (4.6, 2.2) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (eeprom0) {};
@ -296,9 +330,9 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
\begin{figure}[hbt!]
\centering
\includegraphics[angle=90, height=1.7in]{photo2245.jpg}
\includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
\caption{LVDS-TTL card and front panel}
\includegraphics[height=2.1in]{DIO_RJ45_FP.pdf}
\includegraphics[height=2.1in]{photo2245.jpg}
\caption{LVDS-TTL Card photo}
\end{figure}
@ -306,11 +340,9 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
% page-by-page.
\onecolumn
\sourcesection{2245 LVDS-TTL}{https://github.com/sinara-hw/DIO_LVDS_RJ45/wiki}
\section{Electrical Specifications}
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
Information in this section is based on the datasheet of the repeaters IC (FIN1101K8X\footnote{\label{repeaters}https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}).
\begin{table}[h]
\begin{threeparttable}
@ -331,7 +363,9 @@ All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherw
\end{tabularx}
\end{threeparttable}
\end{table}
The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
All specifications are in the recommended operating temperature range unless otherwise noted.
All typical values of DC specifications are at $T_A = 25\degree C$.
\begin{table}[h]
@ -342,7 +376,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
Output differentiual Voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
\cline{0-5}
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
\cline{0-5}
@ -352,35 +386,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
\hline
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
\hline
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
\begin{table}[h]
\begin{threeparttable}
\caption{AC Specifications}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
(20\% to 80\%) & & & & & \\
\cline{0-5}
Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
(80\% to 20\%) & & & & & \\
\cline{0-5}
Pulse width distortion & & 0.01 & 0.2 & ns & \\
\hline
LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
deterministic & & & & & 800 Mbps\\
\hline
LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
random (RMS) & & & & & \\
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended Input Voltage \\
\thickhline
\end{tabularx}
\end{threeparttable}
@ -388,18 +394,46 @@ All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 30
\newpage
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise specified.
\begin{table}[h]
\begin{threeparttable}
\caption{AC Specifications}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Differential Output Rise Time & \multirow{2}{*}{$t_{TLHD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & duty Cycle = 50\%.\\
(20\% to 80\%) & & & & & & \\
\cline{0-5}
Differential Output Fall Time & \multirow{2}{*}{$t_{THLD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
(80\% to 20\%) & & & & & & \\
\cline{0-5}
Pulse width distortion & $PWD$ & & 0.01 & 0.2 & ns & \\
\hline
LVDS data jitter, & \multirow{2}{*}{$t_{DJ}$} & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
deterministic & & & & & & 800 Mbps\\
\hline
LVDS clock jitter, & \multirow{2}{*}{$t_{RJ}$} & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
random (RMS) & & & & & & \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
\section{Configuring IO Direction \& Termination}
The IO direction can be configured by switches, which are found at the top of the card.
\begin{multicols}{2}
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
IO direction switches partly decides the IO direction of each bank.
\begin{itemize}
\itemsep0em
\item IO direction switch closed (\texttt{ON}) \\
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
\item IO direction switch open (OFF) \\
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
\item Closed switch (ON) \\
Fix the corresponding channel to output. The direction cannot be changed by I\textsuperscript{2}C.
\item Opened switch (OFF) \\
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
\end{itemize}
\vspace*{\fill}\columnbreak
\columnbreak
\begin{center}
\centering
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
@ -409,12 +443,15 @@ The IO direction of each channel can be configured by DIP switches, which are fo
\newpage
\codesection{2245 LVDS-TTL card}
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
\subsection{One pulse per second}
The channel should be configured as output in both gateware and hardware.
The channel should be configured as output in both the gateware and hardware.
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
\subsection{Morse code}
@ -423,7 +460,7 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
\newpage
\subsection{Counting rising edges in a 1ms window}
The channel should be configured as input in both gateware and hardware.
The channel should be configured as input in both the gateware and hardware.
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
@ -449,7 +486,8 @@ One channel needs to be configured as input, and the other as output.
\newpage
\subsection{SPI Master Device}
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
If a EEM port is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices.
Invocation of an SPI transfer follows this pattern:
\begin{enumerate}
% The config register can be set using set_config.
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
@ -482,7 +520,7 @@ The list of configurations supported in the gateware are listed as below:
\end{tabular}
\end{table}
The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves.
The following ARTIQ example demonstrates the flow of an SPI transcation with a typical SPI setup with 3 homogeneous slaves.
The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
\begin{center}
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
@ -561,16 +599,19 @@ The following examples will assume the SPI communication has the following prope
\item Most significant bit (MSB) first
\item Full duplex
\end{itemize}
The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
The base line configuration for an \texttt{SPIMaster} instance can be defined as such:
\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
\subsubsection{SPI frequency}
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor from [2, 257].
In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
\subsubsection{SPI write}
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves.
Suppose the instruction and data are 8 bits and 32 bits respectively.
The timing diagram of such write operation is shown in the following.
\begin{center}
\begin{tikztimingtable}
@ -591,11 +632,11 @@ Typically, an SPI write operation involves sending an instruction and data to th
\end{center}
\newpage
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transcation can be performed by the following code.
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
\subsubsection{SPI read}
A 32-bit read is represented by the following timing diagram:
A 32-bits read is represented by the following timing diagram.
\begin{center}
\begin{tikztimingtable}
@ -620,8 +661,14 @@ Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This S
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
\newpage
\ordersection{2245 LVDS-TTL}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2245 LVDS-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\finalfootnote
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

279
4410-4412.tex
View File

@ -1,5 +1,25 @@
\input{preamble.tex}
\graphicspath{{images/4410-4412}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfigure}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usepackage{pifont}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{4410/4412 DDS Urukul}
\author{M-Labs Limited}
@ -13,32 +33,46 @@
\section{Features}
\begin{itemize}
\item{4-channel 1GS/s DDS}
\item{Output frequency from \textless 1 to \textgreater 400 MHz}
\item{Sub-Hz frequency resolution}
\item{Controlled phase steps}
\item{Accurate output amplitude control}
\item{4-channel 1GS/s DDS.}
\item{Output frequency ranges from \textless 1 to \textgreater 400 MHz.}
\item{Sub-Hz frequency resolution.}
\item{Controlled phase steps.}
\item{Accurate output amplitude control.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Dynamic low-noise RF source}
\item{Driving RF electrodes in ion traps}
\item{Driving acousto-optic modulators}
\item{Form a laser intensity servo with 5108 Sampler}
\item{Dynamic low-noise RF source.}
\item{Driving RF electrodes in ion traps.}
\item{Driving acousto-optic modulators.}
\item{Form a laser intensity servo with 5108 Sampler.}
\end{itemize}
\section{General Description}
The 4410/4412 DDS Urukul card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 4410/4412 DDS Urukul card is a 4hp EEM module part of the ARTIQ Sinara family.
It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
It provides 4 channels of DDS (direct digital synthesis) at 1GS/s. Output frequencies from \textless 1 to \textgreater 400 MHz are supported. The nominal maximum output power of each channel is 10dBm. Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches (1ns temporal resolution) on each channel provide 70 dB isolation.
It provides 4 channels of DDS at 1GS/s.
Output frequency from \textless 1 to \textgreater 400 MHz are supported.
The nominal maximum output power of each channel is 10dBm.
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator.
RF switches (1ns temporal resolution) on each channel provides 70 dB isolation.
4410 DDS Urukul comes with AD9910 chips, while 4412 DDS Urukul comes with AD9912 chips instead.
4410 DDS Urukul features AD9910 chips, while 4412 DDS Urukul features AD9912 chips. AD9912 is capable of higher frequency precision (~8 \textmu Hz) than the AD9910 (~0.25 Hz). The ARTIQ SU-Servo configuration is only available for AD9910.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{0.88}{
@ -145,7 +179,7 @@ It provides 4 channels of DDS (direct digital synthesis) at 1GS/s. Output freque
\draw (3.8, -0.35) node[twoportshape, t={CPLD}, circuitikz/bipoles/twoport/width=1.1, scale=0.8, rotate=-90] (cpld) {};
% Synthronization clock buffer for DDS block
\draw (3.5, -2.5) node[twoportshape, t=\fourcm{Sync}{Buffer}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (sync_buf) {};
\draw (3.5, -2.5) node[twoportshape, t=\MymyLabel{Sync}{Buffer}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (sync_buf) {};
% Connect CPLD to:
% DDS clock buffer
@ -161,10 +195,10 @@ It provides 4 channels of DDS (direct digital synthesis) at 1GS/s. Output freque
\draw [-latexslim] (sync_buf.south) -- ++ (0, -0.3) -- ++ (-1.05, 0);
% LVDS Transceivers
\draw (6, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds0) {};
\draw (6, -0.7) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds1) {};
\draw (6, -2.5) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds2) {};
\draw (6, -3.2) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds3) {};
\draw (6, 0) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds0) {};
\draw (6, -0.7) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds1) {};
\draw (6, -2.5) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds2) {};
\draw (6, -3.2) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds3) {};
% Connect CPLD to transceivers
\draw [latexslim-latexslim] (lvds0.west) -- ++ (-1.13, 0);
@ -230,7 +264,7 @@ It provides 4 channels of DDS (direct digital synthesis) at 1GS/s. Output freque
\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
% Attenuators {0, 1, 2, 3} for amplifiers {0, 1, 2, 3}
\draw (4.6, 0) node[twoportshape, t=\fourcm{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
\draw (4.6, 0) node[twoportshape, t=\MymyLabel{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
% DDS {0, 1, 2, 3} for attenuators {0, 1, 2, 3}
\draw (6.6, 0) node[twoportshape, t={DDS}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (dds) {};
@ -271,23 +305,22 @@ It provides 4 channels of DDS (direct digital synthesis) at 1GS/s. Output freque
\centering
\includegraphics[height=2.2in]{Urukul_FP.jpg}
\includegraphics[height=2.2in]{photo4410.jpg}
\caption{Urukul card and front panel}
\caption{Urukul Card photo}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{4410/4412 DDS Urukul}{https://github.com/sinara-hw/Urukul/}
\section{Electrical Specifications}
Specifications of parameters are based on the datasheets of the DDS IC
(AD9910\footnote{\label{ad9910}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf}},
AD9912\footnote{\label{ad9912}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9912.pdf}}),
clock buffer IC (Si53312\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5331x_datasheet.pdf}}),
digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}), Sinara project information\footnote{\label{urukul_wiki}\url{https://github.com/sinara-hw/Urukul/wiki\#details-specification-and-typical-performance-data}}
and corresponding test results\footnote{\label{sinara354}\url{https://github.com/sinara-hw/sinara/issues/354\#issuecomment-352859041}}.
Specifications of parameters are based on the datasheets of the
DDS IC(AD9910\footnote{\label{ad9910}https://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf},
AD9912\footnote{\label{ad9912}https://www.analog.com/media/en/technical-documentation/data-sheets/AD9912.pdf}),
clock buffer IC (Si53312\footnote{\label{clock_buffer}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si53312.pdf}),
digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}),
various information from Sinara wiki\footnote{\label{urukul_wiki}https://github.com/sinara-hw/Urukul/wiki\#details-specification-and-typical-performance-data}
and corresponding test results\footnote{\label{sinara354}https://github.com/sinara-hw/sinara/issues/354\#issuecomment-352859041}.
\begin{table}[h]
\centering
\begin{threeparttable}
@ -328,9 +361,11 @@ and corresponding test results\footnote{\label{sinara354}\url{https://github.com
Resolution & & & & & \\
\hspace{3mm} Frequency\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{urukul_wiki} & & 0.25 & & Hz & AD9910 \\
& & 8 & & $\mu$Hz & AD9912 \\
\hspace{3mm} Phase offset\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 16/14 & & bits & AD9910/AD9912 respectively \\
\hspace{3mm} Phase offset\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 16 & & bits & AD9910 \\
& & 14 & & bits & AD9912 \\
\hspace{3mm} Digital amplitude\repeatfootnote{ad9910} & & 14 & & bits & AD9910 \\
\hspace{3mm} DAC full scale current\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 8/10 & & bits & AD9910/AD9912 respectively \\
\hspace{3mm} DAC full scale current\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 8 & & bits & AD9910 \\
& & 10 & & bits & AD9912 \\
\hspace{3mm} Temporal (I/O Update)\repeatfootnote{urukul_wiki} & & 4 & & ns & \\
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & & 0.5 & & dB & \\
\thickhline
@ -338,12 +373,14 @@ and corresponding test results\footnote{\label{sinara354}\url{https://github.com
\end{threeparttable}
\end{table}
The tabulated performance characteristics are produced using the following setup unless otherwise noted:
\newpage
The tabulated performance characteristics are produced using the following setup unless otherwise noted.
\begin{itemize}
\item 100 MHz input clock into SMA, 10 dBm
\item Input clock divided by 4
\item PLL with x40 multiplier
\item Output frequency at 80 MHz or 81 MHz
\item 100 MHz input clock into SMA, 10 dBm.
\item Input clock divided by 4.
\item PLL with x40 multiplier.
\item Output frequency at 80 MHz or 81 MHz.
\end{itemize}
\begin{table}[h]
@ -391,7 +428,7 @@ The tabulated performance characteristics are produced using the following setup
\newpage
Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\footnote{\label{urukul29}\url{https://github.com/sinara-hw/Urukul/issues/29}}. An external 125 MHz clock signal was supplied.
Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\footnote{\label{urukul29}https://github.com/sinara-hw/Urukul/issues/29}. An external 125 MHz clock signal were supplied.
\newcommand{\ts}{\textsuperscript}
\newcolumntype{Y}{>{\centering\arraybackslash}X}
@ -544,7 +581,9 @@ Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\foot
\newpage
The RMS voltage of a 4410 DDS Urukul channel at different amplitude scale factors is measured below. The DDS channel is directly connected to an oscilloscope with a 50\textOmega~termination. The reported values are obtained from the oscilloscope.
The RMS voltage of a 4410 DDS Urukul channel at different amplitude scale factor is measured.
The DDS channel is directly connected to an oscilloscope with a 50\textOmega~termination.
The reported values are obtained from the oscilloscope.
\begin{multicols}{2}
\begin{figure}[H]
@ -693,7 +732,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
color=blue,
mark=square,
samples=11,
y filter/.expression={y/0.089807 * 0.1}
y filter/.code={\pgfmathparse{\pgfmathresult/0.089807*0.1}\pgfmathresult}
] coordinates {
(0.0, 0) (0.1, 0.089807) (0.2, 0.179723) (0.3, 0.268852) (0.4, 0.354310) (0.5, 0.441055)
(0.6, 0.526386) (0.7, 0.61233) (0.8, 0.69044) (0.9, 0.75856) (1.0, 0.81703)
@ -703,7 +742,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
color=orange,
mark=square,
samples=11,
y filter/.expression={y/50.0729 * 0.1}
y filter/.code={\pgfmathparse{\pgfmathresult/50.0729*0.1}\pgfmathresult}
] coordinates {
(0, 0) (0.1, 50.0729) (0.2, 100.309) (0.3, 150.996) (0.4, 200.905) (0.5, 250.004)
(0.6, 297.000) (0.7, 345.980) (0.8, 394.391) (0.9, 442.869) (1.0, 490.651)
@ -713,7 +752,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
color=green,
mark=square,
samples=11,
y filter/.expression={y/28.4696 * 0.1}
y filter/.code={\pgfmathparse{\pgfmathresult/28.4696*0.1}\pgfmathresult}
] coordinates {
(0, 0) (0.1, 28.4696) (0.2, 57.143) (0.3, 85.776) (0.4, 114.694) (0.5, 143.302)
(0.6, 171.911) (0.7, 200.098) (0.8, 227.816) (0.9, 256.321) (1.0, 281.930)
@ -723,7 +762,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
color=red,
mark=square,
samples=11,
y filter/.expression={y/16.6691 * 0.1}
y filter/.code={\pgfmathparse{\pgfmathresult/16.6691*0.1}\pgfmathresult}
] coordinates {
(0, 0) (0.1, 16.6691) (0.2, 33.3762) (0.3, 49.8844) (0.4, 67.055) (0.5, 83.652)
(0.6, 99.970) (0.7, 116.906) (0.8, 133.368) (0.9, 150.839) (1.0, 167.033)
@ -776,7 +815,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
\end{multicols}
\footnotetext{\label{urukul64}\url{https://github.com/sinara-hw/Urukul/issues/64}}
\footnotetext{\label{urukul64}https://github.com/sinara-hw/Urukul/issues/64}
\begin{figure}[H]
\centering
@ -797,8 +836,61 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
\end{figure}
\newpage
\section{Configuring Operation Mode}
Mode of operation is specified by a DIP switch. The DIP switch can be found at the top right corner of the card. The following table summarizes the required setting for each mode.
\section{Front Panel Drawings}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=3in]{dds_drawings.pdf}
\captionof{figure}{4410 DDS Urukul front panel drawings}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90498177 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=3in]{dds_assembly.pdf}
\captionof{figure}{4410 DDS Urukul front panel assembly}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90498177 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
6 & 3040012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
7 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
8 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
9 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\newpage
\section{Urukul Mode Configurations}
Mode of operation is specified by a DIP switch.
The DIP switch can be found at the top right corner of the card.
The following table summarizes the required setting for each mode.
\ding{51} indicates ON, while \ding{53} indicates OFF.
\begin{multicols}{2}
@ -824,37 +916,47 @@ Mode of operation is specified by a DIP switch. The DIP switch can be found at t
\end{multicols}
\section{Urukul Single-/Double-EEM Modes}
4410/4412 DDS Urukul cards can operate with either a single or double EEM connections. When only EEM0 is connected, the card will act in single-EEM mode; when both EEM0 and EEM1 are connected, the card will act in double-EEM mode. 2-EEM mode when both EEM0 \& EEM1 are connected. Double-EEM mode provides these additional features in comparison to single-EEM mode:
\section{Urukul 1-EEM/2-EEM Modes}
4410/4412 DDS Urukul can operate with either 1 or 2 EEM connections.
It is in 1-EEM mode when only EEM0 is connected, 2-EEM mode when both EEM0 \& EEM1 are connected.
2-EEM mode provides these additional features in comparison to 1-EEM mode.
\begin{itemize}
\item \textbf{1 ns temporal resolution RF switches} \\
Without EEM1, the only way to access the switches is through the CPLD, using SPI. \\
With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver. 1 ns temporal resolution can then be achieved using the ARTIQ RTIO system.
\item 1 ns temporal resolution RF switches \\
Without EEM1, the only way to access the switches is through the CPLD using SPI. \\
With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver.
1 ns temporal resolution is achieved using the ARTIQ RTIO system.
\item \textbf{SU-Servo (4410 DDS Urukul feature)} \\
SU-Servo requires both EEM0 \& EEM1 to allow the control of multiple DDS channels simultaneously using the QSPI interface.
\item SU-Servo (4410 DDS Urukul feature) \\
SU-Servo requires both EEM0 \& EEM1 to control multiple DDS channels simultaneously using the QSPI interface.
\end{itemize}
\newpage
\codesection{4410/4412 DDS Urukul}
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 4410/4412 DDS Urukul card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\subsection{10 MHz sinusoidal wave}
Generates a 10MHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB. Both the CPLD and the DDS channels should be initialized. By default, AD9910 single-tone profiles are programmed to profile 7.
\subsection{10 MHz Sinusoidal Wave}
Generate a 10MHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB.
Both the CPLD and the DDS channels should be initialized.
By default, AD9910 single-tone profiles are programmed to profile 7.
\inputcolorboxminted{firstline=11,lastline=18}{examples/dds.py}
If the synchronization feature of AD9910 is enabled, RF signal across different channels of the same Urukul can be synchronized. For example, phase-coherent RF signal can be produced on both channel 0 and channel 1 after configuring an appropriate phase mode.
If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized.
For example, phase-coherent RF signal can be produced on both channel 0 and channel 1 after configuring an appropriate phase mode.
\inputcolorboxminted{firstline=28,lastline=43}{examples/dds.py}
Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant. It can be negated by adjusting the \texttt{phase} parameter.
Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant.
It can be negated by adjusting the \texttt{phase} parameter.
\newpage
\subsection{Periodic RF pulse (AD9910 Only)}
This example demonstrates that the RF signal can be modulated by amplitude using the RAM modulation feature of the AD9910. By default, RAM profiles are programmed to profile 0.
This examples demonstrates that the RF signal can be modulated by amplitude using the RAM modulation feature of AD9910.
By default, RAM profiles are programmed to profile 0.
\inputcolorboxminted{firstline=53,lastline=91}{examples/dds.py}
@ -866,7 +968,8 @@ The generated RF output of the above example consists of the following features
\item No signal for 3 microseconds.
\item Go back to item 1.
\end{enumerate}
The expected waveform is plotted on the following figure. Note that phase of the RF pulses may drift gradually.
The expected waveform is plotted on the following figure.
Note that phase of the RF pulses may drift gradually.
Urukul was operated with a 50$\Omega$ termination to produce the waveform.
\begin{tikzpicture}[
@ -874,7 +977,7 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
func(\x)= (\x<0) * (0) +
and(\x>=0, \x<2) * (0.42*cos(deg(10*pi*\x))) +
and(\x>=2, \x<3) * (0) +
and(\x>=3, \x<4) * (0.42*cos(deg(10*pi*\x))) +
and(\x>=3, \x<4) * (0.42*cos(deg(10*pi*\x)))) +
and(\x>=4, \x<7) * (0) +
and(\x>=7, \x<7.5) * (0.42*cos(deg(10*pi*\x)));
}
@ -899,12 +1002,15 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
\end{axis}
\end{tikzpicture}
\subsection{Simple amplitude ramp (AD9910 only)}
\subsection{Simple Amplitude Ramp (AD9910 Only)}
An amplitude ramp of an RF signal can be generated by modifying the \texttt{self.amp} array in the previous example.
\inputcolorboxminted{firstline=95,lastline=98}{examples/dds.py}
The generated RF output has an incrementing amplitude scale factor (ASF), increasing by 0.1 at every microsecond. Once the ASF reaches 1.0, it drops back to 0.0 at the next microsecond. The expected waveform over 1 cycle is plotted on the following figure. Note that phase of the RF pulses may drift gradually.
The generated RF output has an incrementing amplitude scale factor (ASF), increasing by 0.1 at every microsecond.
Once the ASF reaches 1.0, it drops back to 0.0 at the next microsecond.
The expected waveform over 1 cycle is plotted on the following figure.
Note that phase of the RF pulses may drift gradually.
Urukul was operated with a 50$\Omega$ termination to produce the waveform.
\begin{tikzpicture}[
@ -946,23 +1052,26 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
\newpage
\subsection{RAM synchronization (AD9910 only)}
Multiple RAM channels can also be synchronized. Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}. For example, set phase to 0 for the channels (\texttt{phase=0.0}):
\subsection{RAM Synchronization (AD9910 Only)}
Multiple RAM channels can also be synchronized.
Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}.
For example, set phase to 0 for the channels (\texttt{phase=0.0}).
\inputcolorboxminted{firstline=116,lastline=116}{examples/dds.py}
Then, replace the \texttt{run()} function with the following:
Then, replace the \texttt{run()} function with the following.
\inputcolorboxminted{firstline=122,lastline=134}{examples/dds.py}
Two phase-coherent RF signal with the same waveform as the previous figure (from either RAM examples) should be generated.
\subsection{Voltage-controlled DDS amplitude (SU-Servo only)}
The SU-Servo feature can be enabled by integrating the 4410 DDS Urukul with a 5108 Sampler. Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function:
\subsection{Voltage-controlled DDS Amplitude (SU-Servo Only)}
The SU-Servo feature can be enabled by integrating the 4410 DDS Urukul with a 5108 Sampler.
Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function.
\[H(s)=k_p+\frac{k_i}{s+\frac{k_i}{g}}\]
In the following example, the amplitude of DDS is proportional to the ADC input from Sampler. First, initialize the RTIO, SU-Servo and its channel. Note that the programmable gain of the Sampler is $10^0=1$ and the input range is [-10V, 10V].
In the following example, the amplitude of DDS is proportional to the ADC input from Sampler.
First, initialize the RTIO, SU-Servo and its channel.
Note that the programmable gain of the Sampler is $10^0=1$, the input range is [-10V, 10V].
\inputcolorboxminted{firstline=10,lastline=17}{examples/suservo.py}
@ -975,13 +1084,17 @@ When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
\inputcolorboxminted{firstline=26,lastline=30}{examples/suservo.py}
SU-Servo encodes the ADC voltage in a linear scale [-1, 1]. Therefore, 3V is converted to 0.3. Note that the ASF of all DDS channels are capped at 1.0 and the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
SU-Servo encodes the ADC voltage in a linear scale [-1, 1].
Therefore, 3V is converted to 0.3.
Note that the ASF of all DDS channels are capped at 1.0, the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
Finally, enable the SU-Servo channel with the IIR filter programmed beforehand:
Finally, enable the SU-Servo channel with the IIR filter programmed beforehand.
\inputcolorboxminted{firstline=32,lastline=33}{examples/suservo.py}
A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC. The RMS voltage of the DDS channel against the ADC voltage is plotted. The DDS channel is terminated with 50\textOmega.
A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC.
The RMS voltage of the DDS channel against the ADC voltage is plotted.
The DDS channel is terminated with 50\textOmega.
\begin{center}
\begin{tikzpicture}[
@ -1014,10 +1127,22 @@ A 10 MHz DDS signal is generated from the example above, with amplitude controll
\end{tikzpicture}
\end{center}
DDS signal should be attenuated. High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power. 15 dB attenuation at the digital attenuator was applied in this example.
DDS signal should be attenuated.
High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power.
15 dB attenuation at the digital attenuator was applied in this example.
\ordersection{4410/4412 DDS Urukul}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 4410 DDS Urukul in the ARTIQ Sinara crate configuration tool.
The default chip is AD9910 (4410 DDS Urukul), which supports more features.
If you need the higher frequency resolution of the AD9912 (4412 DDS Urukul), leave us a note when placing the order.
To enable SU-Servo feature between 4410 Urukul and 5108 Sampler, specify that SU-Servo is to be integrated into the gateware when placing the order.
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\finalfootnote
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

131
4456.tex
View File

@ -1,5 +1,25 @@
\input{preamble.tex}
\graphicspath{{images/4456}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfigure}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usepackage{pifont}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{4456 Synthesizer Mirny}
\author{M-Labs Limited}
@ -13,33 +33,45 @@
\section{Features}
\begin{itemize}
\item{4-channel VCO/PLL}
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz}
\item{Up to 13.6 GHz with Almazny mezzanine}
\item{Higher frequency resolution than Urukul}
\item{Lower jitter and phase noise}
\item{Large frequency changes take several milliseconds}
\item{4-channel VCO/PLL.}
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz.}
\item{Up to 13.6 GHz with Almazny mezzanine.}
\item{Higher frequency resolution than Urukul.}
\item{Lower jitter and phase noise.}
\item{Large frequency changes take several milliseconds.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Low-noise microwave source}
\item{Quantum state control}
\item{Driving acousto/electro-optic modulators}
\item{Low-noise microwave source.}
\item{Quantum state control.}
\item{Driving acousto/electro-optic modulators.}
\end{itemize}
\section{General Description}
The 4456 Synthesizer Mirny card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 4456 Synthesizer Mirny card is a 4hp EEM module part of the ARTIQ Sinara family.
It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
It provides 4 channels of PLL frequency synthesis. Output frequencies from 53 MHz to \textgreater 4 GHz are supported.The range can be expanded up to 13.6 GHz with the Almazny mezzanine (4467 HF Synthesizer).
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provides at least 50 dB isolation.
It provides 4 channels of PLL frequency synthesis.
Output frequency from 53 MHz to \textgreater 4 GHz are supported.
The range can be expanded up to 13.6 GHz with Almazny mezzanine.
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator.
RF switches on each channel provides at least 50 dB isolation.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{0.95}{
@ -196,8 +228,8 @@ Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF sw
\draw [latexslim-latexslim] (cpld.east) -- (afe.west);
% Draw LVDS transceivers, EEM
\draw (6.2, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
\draw (6.2, -1.6) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
\draw (6.2, 0) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
\draw (6.2, -1.6) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
\draw (7.8, -1.5) node[twoportshape, t={EEM Port}, circuitikz/bipoles/twoport/width=3.8, scale=0.7, rotate=-90] (eem) {};
% Connect LVDS transceiver to CPLD
@ -236,7 +268,7 @@ Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF sw
\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
% Attenuators {0, 1, 2, 3} for amplifiers {0, 1, 2, 3}
\draw (4.6, 0) node[twoportshape, t=\fourcm{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
\draw (4.6, 0) node[twoportshape, t=\MymyLabel{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
% PLL {0, 1, 2, 3} for attenuators {0, 1, 2, 3}
\draw (6.6, 0) node[twoportshape, t={PLL}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (pll) {};
@ -275,24 +307,22 @@ Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF sw
\begin{figure}[hbt!]
\centering
\includegraphics[height=2in]{Mirny_FP.pdf}
\includegraphics[height=2in]{photo4456.jpg}
\includegraphics[height=3in, angle=90]{Mirny_FP.pdf}
\caption{Mirny card and front panel}
\caption{Mirny Card photo}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{4456 Synthesizer Mirny}{https://github.com/sinara-hw/mirny}
\section{Electrical Specifications}
Specifications of parameters are based on the datasheets of the PLL IC
(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
Specifications of parameters are based on the datasheets of the
PLL IC(ADF5356\footnote{\label{adf5356}https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}),
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}),
digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}).
Test results are from the Krzysztof Belewicz's thesis ``Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}.
\begin{table}[h]
\centering
@ -341,12 +371,16 @@ Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for dr
\newpage
Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}.
The SPI signal is driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card.
Mirny is then connected to the RSA5100A spectrum analyzer for measurement.
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny.
Note that the common-mode choke is not present on the Mirny card.
The following is a comparison between 2 setups at 1 GHz output:
\begin{itemize}
\item Red: Before any modifications
\item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
\item Blue: Adding a CM choke with an 100 \textmu F capacitor after the CM choke
\end{itemize}
\begin{figure}[H]
@ -355,7 +389,7 @@ Noise response spike can be improved by inserting an additional common-mode chok
\caption{Phase noise measurement at 1 GHz}
\end{figure}
Phase noise at different output frequencies is then measured:
Phase noise at different output frequencies are then measured.
\newcolumntype{Y}{>{\centering\arraybackslash}X}
@ -391,15 +425,22 @@ Phase noise at different output frequencies is then measured:
\caption{Phase noise measurement}
\end{figure}
\codesection{4456 Synthesizer Mirny}
\newpage
\subsection{1 GHz sinusoidal wave}
Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 4456 Synthesizer Mirny card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\subsection{1 GHz Sinusoidal Wave}
Generate a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB.
Both the CPLD and the PLL channels should be initialized.
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
\subsection{ADF5356 power control}
Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
\subsection{ADF5356 Power Control}
Output power can be controlled be configuring the PLL channels individually, in addition to the digital attenuators.
After initialization of the PLL channel (ADF5356), the following line of code can change the output power level.
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
@ -417,17 +458,27 @@ The parameter corresponds to a specific change of output power according to the
\end{tabular}
\end{center}
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the folowing line.
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
\newpage
\subsection{Periodic 100\textmu s pulses}
The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
The output can be toggled on and off periodically using the RF switches.
The following code emits a 100\textmu s pulse in every millisecond.
A microwave signal should be programmed in prior (such as the 1 GHz wave example).
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
\ordersection{4456 Synthesizer Mirny}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 4456 Synthesizer Mirny in the ARTIQ Sinara crate configuration tool.
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\finalfootnote
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

58
5108.tex
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@ -1,5 +1,24 @@
\include{preamble.tex}
\graphicspath{{images/5108}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfigure}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{5108 ADC Sampler}
\author{M-Labs Limited}
@ -45,6 +64,15 @@ However, the sample rate in practice is typically limited by the use of ARTIQ-Py
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{1}{
@ -130,7 +158,7 @@ However, the sample rate in practice is typically limited by the use of ARTIQ-Py
\end{scope}
% Draw termination switches
\draw (1.0, 1.925) node[twoportshape,t=\fourcm{100k/50\textOmega}{Switch \phantom{s} x8}, circuitikz/bipoles/twoport/width=1.5, scale=0.5] (termswitch) {};
\draw (1.0, 1.925) node[twoportshape,t=\MymyLabel{100k/50\textOmega}{Switch \phantom{s} x8}, circuitikz/bipoles/twoport/width=1.5, scale=0.5] (termswitch) {};
\begin{scope}[xshift=1.2cm, yshift=1.925cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
@ -142,14 +170,14 @@ However, the sample rate in practice is typically limited by the use of ARTIQ-Py
% Draw PGIAs
% The connections are too complicated for the usual buffer/op-amp symbol
\draw (3, 2.45) node[twoportshape,t=\fourcm{CH 0}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia0) {};
\draw (3, 1.75) node[twoportshape,t=\fourcm{CH 1}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia1) {};
\draw (3, 1.05) node[twoportshape,t=\fourcm{CH 2}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia2) {};
\draw (3, 0.35) node[twoportshape,t=\fourcm{CH 3}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia3) {};
\draw (3, -0.35) node[twoportshape,t=\fourcm{CH 4}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia4) {};
\draw (3, -1.05) node[twoportshape,t=\fourcm{CH 5}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia5) {};
\draw (3, -1.75) node[twoportshape,t=\fourcm{CH 6}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia6) {};
\draw (3, -2.45) node[twoportshape,t=\fourcm{CH 7}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia7) {};
\draw (3, 2.45) node[twoportshape,t=\MymyLabel{CH 0}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia0) {};
\draw (3, 1.75) node[twoportshape,t=\MymyLabel{CH 1}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia1) {};
\draw (3, 1.05) node[twoportshape,t=\MymyLabel{CH 2}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia2) {};
\draw (3, 0.35) node[twoportshape,t=\MymyLabel{CH 3}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia3) {};
\draw (3, -0.35) node[twoportshape,t=\MymyLabel{CH 4}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia4) {};
\draw (3, -1.05) node[twoportshape,t=\MymyLabel{CH 5}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia5) {};
\draw (3, -1.75) node[twoportshape,t=\MymyLabel{CH 6}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia6) {};
\draw (3, -2.45) node[twoportshape,t=\MymyLabel{CH 7}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia7) {};
% Draw termination connection to input lines
\draw [-] (0.65, 1.675) -- (0.65, 1.225);
@ -182,7 +210,7 @@ However, the sample rate in practice is typically limited by the use of ARTIQ-Py
\draw [-latexslim] (bnc7.east) -- (1.9, -1.225) -- (1.9, -2.45) -- (pgia7.west);
% Draw shift register & ADC
\draw (4.7, 1) node[twoportshape,t=\fourcm{Shift}{Registers}, circuitikz/bipoles/twoport/width=1.6, scale=0.6, rotate=-90] (sr) {};
\draw (4.7, 1) node[twoportshape,t=\MymyLabel{Shift}{Registers}, circuitikz/bipoles/twoport/width=1.6, scale=0.6, rotate=-90] (sr) {};
\draw (4.7, -1) node[twoportshape,t={ADC}, circuitikz/bipoles/twoport/width=1.6, scale=0.6, rotate=-90] (adc) {};
% Connect PGIA -> ADC paths
@ -206,7 +234,7 @@ However, the sample rate in practice is typically limited by the use of ARTIQ-Py
\draw [latexslim-] (3.45, -1.85) -- ++ (0.35, 0);
% Draw LVDS transceivers & repeaters
\draw (6.3, 1) node[twoportshape,t=\fourcm{LVDS}{Transceivers}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (lvds) {};
\draw (6.3, 1) node[twoportshape,t=\MymyLabel{LVDS}{Transceivers}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (lvds) {};
\draw (6.3, -1) node[twoportshape,t={Repeaters}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (rep) {};
% ADC & SR connection lines
@ -676,6 +704,8 @@ To order, please visit \url{https://m-labs.hk} and select the 5108 ADC Sampler i
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

182
5432.tex
View File

@ -1,5 +1,24 @@
\input{preamble.tex}
\graphicspath{{images/5432}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfig}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{5432 DAC Zotino}
\author{M-Labs Limited}
@ -13,30 +32,43 @@
\section{Features}
\begin{itemize}
\item{32-channel DAC}
\item{16-bits resolution}
\item{1 MSPS shared between all channels}
\item{Output voltage $\pm$10V}
\item{HD68 connector}
\item{Can be broken out to BNC/SMA/MCX}
\item{32-channel DAC.}
\item{16-bits resolution.}
\item{1 MSPS shared between all channels.}
\item{Output voltage $\pm$10V.}
\item{HD68 connector.}
\item{Can be broken out to BNC/SMA/MCX.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Controlling setpoints of PID controllers for laser power stabilization}
\item{Low-frequency arbitrary waveform generation}
\item{Driving DC electrodes in ion traps}
\item{Controlling setpoints of PID controllers for laser power stabilization.}
\item{Low-frequency arbitrary waveform generation.}
\item{Driving DC electrodes in ion traps.}
\end{itemize}
\section{General Description}
The 5432 Zotino is a 4hp EEM module and part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 5432 Zotino is a 4hp EEM module part of the ARTIQ Sinara family.
It adds digital-analog converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
It provides 4 groups of 8 analog channels each, exposed by 1 HD68 connector.
Each channel supports output voltage from -10 V to 10 V.
All channels can be updated simultaneously.
Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{0.88}{
@ -46,20 +78,20 @@ It provides four groups of eight analog channels each, exposed by one HD68 conne
\draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
% IDC Connectors to IDC cards
\draw (2.2, 1.2) node[twoportshape, t={\twocm{IDC}{DAC 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) {};
\draw (1.4, 1.2) node[twoportshape, t={\twocm{IDC}{DAC 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) {};
\draw (2.2, -1.2) node[twoportshape, t={\twocm{IDC}{DAC 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) {};
\draw (1.4, -1.2) node[twoportshape, t={\twocm{IDC}{DAC 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) {};
\draw (2.2, 1.2) node[twoportshape, t={\MyLabel{IDC}{DAC 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) {};
\draw (1.4, 1.2) node[twoportshape, t={\MyLabel{IDC}{DAC 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) {};
\draw (2.2, -1.2) node[twoportshape, t={\MyLabel{IDC}{DAC 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) {};
\draw (1.4, -1.2) node[twoportshape, t={\MyLabel{IDC}{DAC 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) {};
% Op-amp x32
\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
% DAC AD5372
\draw (4.6, 0.2) node[twoportshape, t=\twocm{32-CH}{DAC}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (dac) {};
\draw (4.6, 0.2) node[twoportshape, t=\MyLabel{32-CH}{DAC}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (dac) {};
% LVDS Transceivers
\draw (6.6, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
\draw (6.6, -1.6) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
\draw (6.6, 0) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
\draw (6.6, -1.6) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
% Aesthetic EEPROM
\draw (6.6, 1.6) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eeprom) {};
@ -90,10 +122,10 @@ It provides four groups of eight analog channels each, exposed by one HD68 conne
% TEC Cooler on top of the DAC
% To make it more obvious that it is cooling the DAC
\draw (4.6, 1.45) node[twoportshape, t=\fourcm{TEC}{Cooler}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (tec_cooler) {};
\draw (4.6, 1.45) node[twoportshape, t=\MymyLabel{TEC}{Cooler}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (tec_cooler) {};
% TEC Controller lined up with EEM IN
\draw (8.2, 3.5) node[twoportshape, t=\fourcm{TEC Controller}{Connector}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (tec_conn) {};
\draw (8.2, 3.5) node[twoportshape, t=\MymyLabel{TEC Controller}{Connector}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (tec_conn) {};
% Thermistor for TEC controller
\draw (6.6, 3.3) node[thermistorshape, scale=0.7, rotate=-90] (thermistor) {};
@ -111,33 +143,24 @@ It provides four groups of eight analog channels each, exposed by one HD68 conne
\caption{Simplified Block Diagram}
\end{figure}
\begin{figure}[hbt!]
\begin{figure}[h]
\centering
\includegraphics[height=2in]{Zotino_FP.jpg}
\includegraphics[height=2in]{photo5432.jpg}
\caption{Zotino card photograph}
\end{figure}
\begin{figure}[hbt!]
\centering
\includegraphics[height=2.3in, angle=90]{Zotino_FP.jpg}
\caption{Zotino front panel}
\caption{Zotino Card photo}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{5432 DAC Zotino}{https://github.com/sinara-hw/Zotino/}
\section{Electrical Specifications}
% \hypersetup{hidelinks}
% \urlstyle{same}
These specifications are based on the datasheet of the DAC IC
(AD5372BCPZ\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}}),
and various information from the Sinara wiki\footnote{\label{zotino_wiki}\url{https://github.com/sinara-hw/Zotino/wiki}}.
The specifications are based on the datasheet of the DAC IC
(AD5372BCPZ\footnote{\label{dac}https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}),
and various information from Sinara wiki\footnote{\label{zotino_wiki}https://github.com/sinara-hw/Zotino/wiki}.
\begin{table}[h]
\centering
@ -162,7 +185,9 @@ and various information from the Sinara wiki\footnote{\label{zotino_wiki}\url{ht
\end{threeparttable}
\end{table}
The following table records the cross-talk and transient behavior of Zotino\footnote{\label{zotino21}\url{https://github.com/sinara-hw/Zotino/issues/21}}. In terms of output noise, measurements were made after a 15-cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF\footnote{\label{zotino27}\url{https://github.com/sinara-hw/Zotino/issues/27}}. DAC output during noise measurement was 3.5 V.
The following are cross-talk and transient behavior of Zotino\footnote{\label{zotino21}https://github.com/sinara-hw/Zotino/issues/21}.
In terms of output noise, it was measured after 15 cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF\footnote{\label{zotino27}https://github.com/sinara-hw/Zotino/issues/27}.
The DAC output during noise measurement is 3.5 V.
\begin{table}[h]
\centering
@ -197,7 +222,7 @@ The following table records the cross-talk and transient behavior of Zotino\foot
\newpage
Step response was found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observing the waveform\repeatfootnote{zotino21}.
Step response are found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observe the waveform\repeatfootnote{zotino21}.
\begin{figure}[hbt!]
\centering
@ -210,12 +235,12 @@ Step response was found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (
\caption{Step response}%
\end{figure}
Far-end crosstalk was measured using the following setup\repeatfootnote{zotino21}:
Far-end crosstalk is measured using the following setup\repeatfootnote{zotino21}.
\begin{enumerate}
\item CH1 as aggressor, CH0 as victim
\item CH0, 2-7 terminated, CH 8-31 open
\item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables and connectors.
\item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables \& connectors.
\end{enumerate}
\begin{figure}[hbt!]
@ -226,24 +251,85 @@ Far-end crosstalk was measured using the following setup\repeatfootnote{zotino21
\newpage
\codesection{5432 DAC Zotino}
\section{Front Panel Drawings}
\begin{multicols}{2}
\subsection{Setting output voltage}
The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channels 0, 1, 2, and 3 respectively. Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
\begin{center}
\centering
\includegraphics[height=3in]{zotino_drawings.pdf}
\captionof{figure}{5432 DAC Zotino front panel drawings}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90503572 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=3in]{zotino_assembly.pdf}
\captionof{figure}{5432 DAC Zotino front panel assembly}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90503572 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
6 & 3040012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
7 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\newpage
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 5432 DAC Zotino card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\subsection{Set output voltage}
The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channel 0, 1, 2, 3 respectively.
Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
\inputcolorboxminted{firstline=11,lastline=22}{examples/zotino.py}
\newpage
\subsection{Triangular wave}
Generates a triangular waveform at 10 Hz, 16 V peak-to-peak. Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
\subsection{Triangular Wave}
A triangular waveform at 10 Hz, 16 V peak-to-peak.
Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.
\inputcolorboxminted{firstline=30,lastline=49}{examples/zotino.py}
\ordersection{5432 DAC Zotino}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 5432 DAC Zotino in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\finalfootnote
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

194
5518-5528.tex
View File

@ -1,5 +1,25 @@
\input{preamble.tex}
\graphicspath{{images/5518-5528}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfig}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usepackage{pifont}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{5518 BNC-IDC / 5528 SMA-IDC}
\author{M-Labs Limited}
@ -13,31 +33,44 @@
\section{Features}
\begin{itemize}
\item{8 channels}
\item{Internal IDC connector}
\item{External BNC or SMA connectors}
\item{8 channels.}
\item{Internal IDC connector.}
\item{External BNC or SMA connectors.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Break out analog signals}
\item{Breaks out analog signals.}
\item{BNC or SMA adapters for: \begin{itemize}
\item{5432 DAC Zotino}
\item{5632 DAC Fastino}
\end{itemize}}
\item{(5528 only) SMA adapter for 5108 Sampler}
\item{Convert from/to HD68 with 5568 HD68-IDC}
\item{(5528 only) SMA adapter for 5108 Sampler.}
\item{Convert from/to HD68 with 5568 HD68-IDC.}
\end{itemize}
\section{General Description}
The 5518 BNC-IDC card is a 8hp EEM module; the 5528 SMA-IDC card is a 4hp EEM module. Both adapter cards break out analog signals from IDC connectors to BNC (5518) or SMA (5528). IDC connectors can be found on 5108 Sampler, 5432 DAC Zotino, 5632 DAC Fastino and 5568 HD68-IDC.
The 5518 BNC-IDC card is a 8hp EEM module, while the 5528 SMA-IDC card is a 4hp EEM module.
Both adapter cards break out analog signal from IDC connectors to BNC (5518) or SMA (5528).
IDC connectors can be found on 5108 Sampler, 5432 DAC Zotino, 5632 DAC Fastino \& 5568 HD68-IDC.
Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking out all 32 channels of 5432 DAC Zotino, 5632 DAC Fastino or 5568 HD68-IDC requires four BNC/SMA-IDC cards. Breaking out all 8 ADC channels of 5108 Sampler requires only one BNC/SMA-IDC card.
Each card provides 8 channels, with BNC (5518) or SMA (5528) connectors.
Breaking out all 32 channels from 5432 DAC Zotino, 5632 DAC Fastino or 5568 HD68-IDC requires 4 BNC/SMA-IDC cards.
Only 1 BNC/SMA-IDC is required to break out all 8 ADC channels from a 5108 Sampler.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{0.95}{
@ -124,9 +157,9 @@ Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking
\end{scope}
% Draw CH0, CH1 & CH7 CM chokes
\draw (3, 1.2) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm0) {};
\draw (3, 0.4) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm1) {};
\draw (3, -1.1) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm7) {};
\draw (3, 1.2) node[twoportshape, t=\MymyLabel{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm0) {};
\draw (3, 0.4) node[twoportshape, t=\MymyLabel{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm1) {};
\draw (3, -1.1) node[twoportshape, t=\MymyLabel{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm7) {};
% Omission dots for other channels
\node at (3, -0.15)[circle,fill,inner sep=0.7pt]{};
@ -167,12 +200,15 @@ Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking
\begin{figure}[hbt!]
\centering
\subfloat[\centering BNC-IDC]{{
\includegraphics[height=2.5in]{BNC_IDC_FP.jpg}
\includegraphics[height=2.5in]{photo5518.jpg}
}}%
\subfloat[\centering SMA-IDC]{{
\includegraphics[height=2.6in]{photo5528.jpg}
\quad
\includegraphics[height=2.5in]{SMA_IDC_FP.pdf}
\quad
}}%
\caption{BNC-IDC/SMA-IDC card photos}%
\caption{BNC-IDC/SMA-IDC Card photos}%
\label{fig:example}%
\end{figure}
@ -180,41 +216,39 @@ Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking
% page-by-page.
\onecolumn
\sourcesectiond{5518 BNC-IDC}{5528 SMA-IDC}{https://github.com/sinara-hw/BNC\_IDC}{https://github.com/sinara-hw/SMA\_IDC\_Adapter}
\section{Electrical Specifications}
Specifications of parameters are based on the datasheet of the
common mode line filter\footnote{\label{cm_choke}\url{https://www.we-online.com/catalog/datasheet/744229.pdf}}.
common mode line filter\footnote{\label{cm_choke}https://www.we-online.com/catalog/datasheet/744229.pdf}.
\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Electrical Specifications}
\begin{tabularx}{0.65\textwidth}{l | c | c | X}
\begin{tabularx}{0.65\textwidth}{l | c | c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Max. Value} & \textbf{Unit} & \textbf{Conditions} \\
\textbf{Parameter} & \textbf{Symbol} & \textbf{Max. Value} & \textbf{Unit} & \textbf{Conditions} \\
\hline
Rated voltage & 80 & V & \\
Rated voltage & $V_{R}$ & 80 & V & \\
\hline
Rated current & 400 & mA & $\Delta T^{*}=40K$ \\
Rated current & $I_{R}$ & 400 & mA & $\Delta T^{*}=40K$ \\
\thickhline
\end{tabularx}
*$\Delta T$ refers to the temperature of the CM line filter minus the ambient.
\end{threeparttable}
\end{table}
Impedance characteristics of common mode \& differential mode signal at different frequencies are shown in the following graph:
Impedance characteristics of common mode \& differential mode signal at different frequencies are shown in the following graph.
\begin{figure}[H]
\centering
\includegraphics[height=4.8in]{idc_cm_choke.jpg}
\includegraphics[]{idc_cm_choke.pdf}
\caption{Common Mode Line Filter Impedance Characteristics}
\end{figure}
\newpage
\section{Channel Mapping}
The following table shows the corresponding channel numbers of the BNC/SMA-IDC adapter IO ports when connected to Sinara cards that support IDC connections.
The following table shows the corresponding channel number of the BNC/SMA-IDC adapter IO ports, when it is connected to Sinara cards that support IDC connections.
\begin{table}[h]
\caption{Channel Mapping of BNC/SMA-IDC to Zotino, Fastino \& HD68-IDC}
\centering
@ -233,14 +267,118 @@ The following table shows the corresponding channel numbers of the BNC/SMA-IDC a
\centering
\begin{tabular}{|l|l|l|l|l|l|l|l|l|}
\hline
& IO 0 & IO 1 & IO 2 & IO 3 & IO 4 & IO 5 & IO 6 & IO 7 \\ \hline
& IO 0 & IO 1 & IO 2 & IO 3 & IO 4 & IO 5 & IO 6 & IO 7 \\ \hline
Sampler Ch. & \multicolumn{1}{c|}{7} & \multicolumn{1}{c|}{6} & \multicolumn{1}{c|}{5} & \multicolumn{1}{c|}{4} & \multicolumn{1}{c|}{3} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{0} \\ \hline
\end{tabular}
\end{table}
\ordersection{5518 BNC-IDC/5528 SMA-IDC}
\section{Front Panel Drawings}
\finalfootnote
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=2.7in]{bnc_idc_drawings.pdf}
\captionof{figure}{5518 BNC-IDC front panel drawings}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (5518 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90506946 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=2.7in]{bnc_idc_assembly.pdf}
\captionof{figure}{5518 BNC-IDC front panel assembly}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (5518 Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90506946 & 1 & FP-LYKJ 3U8HP PANEL \\ \hline
2 & 3033098 & 0.04 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
3 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
4 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
5 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
6 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI (100EA) \\ \hline
7 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
8 & 3207076 & 0.01 & SCR M2.5*16 PAN 100 21101-222 \\ \hline
9 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT (100PCS) \\ \hline
10 & 3211232 & 1 & SCR M2.5*14 PAN PHL SS \\ \hline
11 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=3in]{sma_idc_drawings.pdf}
\captionof{figure}{5528 SMA-IDC front panel drawings}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (5528 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90506946 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=3in]{sma_idc_assembly.pdf}
\captionof{figure}{5528 SMA-IDC front panel assembly}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (5528 Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90506949 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3040012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
6 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
7 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI (100EA) \\ \hline
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
9 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 5518 BNC-IDC/5528 SMA-IDC in the ARTIQ Sinara crate configuration tool.
The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

82
5568.tex
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@ -1,5 +1,25 @@
\input{preamble.tex}
\graphicspath{{images/5568}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfig}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usepackage{pifont}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{5568 HD68-IDC}
\author{M-Labs Limited}
@ -13,9 +33,9 @@
\section{Features}
\begin{itemize}
\item{32 channels}
\item{Internal IDC connector}
\item{External HD68 connectors}
\item{32 channels.}
\item{Internal IDC connector.}
\item{External HD68 connectors.}
\end{itemize}
\section{Applications}
@ -32,13 +52,25 @@
\end{itemize}
\section{General Description}
The 5568 HD68-IDC card is a 4hp EEM module, part of the ARTIQ/Sinara family. It is an adapter card that converts IDC connections to or from HD68 connections. It can be connected via external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
The 5568 HD68-IDC card is a 4hp EEM module part of the ARTIQ Sinara family.
It is an adapter that converts IDC connection from/to HD68 connection.
It connects to an external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
Each card supports 32 channels, with one HD68 connector and four IDC connectors. Each IDC connector supports 8 channels. All 32 channels can be accessed using an external HD68 cable.
Each card support 32 channels, with 1 HD68 connector and 4 IDC connectors.
Each IDC connector supports 8 channels, while all 32 channels are accessible using an external HD68 cable.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{1}{
@ -48,10 +80,10 @@ Each card supports 32 channels, with one HD68 connector and four IDC connectors.
\draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
% IDC Connectors to IDC cards
\draw (3.0, 1.8) node[twoportshape, t={\twocm{IDC}{CH 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem2) {};
\draw (1.8, 1.8) node[twoportshape, t={\twocm{IDC}{CH 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem3) {};
\draw (3.0, -1.8) node[twoportshape, t={\twocm{IDC}{CH 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem1) {};
\draw (1.8, -1.8) node[twoportshape, t={\twocm{IDC}{CH 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem0) {};
\draw (3.0, 1.8) node[twoportshape, t={\MyLabel{IDC}{CH 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem2) {};
\draw (1.8, 1.8) node[twoportshape, t={\MyLabel{IDC}{CH 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem3) {};
\draw (3.0, -1.8) node[twoportshape, t={\MyLabel{IDC}{CH 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem1) {};
\draw (1.8, -1.8) node[twoportshape, t={\MyLabel{IDC}{CH 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem0) {};
% Connect Op-amp to EEM OUT and HD68
\draw [-latexslim] (3.0, 0) -- (hd68.east);
@ -68,30 +100,36 @@ Each card supports 32 channels, with one HD68 connector and four IDC connectors.
\begin{figure}[h]
\centering
\includegraphics[height=3.5in, angle=90]{photo5568.jpg}
\includegraphics[height=3in, angle=90]{HD68_IDC_FP.pdf}
\caption{Card and front panel}
\includegraphics[height=2.1in]{HD68_IDC_FP.pdf}
\includegraphics[height=2.1in]{photo5568.jpg}
\caption{HD68-IDC Card photo}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{5568 HD68-IDC}{https://github.com/sinara-hw/IDC_HD68_Adapter}
\section{Cable Connection Diagram}
The 5568 HD68-IDC card can convert signals from HD68 format to IDC format. Within the Sinara family, the analog output of 5432 DAC Zotino \& 5632 DAC Fastino cards is exported using HD68 connectors. To break out the analog signal into a different crate, connect 5568 HD68-IDC with the DAC card using an external SCSI cable. Then plug in IDC cables to the appropriate IDC connectors to break out the signal to e.g. 5518 BNC-IDC, 5528 SMA-IDC, or 5538 MCX-IDC.
The 5568 HD68-IDC card can convert signal from HD68 format to IDC format.
In the Sinara family, analog output of 5432 DAC Zotino \& 5632 DAC Fastino cards are exported using HD68 connectors.
To break out the analog signal in a different crate, connect 5568 HD68-IDC with the DAC card using an external SCSI cable.
Then, plug in IDC cables to the appropriate IDC connectors to break out the signal to 5518 BNC-IDC or 5528 SMA-IDC cards.
The cable connections for 5568 HD68-IDC can be seen in the diagram below.
\begin{figure}[h]
\centering
\includegraphics[height=4in]{hd68_idc_connection.pdf}
\includegraphics[height=5in]{hd68_idc_connection.pdf}
\caption{HD68-IDC connection diagram}
\end{figure}
\ordersection{5568 HD68-IDC}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 5568 HD68-IDC in the ARTIQ Sinara crate configuration tool.
The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\finalfootnote
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

137
7210.tex
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@ -1,10 +1,29 @@
\input{preamble.tex}
\graphicspath{{images/7210}{images}}
\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfig}
\usepackage{tikz}
\usepackage{pgfplots}
\usepackage{circuitikz}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\title{7210 Clocker}
\author{M-Labs Limited}
\date{January 2024}
\revision{Revision 3}
\date{January 2022}
\revision{Revision 2}
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
\begin{document}
@ -13,18 +32,18 @@
\section{Features}
\begin{itemize}
\item{Low-jitter clock signal distribution}
\item{SMA \& MMCX input}
\item{4 SMA \& 6 MMCX output}
\item{\textless100 fs RMS jitter}
\item{Distribute a low jitter clock signal.}
\item{SMA \& MMCX clock input.}
\item{4 SMA \& 6 MMCX output.}
\item{\textless100 fs RMS clock jitter.}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Distribute clock signals}
\item{Amplify clock signals}
\item{Drive clock input for:\begin{itemize}
\item{Distribute clock signal.}
\item{Clock distribution amplifier.}
\item{Drive clocks input for:\begin{itemize}
\item{4410/4412 DDS Urukul}
\item{4456 Synthesizer Mirny}
\item{4624 Phaser}
@ -32,17 +51,30 @@
\end{itemize}
\section{General Description}
The 7210 Clocker card is a 4hp EEM module, capable of distributing clock signals with \textless100 fs RMS jitter.
The 7210 Clocker card is a 4hp EEM module.
It distrubites clock signal with \textless100 fs RMS jitter.
Clock input can be supplied to Clocker through the external SMA connector or the internal MMCX connector. The input source is selected using an SPDT switch.
Clock input can be supplied to Clocker through the external SMA connector or the internal MMCX connector.
The input source can be selected using an SPDT switch.
Each card distributes the input to 10 outputs.
4 outputs are interfaced with SMA connectors, the other 6 are with MMCX connectors.
Each Clocker card distributes an input to 10 outputs. 4 outputs are interfaced with SMA connectors, the other 6 with MMCX connectors.
Clocker can be powered externally or internally. To provide external power, connect an external 12V power source either through front panel power jack or rear connector. Alternatively, connect it to a carrier card (e.g. 1124 Kasli, 1125 Kasli-SoC) using the EEM port.
Clocker can be powered externally or internally.
To provide external power, connect an external 12V power source through the front panel power jack.
Otherwise, connect it to a carrier card (1124 Kasli or 1125 Kasli-SoC) using the EEM port.
% Switch to next column
\vfill\break
\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand{\inputcolorboxminted}[2]{%
\begin{tcolorbox}[colback=white]
\inputminted[#1, gobble=4]{python}{#2}
\end{tcolorbox}
}
\begin{figure}[h]
\centering
\scalebox{0.95}{
@ -179,11 +211,11 @@ Clocker can be powered externally or internally. To provide external power, conn
\node [label=right:\tiny{SMA CLK IN}] at (sma_clkin) {};
% Draw the SPDT switch
\draw (2.6, -2) node[twoportshape,t=\fourcm{Input Clock \phantom{spac} }{Selection Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.6] (clk_sel) {};
\draw (2.6, -2) node[twoportshape,t=\MymyLabel{Input Clock \phantom{spac} }{Selection Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.6] (clk_sel) {};
\begin{scope}[xshift=3cm, yshift=-1.78cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0);
\draw (1.25,0)to[short,o-](1.6,0) ;
\end{scope}
% Connect CLKINs to the clock buffer
@ -214,24 +246,24 @@ Clocker can be powered externally or internally. To provide external power, conn
\caption{Simplified Block Diagram}
\end{figure}
\vspace{5mm}
\begin{figure}[hbt!]
\centering
\includegraphics[height=3.5in]{photo7210.jpg}
\includegraphics[height=3.5in]{clocker_front_panel.jpg}
\caption{Clocker card and front panel}
\includegraphics[height=3in]{Clocker_FP.jpg}
\includegraphics[height=3in]{photo7210.jpg}
\caption{Clocker Card photo}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{7210 Clocker}{https://github.com/sinara-hw/Clocker}
\section{Electrical Specifications}
Specifications are derived based on the datasheets of the clock buffer (ADCLK950BCPZ\footnote{\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADCLK950.pdf}}) and the RF transformer (TCM2-43X+\footnote{\url{https://www.minicircuits.com/pdfs/TCM2-43X+.pdf}}) used. Clock output specifications are tested by supplying a 100 MHz DDS signal to the SMA input connector\footnote{\label{clocker6}\url{https://github.com/sinara-hw/Clocker/issues/6\#issuecomment-414048168}}. The output is connected to an oscilloscope with 50\textOmega~termination.
Specifications are derived based on the datasheets of
the clock buffer (ADCLK950BCPZ\footnote{\label{clock_buffer}https://www.analog.com/media/en/technical-documentation/data-sheets/ADCLK950.pdf}) \&
the RF transformer (TCM2-43X+\footnote{\label{rf_transformer}https://www.minicircuits.com/pdfs/TCM2-43X+.pdf}).
Clock output specifications is tested by supplying a 100 MHz DDS signal to the SMA input connector.\footnote{\label{clocker6}https://github.com/sinara-hw/Clocker/issues/6\#issuecomment-414048168}
The output is connected to an oscilloscope with 50\textOmega~termination.
\begin{table}[h]
\centering
@ -242,13 +274,13 @@ Specifications are derived based on the datasheets of the clock buffer (ADCLK950
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Clock input & & & & & \\
Clock input\repeatfootnote{clock_buffer}\textsuperscript{,}\repeatfootnote{rf_transformer} & & & & & \\
\hspace{3mm} Peak-to-peak voltage & 0.40 & & 2.40 & V\textsubscript{p-p} & \\
\hspace{3mm} Frequency & 10 & & 4000 & MHz & \\
\hline
Clock output & & & & & \\
\hspace{3mm} Peak-to-peak voltage & & 0.8 & & V\textsubscript{p-p} & \multirow{3}{*}{50\textOmega~load, 100 MHz} \\
\hspace{3mm} Power & & 5 & & dBm & \\
Clock output
& & 0.8 & & V\textsubscript{p-p} & \multirow{3}{*}{50\textOmega~load, 100 MHz} \\
& & 5 & & dBm & \\
\thickhline
\end{tabularx}
\end{threeparttable}
@ -256,44 +288,41 @@ Specifications are derived based on the datasheets of the clock buffer (ADCLK950
\begin{figure}[H]
\centering
\includegraphics[width=6in]{clocker_waveform.png}
\includegraphics[width=5in]{clocker_waveform.png}
\caption{Waveform of Clocker at 100 MHz\repeatfootnote{clocker6}}
\end{figure}
\newpage
\section{Phase-Noise Performance}
Performance measured against 100 MHz Wenzel Quartz, phase-locked to 10MHz Wenzel Blue Top oscillator\footnote{\label{clockerpn}\url{https://github.com/sinara-hw/Clocker/issues/4\#issuecomment-1310591042}}. Blue trace represents measurement against itself for reference.
\begin{figure}[H]
\centering
\includegraphics[width=6.5in]{clocker_phase_noise.png}
\caption{Absolute phase noise of Clocker measured @ 100 MHz (pink trace)\repeatfootnote{clockerpn}}
\end{figure}
\section{Selecting Clock Source}
Clock input can be supplied to 7210 Clocker using either the internal MMCX connector or the external SMA connector on the front panel. The selection of clock input is configurable by an SPDT switch, located between the MMCX input connector (\texttt{INT CLK IN}) and the MMCX output connectors. See Figure 5.
Clock input can be supplied to the 7210 Clocker using either the internal MMCX connector or the external SMA connector on the front panel.
The selection of clock input is configurable by a SPDT switch.
It is located between the MMCX input connector (\texttt{INT CLK IN}) and the MMCX output connectors.
\begin{multicols}{2}
Either \texttt{INT} or \texttt{EXT} can be selected.
Either INT or EXT can be selected.
\begin{itemize}
\item Internal MMCX (\texttt{INT}) \\
Clock signal from the MMCX connector \texttt{INT CLK IN} is distributed to all outputs.
\item External SMA (\texttt{EXT}) \\
Clock signal from the SMA connector \texttt{CLK IN} on the front panel is distributed to all outputs.
\itemsep0em
\item Internal MMCX (INT) \\
Clock signal from the MMCX connector \texttt{INT CLK IN} is distributed to all MMCX outputs.
\item External SMA (EXT) \\
Clock signal from the SMA connector \texttt{CLK IN} on the front panel is distributed to all MMCX outputs.
\end{itemize}
\vspace*{\fill}\columnbreak
\columnbreak
\begin{center}
\centering
\includegraphics[height=1.5in]{clocker_spdt_switch.jpg}
\includegraphics[height=1.7in]{clocker_spdt_switch.jpg}
\captionof{figure}{Position of the SPDT switch}
\end{center}
\end{multicols}
\ordersection{7210 Clocker}
\finalfootnote{}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 7210 Clocker in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
\end{document}

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@ -1,13 +0,0 @@
inputs = 1124 2118-2128 2238 2245 4410-4412 4456 5108 5432 5518-5528 5568 7210
dir = build
all: $(inputs)
$(inputs) : % : %.tex
pdflatex -shell-escape $@.tex
if ! test -d "$(dir)"; then mkdir build; fi
mv $@.pdf build/
rm $@.log
clean:
rm -r _minted* *.aux *.out

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20
README.md
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@ -1,20 +0,0 @@
# sinara-hw/datasheets
Repository for Sinara hardware datasheets.
## Build all
```shell
nix build .#all-pdfs
```
Output files will be in `result`.
### Build individual sheets
```shell
nix develop
make 1124
```
Output files will be in `build`. Run make twice in a row to get correct output for all LaTeX features, i.e. in particular correct "page x of y" footnotes, which require two passes of the compiler. (`#all-pdfs` already does this automatically). Auxiliary files and clutter can be removed with `make clean`.

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28
datasheet.cls
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\RequirePackage{threeparttable}
% Align figure and table captions to left.
\RequirePackage[font=bf,
skip=5pt,
justification=raggedright,
format=hang,
singlelinecheck=off,
hypcap=false]{caption}
\RequirePackage[font=bf, skip=5pt, justification=raggedright, format=hang, singlelinecheck=off]{caption}
% Format hyperlinks as blue and set PDF title based on \title{} in the document.
\RequirePackage[pdfusetitle]{hyperref}
\hypersetup{
pdftex,
breaklinks=true,
colorlinks=true,
linkcolor=.,
urlcolor=blue
}
% Configure page margins
\RequirePackage{geometry}
@ -119,17 +124,6 @@
% No numbering for section titles
\setcounter{secnumdepth}{0}
% Section and subsection spacing
\usepackage{titlesec}
\titlespacing*{\section}{0pt}{.2ex}{.2ex}
\titlespacing*{\subsection}{0pt}{.2ex}{.2ex}
% Format hyperlinks as blue and set PDF title based on \title{} in the document.
% Hyperref must be loaded last (in particular after titlesec)
\RequirePackage[pdfusetitle]{hyperref}
\hypersetup{
breaklinks=true,
colorlinks=true,
linkcolor=.,
urlcolor=blue
}

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flake.lock
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{
"nodes": {
"nixpkgs": {
"locked": {
"lastModified": 1729880355,
"narHash": "sha256-RP+OQ6koQQLX5nw0NmcDrzvGL8HDLnyXt/jHhL1jwjM=",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "18536bf04cd71abd345f9579158841376fdd0c5a",
"type": "github"
},
"original": {
"owner": "NixOS",
"ref": "nixos-unstable",
"repo": "nixpkgs",
"type": "github"
}
},
"root": {
"inputs": {
"nixpkgs": "nixpkgs"
}
}
},
"root": "root",
"version": 7
}

43
flake.nix
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{
description = "Sinara datasheets";
inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable;
outputs = { self, nixpkgs }:
let
pkgs = import nixpkgs { system = "x86_64-linux";};
latex-pkgs = pkgs.texlive.combine {
inherit (pkgs.texlive)
scheme-small collection-latexextra collection-fontsextra
collection-fontsrecommended cbfonts-fd cbfonts palatino textgreek helvetic
greek-inputenc maths-symbols mathpazo babel isodate tcolorbox etoolbox
pgfplots visualtikz quantikz tikz-feynman circuitikz
minted pst-graphicx;
};
python-pkgs = with pkgs.python3Packages; [ pygments ];
in rec {
all-pdfs = pkgs.stdenvNoCC.mkDerivation rec {
name = "datasheets-pdfs";
src = self;
buildInputs = [ latex-pkgs ] ++ python-pkgs;
# is there a better way to get .aux/.out files correct than to just run latexpdf twice?
buildPhase = ''
make all
make all
'';
installPhase = ''
mkdir $out
cp build/*.pdf $out
'';
};
devShells.x86_64-linux.default = pkgs.mkShell {
name = "datasheet-dev-shell";
buildInputs = [ latex-pkgs ] ++ python-pkgs;
};
};
}

3
footnote.tex
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\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}

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64
preamble.tex
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\documentclass[10pt]{datasheet}
\usepackage{palatino}
\usepackage{textgreek}
\usepackage{minted}
\usepackage{tcolorbox}
\usepackage{etoolbox}
\usepackage[justification=centering]{caption}
\usepackage[utf8]{inputenc}
\usepackage[english]{babel}
\usepackage[english]{isodate}
\usepackage{graphicx}
\usepackage{subfig}
\usepackage{tikz}
\usepackage{pgfplots}
\pgfplotsset{compat=1.18}
\usepackage{circuitikz}
\usepackage{pifont}
\usetikzlibrary{calc}
\usetikzlibrary{fit,backgrounds}
\newcommand*{\twocm}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand*{\fourcm}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
\newcommand{\inputcolorboxminted}[3][4]{%
\begin{tcolorbox}[colback=white]
\inputminted[#2, gobble=#1]{python}{#3}
\end{tcolorbox}
}
\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
\newcommand*{\sourcesection}[2]{
\section{Source}
#1, like all the Sinara hardware family, is open-source hardware, and design files (schematics, PCB layouts, BOMs) can be found in detail at the repository \url{#2}.
}
\newcommand*{\sourcesectiond}[4]{
\section{Source}
#1 and #2, like all the Sinara hardware family, are open-source hardware, and design files (schematics, PCB layouts,
BOMs) can be found in detail at the repositories \url{#3} and \url{#4}.
}
\newcommand*{\ordersection}[1]{
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and choose #1 in the ARTIQ/Sinara hardware selection tool. Cards can be ordered as part of a fully-featured ARTIQ/Sinara crate or standalone through the 'Spare cards' option. Otherwise, orders can also be made by writing directly to \url{mailto:sales@m-labs.hk}.
}
\newcommand{\codesection}[1] {
\section{Example ARTIQ Code}
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources of the #1. They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
}
\newcommand*{\finalfootnote}{
\section*{}
\vspace*{\fill}
\begin{footnotesize}
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
\end{footnotesize}
}

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44
shell.nix Normal file
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@ -0,0 +1,44 @@
let
pkgs = import <nixpkgs> {};
in
pkgs.mkShell {
buildInputs = [
#pkgs.texlive.combined.scheme-small
(pkgs.texlive.combine {
inherit (pkgs.texlive)
scheme-small
collection-latexextra
collection-fontsextra
collection-fontsrecommended
palatino
textgreek
minted
tcolorbox
etoolbox
maths-symbols
greek-inputenc
babel
isodate
pst-graphicx
visualtikz
quantikz
tikz-feynman
pgfplots
cbfonts-fd
cbfonts
mathpazo
helvetic
circuitikz ;
# To compile, call:
# $ pdflatex -shell-escape xxx.tex
# if missing packages, you can search if the required tex packages is in nixpkgs or not from here
# https://raw.githubusercontent.com/NixOS/nixpkgs/master/pkgs/tools/typesetting/tex/texlive/pkgs.nix
# if available, just add it to the above list
})
];
}

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63
template.tex
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\include{preamble.tex}
\graphicspath{{images}}
\title{BOARD NAME}
\author{M-Labs Limited}
\date{October 2024}
\revision{Revision 1}
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
\begin{document}
\maketitle
\section{Features}
\begin{itemize}
\item{features}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{applications}
\end{itemize}
\section{General Description}
% Switch to next column
\vfill\break
\begin{figure}[h]
\centering
\scalebox{1.15}{
\begin{circuitikz}[european, every label/.append style={align=center}]
\begin{scope}[]
% if applicable
\end{scope}
\end{circuitikz}
}
\caption{Simplified Block Diagram}
\end{figure}
\begin{figure}[hbt!]
\centering
% card photo
% front panel
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\section{Specifications}
\newpage
\section{Example ARTIQ code}
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\end{document}

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