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173
1124.tex
173
1124.tex
@ -1,5 +1,4 @@
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\input{preamble.tex}
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\input{shared/coredevice.tex}
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\include{preamble.tex}
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\graphicspath{{images/1124}{images}}
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\title{1124 Carrier Kasli 2.0}
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@ -14,28 +13,28 @@
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\section{Features}
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\begin{itemize}
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\item{4 SFP 6Gb/s slots for Ethernet \& DRTIO at 2.5Gb/s}
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\item{12 EEM ports for daughtercards}
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\item{4 MMCX clock outputs}
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\item{Xilinx Artix-7 FPGA core}
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\item{DDR3 SDRAM}
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\item{4 SFP 6Gb/s slots for Ethernet and DRTIO}
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\item{12 EEM ports for daughtercards}
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\item{4 MMCX clock outputs}
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\item{Xilinx Artix-7 FPGA core}
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\item{DDR3 SDRAM}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{Run ARTIQ kernels}
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\item{Communicate with the host}
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\item{Control other Sinara EEM cards}
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\item{Distributed Real-Time I/O}
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\item{Run ARTIQ kernels}
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\item{Communicate with the host}
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\item{Control other Sinara EEM cards}
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\item{Distributed Real-Time I/O}
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\end{itemize}
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\section{General Description}
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The 1124 Kasli 2.0 Carrier card is an 8hp EEM module, designed to run ARTIQ kernels sent from a host machine over the network. It supports up to 12 EEM connections to other EEM cards in the ARTIQ/Sinara family and up four SFP connections, used for comunications with other carriers and/or Ethernet.
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The 1124 Kasli 2.0 Carrier card is an 8hp EEM module, designed to run ARTIQ kernels sent from a host machine over the network. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections, used for comunications with other carriers and/or Ethernet.
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Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
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Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
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4 SFP 6Gb/s slots are provided. One may be used for Ethernet, which supports communication with a host machine. Remaining slots can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the \mbox{DRTIO} master.
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4 SFP 6Gb/s slots are provided. One may be used for Ethernet, which supports communication with a host machine. Remaining slots can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the \mbox{DRTIO} master.
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% Switch to next column
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\vfill\break
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@ -164,74 +163,142 @@
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\caption{Kasli 2.0 front panel}
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\end{figure}
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% END PAGE ONE (for wide pages a single-column layout is preferable)
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% For wide tables, a single column layout is better. It can be switched
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% page-by-page.
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\onecolumn
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\sourcesection{Kasli 2.0}{https://github.com/sinara-hw/Kasli}
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\section{Electrical Specifications}
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External clock parameters are derived based on the internal termination specified in
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UG471\footnote{\label{ug471}\url{https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO}}
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and the voltage range specified in
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DS181\footnote{\label{ds181}\url{https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
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\begin{table}[h]
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\centering
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\begin{threeparttable}
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\caption{Recommended Operating Conditions}
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\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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Clock input & & & & &\\
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\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
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\cline{2-6}
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% 100R termination & 100/350/600 mV differential input after the transformer.
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& \multicolumn{3} {c|}{10/100/125} & MHz & RTIO clock synthesized from input \\
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\cline{2-6}
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\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
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\hline
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Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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External clock parameters are derived based on the internal termination specified in
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UG471\footnote{\label{ug471}\url{https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO}}
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and the voltage range specified in
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DS181\footnote{\label{ds181}\url{https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
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\spectable
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Power is to be supplied through the barrel connector in the front panel, size 5.5 mm OD, 2.5 mm ID, and is passed on to daughtercards through the EEM connections. Locking barrel connectors are supported.
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\section{FPGA}
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Kasli 2.0 features an XC7A100T-3FGG484E Xilinx Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.
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Kasli 2.0 features an XC7A100T-3FGG484E Xilinx Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.
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A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
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ARTIQ is open-source and can be found in the repository \url{https://github.com/m-labs/artiq}. Orders of Sinara hardware are normally accompanied with precompiled binaries. Long-term support for ARTIQ systems can also be purchased.
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\artiqsection
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A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
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\noteondrtio{Kasli 2.0}
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\subsection{Note on distributed RTIO (DRTIO)}
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DRTIO is the time and data transfer system that allows ARTIQ RTIO channels to be distributed among several core device carrier boards, synchronized and controlled by a central core device. The system itself is more fully described in the ARTIQ documentation\footnote{\label{manual-drtio}\url{https://m-labs.hk/artiq/manual/drtio.html}}. With ARTIQ firmware/gateware, supported core devices, including Kasli 2.0, can take one of three roles:
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\begin{enumerate}
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\item \textbf{Master} \\
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The DRTIO master is unique in a DRTIO system. It requires a direct network connection to the host machine. It may make downstream connections to satellites. It controls its own local RTIO channels and the downstream DRTIO satellite(s).
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\item \textbf{Satellite} \\
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Any other core devices in a DRTIO system are DRTIO satellites. They require an upstream connection to one other core device, master or satellite, through which communications will ultimately be chained to the master. They may make further downstream connections to other satellites. They may control RTIO channels through subkernels or simply pass on communications from the master.
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\item \textbf{Standalone}\\
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When run in a non-distributed ARTIQ configuration, with a single central core device but no satellites, that core device is instead known as standalone.
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\end{enumerate}
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\section{Communication Interfaces}
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Communication between devices is implemented using 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on the Kasli 2.0. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
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Communication between devices is implemented using 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on the Kasli 2.0. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
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Transceiver maximum speed is 6.6 Gb/s\footnote{\url{https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/high-speed-serial.html}}. DRTIO is normally run at 2.5 Gb/s with 8b10b encoding.
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\subsection{Upstream connection}
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\subsection{Upstream connection}
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A Kasli 2.0 board must acquire an upstream connection through the \texttt{SFP0} slot.
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A Kasli 2.0 board must acquire an upstream connection through the \texttt{SFP0} slot.
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\begin{itemize}
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\item \textbf{Standalone/Master} \\
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An Ethernet-capable SFP transceiver should be inserted into the \texttt{SFP0} slot. Typically, a 10000Base-X RJ45 SFP module is used, with an network-connected Ethernet cable attached to the module.
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\item \textbf{Satellite} \\
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The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable connection with SFP transceivers.
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\end{itemize}
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\begin{itemize}
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\item \textbf{Standalone/Master} \\
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An Ethernet-capable SFP transceiver should be inserted into the \texttt{SFP0} slot. Typically, a 10000Base-X RJ45 SFP module is used, with an network-connected Ethernet cable attached to the module.
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\item \textbf{Satellite} \\
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The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable or fibre connection with SFP transceivers.
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\end{itemize}
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\subsection{Downstream connection}
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Kasli 2.0 supports up to 3 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be used.
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\subsection{Downstream connection}
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Kasli 2.0 supports up to 3 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be used. The destination on port \texttt{SFPn} normally receives the destination number \texttt{n}.
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\section{Clock Routing}
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\subsection{Standalone/Master}
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The RTIO clock is typically synthesized by the Si5324 clock multiplier and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors. Alternatively, an external reference can be supplied through the front panel SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis. Kasli 2.0 supports a set of RTIO clock options:
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\begin{table}[H]
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\centering
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\begin{tabular}{|c|c|c|}
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\hline
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RTIO frequency & Configuration & Clock generation \\ \hline
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100 MHz & \texttt{int\char`_100} & internal crystal oscillator using PLL, 100 MHz output \\ \hline
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\multirow{4}{*}{125 MHz} & \texttt{int\char`_125} & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
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& \texttt{ext0\char`_synth0\char`_10to125} & external 10 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
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& \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
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& \texttt{ext0\char`_synth0\char`_125to125} & external 125 MHz reference using PLL, 125 MHz output \\ \hline
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150 MHz & \texttt{int\char`_150} & internal crystal oscillator using PLL, 150 MHz output \\ \hline
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\end{tabular}
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\end{table}
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\clockingsection{Kasli 2.0}{FPGA}
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The clock synthesizer may also be bypassed, using the \texttt{ext0\char`_bypass} option, which will accept a RTIO clock directly supplied to the SMA connector. The resulting signal is then routed to both the RTIO system and downstream satellites.
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Clocking options in a running system should be configured by setting the value of the \texttt{rtio\char`_clock} key to the desired configuration through \texttt{artiq\char`_coremgmt}. For example, a RTIO frequency of 125MHz will be synthesized from an external 10 MHz signal after issuing the following command:
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\begin{minted}{bash}
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artiq_coremgmt config write -s rtio_clock ext0_synth0_10to125
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\end{minted}
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and rebooting.
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\subsection{Satellite}
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The RTIO clock is recovered from the SFP transceiver connected to the upstream device. The resulting signal is then cleaned up by the Si5324 and routed to both the RTIO system and downstream satellites.
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\subsection{WRPLL}
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Kasli 2.0 can be configured to use WRPLL, a clock recovery method making use of White Rabbit's DDMTD (Digital Dual Mixer Time Difference) and the card's Si549 oscillators, both to lock the main RTIO clock and to lock satellite clocks to master.
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\section{User LEDs}
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Kasli 2.0 supplies three user LEDs for debugging purposes. Two are located on the front panel. The third is located on the PCB itself, beside the SFP cage. An additional ERR LED on the front panel is used by ARTIQ firmware to indicate a runtime panic.
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Kasli 2.0 supplies three user LEDs for debugging purposes. Two are located on the front panel. The third is located on the PCB itself, beside the SFP cage. An additional ERR LED on the front panel is used by ARTIQ firmware to indicate a runtime panic.
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\sysdescsection
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\newpage
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An example description file for a system using 1124 Kasli 2.0 as a master core device might begin:
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\codesection{Kasli 2.0 1124 carrier}
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\begin{tcolorbox}[colback=white]
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\begin{minted}{json}
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"target": "kasli",
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"variant": "my_variant",
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"hw_rev": "v2.0",
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"base": "master",
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"peripherals": [ ]
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\end{minted}
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\end{tcolorbox}
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\subsection{Direct Memory Access (DMA)}
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Instead of directly emitting RTIO events, sequences of RTIO events can be recorded in advance and stored in the local SDRAM. The event sequence can then be replayed at a specified timestamp. This is of special advantage in cases where RTIO events are too closely placed to be generated as they are executed, as events can be replayed at a higher speed than the on-FPGA CPU alone is capable of.
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\coresysdesc
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The following example records an LED event sequence and replays it twice consecutively using \texttt{CoreDMA}. When run, the LED should blink twice.
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\coredevicecode{Kasli 2.0 1124 carrier}
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\inputcolorboxminted{firstline=10,lastline=29}{examples/dma.py}
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Stored waveforms can be referenced and replayed in different kernels, but cannot be retrieved and must be regenerated if the core device is rebooted.
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\newpage
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\subsection{Dataset manipulation with core device cache}
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Experiments may require values computed or found in previously executed kernels. To avoid invoking an RPC or sacrificing the pre-computation in \texttt{prepare()} stage, data can be stored in the core device cache.
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The following code snippets describe two experiments, in which the data from the first experiment is cached. The data is then retrieved and printed in hexadecimal form in the second experiment.
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\inputcolorboxminted{firstline=9,lastline=16}{examples/cache.py}
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\inputcolorboxminted{firstline=24,lastline=35}{examples/cache.py}
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Similar to DMA, cached data is no longer retrievable once the core device has been rebooted.
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\ordersection{1124 Carrier Kasli 2.0}
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144
1125.tex
144
1125.tex
@ -1,144 +0,0 @@
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\input{preamble}
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\input{shared/coredevice}
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\graphicspath{{images/1125}{images}}
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\title{1125 Carrier Kasli-SoC}
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\author{M-Labs Limited}
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\date{December 2024}
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\revision{Revision 1} % potentially publishable pending whether block diagram is necessary
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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||||
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\begin{itemize}
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\item{RJ45 10/100/1000T Ethernet connector}
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\item{4 SFP 12Gb/s slots for DRTIO at 2.5Gb/s}
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\item{12 EEM ports for daughtercards}
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\item{Xilinx Zynq-7000 SoC with Kintex-7 FPGA}
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\item{SD card flash memory}
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\end{itemize}
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\section{Applications}
|
||||
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\begin{itemize}
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\item{Run ARTIQ kernels}
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\item{Communicate with the host}
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\item{Control other Sinara EEM cards}
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||||
\item{Distributed Real-Time I/O}
|
||||
\end{itemize}
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||||
\section{General Description}
|
||||
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||||
The 1125 Kasli-SoC Carrier card is an 8hp EEM module, designed to run ARTIQ-Zynq kernels sent over the network from a host machine. Kasli-SoC is built around a Xilinx Zynq-7000 SoC, capable of running more complex computations at high speed than its sister card 1124 Kasli 2.0. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections for comunications with other carriers. A dedicated Ethernet port is used for communications with the host.
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||||
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||||
Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
|
||||
|
||||
4 SFP 12Gb/s slots are provided. These can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli or other Kasli-SoCs) as satellite cards, capable of running subkernels or relaying commands to a larger number of peripherals.
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||||
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||||
% Switch to next column
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\vfill\break
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||||
% TODO, possibly: block diagram
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||||
\begin{figure}[hbt!]
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||||
\centering
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||||
\includegraphics[height=3in]{photo1125.jpg}
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\caption{Kasli-SoC card}
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||||
\includegraphics[angle=90,height=1in]{Kasli-SoC_FP.pdf}
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||||
\caption{Kasli-SoC front panel}
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||||
\end{figure}
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||||
% END PAGE ONE (for wide pages a single-column layout is preferable)
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\onecolumn
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||||
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||||
\sourcesection{Kasli-SoC}{https://github.com/sinara-hw/Kasli-SOC/}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
External clock parameters are derived based on the internal termination specified in
|
||||
UG471\footnote{\label{ug471}\url{https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO}}
|
||||
and the voltage range specified in
|
||||
DS191\footnote{\label{ds191}\url{https://docs.amd.com/v/u/en-US/ds191-XC7Z030-XC7Z045-data-sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
|
||||
|
||||
\spectable
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||||
|
||||
\section{SoC}
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||||
|
||||
Kasli-SoC features a XC7Z030-3FFG676E Xilinx Zynq-7000 System-on-Chip with a Kintex-7 FGPA and an Cortex-A9 dual-core processor to facilitate high-speed real-time control of inputs and outputs. The use of the SoC allows for more complex computations at higher speed than Kasli 2.0's purely on-FPGA CPU. Usually, the SoC is flashed with firmware and gateware binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with the ability to control other Sinara EEMs and run ARTIQ experiment kernels.
|
||||
|
||||
A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
|
||||
|
||||
\artiqsection
|
||||
|
||||
ARTIQ-supported core devices based on Zynq-7000 SoCs, including Kasli-SoC, require firmware and gateware compiled from the ARTIQ-Zynq port, which can be found in the repository \url{https://git.m-labs.hk/M-Labs/artiq-zynq}.
|
||||
|
||||
\noteondrtio{Kasli-SoC}
|
||||
|
||||
\section{Communication Interfaces}
|
||||
|
||||
Communication between core devices is implemented with 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on 1125 Kasli-SoC. Each SFP connector possesses an indicator LED.
|
||||
|
||||
Transceiver maximum speed is 12.5 Gb/s\footnote{\url{https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/high-speed-serial.html}}. DRTIO is normally run at 2.5 Gb/s with 8b10b encoding.
|
||||
|
||||
Additionally, a RJ45 10/100/1000T Ethernet port is featured for network connection to a host machine.
|
||||
|
||||
\subsection{Upstream connection}
|
||||
|
||||
\begin{itemize}
|
||||
\item \textbf{Standalone/Master} \\
|
||||
A network-connected Ethernet cable should be attached the front panel Ethernet port to enable communication with a host machine.
|
||||
\item \textbf{Satellite} \\
|
||||
Satellites must acquire an upstream connection to another satellite or the master. The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable or fibre connection with SFP transceivers.
|
||||
\end{itemize}
|
||||
|
||||
\subsection{Downstream connection}
|
||||
Kasli-SoC supports up to 4 DRTIO satellite connections per device. Any of the 4 downstream SFP ports (i.e. \texttt{SFP0}, \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be freely used. Port \texttt{SFPn} normally receives the destination number \texttt{n + 1}.
|
||||
|
||||
\clockingsection{Kasli-SoC}{SoC}
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Configuring Boot Mode}
|
||||
|
||||
Kasli-SoC is capable of booting either remotely, over JTAG USB, or directly from the SD card. See the ARTIQ manual for more instructions on how to correctly flash and boot a core device. Boot mode must be configured by flipping physical switches on the board. The boot mode DIP switches are located in the middle of the board. To boot from USB, flip both switches towards the label \texttt{JTAG}. To boot from the SD card, flip both switches towards the label \texttt{SD}.
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=3in]{kasli-soc_dip_switches.jpg}
|
||||
\caption{Position of DIP switches, SD card, and reset pins}
|
||||
\end{figure}
|
||||
|
||||
\subsection{POR jumpers and POR reset}
|
||||
|
||||
A known Xilinx hardware bug prevents repeatedly booting over JTAG without a POR reset. If necessary, repeated boots can be made possible by physically setting jumpers on both the \texttt{PS\_POR\_B} and \texttt{PS\_SRST\_B} pins (marked in figure above) and triggering a reset over JTAG, see also the M-Labs POR reset script.\footnote{\url{https://git.m-labs.hk/M-Labs/zynq-rs/src/branch/master/kasli_soc_por.py}}
|
||||
|
||||
\section{User LEDs}
|
||||
|
||||
Kasli-SoC designates two user LEDs for debugging purposes. One is located on the PCB; it can be found at the very bottom left of the board, below the SFP cage, labeled \texttt{USER0}. The second is located on the front panel, besides the Ethernet port, labeled \texttt{L1}.
|
||||
|
||||
\sysdescsection
|
||||
|
||||
An example description file for a system using 1125 Kasli-SoC as a master core device might begin:
|
||||
|
||||
\begin{tcolorbox}[colback=white]
|
||||
\begin{minted}{json}
|
||||
"target": "kasli_soc",
|
||||
"variant": "my_variant",
|
||||
"hw_rev": "v1.0",
|
||||
"base": "master",
|
||||
"peripherals": [ ]
|
||||
\end{minted}
|
||||
\end{tcolorbox}
|
||||
|
||||
\coresysdesc
|
||||
|
||||
\coredevicecode{1125 Kasli-SoC carrier}
|
||||
|
||||
\ordersection{1125 Carrier Kasli-SoC}
|
||||
|
||||
\finalfootnote
|
||||
|
||||
\end{document}
|
||||
@ -34,9 +34,9 @@ The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module
|
||||
|
||||
Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
||||
|
||||
Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely. Both cards are capable of a minimum pulse width of 3ns.
|
||||
Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely.
|
||||
|
||||
Note that isolated TTL cards are less suited to low-noise applications as the isolator itself injects noise between primary and secondary sides. Cable shields may also radiate EMI from the isolated grounds. For low-noise applications, use non-isolated cards such as 2238 MCX-TTL or 2245 LVDS-TTL.
|
||||
Both cards are capable of a minimum pulse width of 3ns.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
||||
257
5108.tex
257
5108.tex
@ -1,4 +1,4 @@
|
||||
\input{preamble.tex}
|
||||
\include{preamble.tex}
|
||||
\graphicspath{{images/5108}{images}}
|
||||
|
||||
\title{5108 ADC Sampler}
|
||||
@ -13,29 +13,34 @@
|
||||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{8-channel ADC}
|
||||
\item{16-bits resolution}
|
||||
\item{1.5 MSPS simultaneously on all channels}
|
||||
\item{Full scale input voltage, $\pm$10mV to $\pm$10V}
|
||||
\item{BNC connector}
|
||||
\item{SMA breakout with 5528 SMA-IDC adapter}
|
||||
\item{8-channel ADC.}
|
||||
\item{16-bits resolution.}
|
||||
\item{1.5 MSPS simultaneously on all channels.}
|
||||
\item{Full scale input voltage $\pm$10mV to $\pm$10V.}
|
||||
\item{BNC connector.}
|
||||
\item{SMA breakout with 5528 SMA-IDC adapter.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Sample intermediate-frequency (IF) waveform}
|
||||
\item{Monitor laser power with a photodiode}
|
||||
\item{Synchronize laser frequencies with a phase frequency detector}
|
||||
\item{Form a laser intensity servo with 4410 Urukul}
|
||||
\item{Sample intermediate-frequency (IF) waveform.}
|
||||
\item{Monitor laser power with a photodiode.}
|
||||
\item{Synchronize laser frequencies with a phase frequency detector.}
|
||||
\item{Form a laser intensity servo with 4410 Urukul.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 5108 ADC Sampler is a 8hp EEM module, part of the ARTIQ/Sinara family. It adds analog-digital converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
The 5108 ADC Sampler is a 8hp EEM module part of the ARTIQ Sinara family.
|
||||
It adds analog-digital converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
It provides eight analog-to-digital channels, exposed by eight BNC connectors. Each channel supports input voltage ranges from \textpm 10mV to \textpm 10V. All channels can be sampled simultaneously. Channels can broken out to SMA by adding a 5528 SMA-IDC card.
|
||||
It provides 8 analog-to-digital channels, each exposed by a BNC connector.
|
||||
Each channel supports input voltage ranges from \textpm 10mV to \textpm 10V.
|
||||
All channels can be sampled simultaneously.
|
||||
Channels can broken out to SMA by adding a 5528 SMA-IDC card.
|
||||
|
||||
5108 ADC Sampler provides a sample rate of 1.5 MSPS. However, the sample rate in practice is typically limited by the use of ARTIQ-Python kernel code.
|
||||
5108 ADC Sampler provides a sample rate of 1.5 MSPS.
|
||||
However, the sample rate in practice is typically limited by the use of ARTIQ-Python kernel code.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
@ -129,7 +134,7 @@ It provides eight analog-to-digital channels, exposed by eight BNC connectors. E
|
||||
\begin{scope}[xshift=1.2cm, yshift=1.925cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
|
||||
\draw (0.4,0) to[short,-o](0.75,0);
|
||||
\draw (0.78,0)-- +(30:0.46);
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\draw (1.25,0)to[short,o-](1.6,0) ;
|
||||
\end{scope}
|
||||
|
||||
% Dwar IDC Port (ADC IN)
|
||||
@ -249,19 +254,17 @@ It provides eight analog-to-digital channels, exposed by eight BNC connectors. E
|
||||
\caption{Simplified Block Diagram}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[height=2.3in]{photo5108.jpg}
|
||||
\includegraphics[height=2.5in, angle=90]{Sampler_FP.jpg}
|
||||
\caption{Sampler card and front panel}
|
||||
\includegraphics[height=1.9in]{Sampler_FP.jpg}
|
||||
\includegraphics[height=1.9in]{photo5108.jpg}
|
||||
\caption{Sampler Card photo}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{5108 ADC Sampler}{https://github.com/sinara-hw/Sampler}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
\begin{table}[h]
|
||||
@ -289,9 +292,9 @@ It provides eight analog-to-digital channels, exposed by eight BNC connectors. E
|
||||
\end{table}
|
||||
|
||||
|
||||
The electrical characteristics are based on various test results\footnote{\label{sinara226}\url{https://github.com/sinara-hw/sinara/issues/226}}\textsuperscript{,}
|
||||
\footnote{\label{sinara489}\url{https://github.com/sinara-hw/sinara/issues/489}}\textsuperscript{,}
|
||||
\footnote{\label{sampler2}\url{https://github.com/sinara-hw/Sampler/issues/2}}.
|
||||
The electrical characteristics are based on various test results\footnote{\label{sinara226}https://github.com/sinara-hw/sinara/issues/226}\textsuperscript{,}
|
||||
\footnote{\label{sinara489}https://github.com/sinara-hw/sinara/issues/489}\textsuperscript{,}
|
||||
\footnote{\label{sampler2}https://github.com/sinara-hw/Sampler/issues/2}.
|
||||
|
||||
\begin{table}[hbt!]
|
||||
\centering
|
||||
@ -319,18 +322,6 @@ The electrical characteristics are based on various test results\footnote{\label
|
||||
& & 206.3 & & LSB RMS & Termination off \\
|
||||
% \hline
|
||||
DC cross-talk\repeatfootnote{sinara226} & & & -96 & dB & 1x gain\\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics (cont.)}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions / Comments} \\
|
||||
\hline
|
||||
% AC cross-talk data on wiki is also outdated (when it was still novo)
|
||||
% sinara-hw/sinara #489 is a better source of info
|
||||
@ -340,33 +331,49 @@ The electrical characteristics are based on various test results\footnote{\label
|
||||
& & -51 & & dBc & 0.1 V\textsubscript{pp} (-48dBFS), limited by ADC (-100dBFS) \\
|
||||
& & -69 & & dBc & 1 V\textsubscript{pp} (-28dBFS) \\
|
||||
& & -58.8 & & dBc & 10 V\textsubscript{pp} (-8dBFS) \\
|
||||
\hline
|
||||
Common-mode rejection ratio\repeatfootnote{sinara226} & & & & & 2 V\textsubscript{pp} sine wave as CM input, termination on\\
|
||||
\hspace{12mm} 1x gain & & & -98 & dB & $f=0.01,0.1,1$ kHz \\
|
||||
& & -87 & & dB & $f=10$ kHz \\
|
||||
& & -55 & & dB & $f=100$ kHz \\
|
||||
& & -83 & & dB & $f=1$ MHz \\
|
||||
& & -85 & & dB & $f=10$ MHz \\
|
||||
\cline{2-6}
|
||||
\hspace{12mm} 100x gain & & & -118 & dB & $f=0.01$ kHz \\
|
||||
& & -98 & & dB & $f=0.1$ kHz \\
|
||||
& & -88 & & dB & $f=1$ kHz \\
|
||||
& & -70 & & dB & $f=10$ kHz \\
|
||||
& & -50 & & dB & $f=100$ kHz \\
|
||||
& & -80 & & dB & $f=1$ MHz \\
|
||||
& & & -118 & dB & $f=10$ MHz \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\subsection{Channel crosstalk}
|
||||
\newpage
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics (cont.)}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions / Comments} \\
|
||||
\hline
|
||||
Common-mode rejection ratio\repeatfootnote{sinara226} & CMRR & & & & & 2 V\textsubscript{pp} sine wave as CM input, termination on\\
|
||||
\hspace{12mm} 1x gain & & & & -98 & dB & $f=0.01,0.1,1$ kHz \\
|
||||
& & & -87 & & dB & $f=10$ kHz \\
|
||||
& & & -55 & & dB & $f=100$ kHz \\
|
||||
& & & -83 & & dB & $f=1$ MHz \\
|
||||
& & & -85 & & dB & $f=10$ MHz \\
|
||||
\cline{3-7}
|
||||
\hspace{12mm} 100x gain & & & & -118 & dB & $f=0.01$ kHz \\
|
||||
& & & -98 & & dB & $f=0.1$ kHz \\
|
||||
& & & -88 & & dB & $f=1$ kHz \\
|
||||
& & & -70 & & dB & $f=10$ kHz \\
|
||||
& & & -50 & & dB & $f=100$ kHz \\
|
||||
& & & -80 & & dB & $f=1$ MHz \\
|
||||
& & & & -118 & dB & $f=10$ MHz \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\newpage
|
||||
|
||||
Crosstalk between ADC channels of 5108 ADC Sampler is shown below\repeatfootnote{sinara489}.
|
||||
|
||||
A 10 V\textsubscript{pp} signal was used as the input. The aggressor channel always has 1x gain. All channels have 50 \textOmega~termination enabled.
|
||||
A 10 V\textsubscript{pp} signal is the input.
|
||||
The aggressor channel always has 1x gain.
|
||||
All channels have 50 \textOmega~termination enabled.
|
||||
|
||||
Data was acquired by taking 512 samples at 80 kHz sampling rate 20 times to average out the FFT.
|
||||
Data is acquired by taking 512 samples at 80 kHz sampling rate 20 times to average out the FFT.
|
||||
|
||||
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
||||
|
||||
@ -420,7 +427,7 @@ Data was acquired by taking 512 samples at 80 kHz sampling rate 20 times to aver
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\clearpage
|
||||
\newpage
|
||||
|
||||
% The plots are quite small given that it is 8-plots-in-1, but the numbers should give a better picture
|
||||
\begin{figure}[hbt!]
|
||||
@ -458,7 +465,7 @@ Data was acquired by taking 512 samples at 80 kHz sampling rate 20 times to aver
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\clearpage
|
||||
\newpage
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
@ -466,14 +473,38 @@ Data was acquired by taking 512 samples at 80 kHz sampling rate 20 times to aver
|
||||
\caption{Crosstalk with 300 kHz input frequency, 1x gain on victim, channel 3 as the aggressor}
|
||||
\end{figure}
|
||||
|
||||
\subsection{Bandwidth}
|
||||
Noise density is measured using the following configuration\repeatfootnote{sampler2}:
|
||||
\begin{enumerate}
|
||||
\item 1/12\textmu s sampling rate
|
||||
\item 10k samples per measurement, averaging over 100 measurements
|
||||
\item Measured at channels 6 \& 7. Channel 6 has the 50\textOmega~termination on, channel 7 has it off
|
||||
\end{enumerate}
|
||||
Noise density with respect to different gain settings with termination on/off are plotted below.
|
||||
|
||||
Bandwidth of small signal and large signal input is shown below\repeatfootnote{sampler2}. The setup is as follows:
|
||||
\begin{multicols}{2}
|
||||
|
||||
\begin{figure}[H]
|
||||
\includegraphics[width=3.3in]{sampler_noise_term.png}
|
||||
\caption{Noise density with termination enabled}
|
||||
\end{figure}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{figure}[H]
|
||||
\includegraphics[width=3.3in]{sampler_noise_no_term.png}
|
||||
\caption{Noise density with termination disabled}
|
||||
\end{figure}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\newpage
|
||||
|
||||
Bandwidth of small signal and large signal input is shown below\repeatfootnote{sampler2}. The setup is as the following:
|
||||
\begin{enumerate}
|
||||
\itemsep0em
|
||||
\item 10k samples, sampled at 79.37 kHz
|
||||
\item Driven by sinusoid from Keysight 33500B generator; sampled using channel 7 without termination
|
||||
\item Small signal measured using 2V\textsubscript{pp}/gain; large signal measured using 15V\textsubscript{pp}/gain
|
||||
\item Driven by sinusoid from Keysight 33500B generator; Sampled using channel 7 without termination
|
||||
\item Small signal measured using 2V\textsubscript{pp}/gain; Large signal measured using 15V\textsubscript{pp}/gain
|
||||
\end{enumerate}
|
||||
\begin{multicols}{2}
|
||||
|
||||
@ -493,13 +524,66 @@ Bandwidth of small signal and large signal input is shown below\repeatfootnote{s
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Front Panel Drawings}
|
||||
\begin{multicols}{2}
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.7in]{sampler_drawings.pdf}
|
||||
\captionof{figure}{5108 ADC Sampler front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.7in]{sampler_assembly.pdf}
|
||||
\captionof{figure}{5108 ADC Sampler front panel assembly}
|
||||
\end{center}
|
||||
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90504202 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
|
||||
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (Assembled)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90504202 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
|
||||
2 & 3033098 & 0.04 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
|
||||
3 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
4 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
5 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
6 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
|
||||
7 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
|
||||
8 & 3207076 & 0.01 & SCR M2.5*12 PAN 100 21101-222 \\ \hline
|
||||
9 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT (100PCS) \\ \hline
|
||||
10 & 3211232 & 1 & SCR M2.5*14 PAN PHL SS \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\section{Configuring Termination}
|
||||
\begin{multicols}{2}
|
||||
The input termination must be configured by setting physical switches on the board. The termination switches are found at the middle left part of the card are by-channel. Switching the termination switches on adds a 50\textOmega~termination between the differential input signals.
|
||||
The input termination can be configured by switches.
|
||||
The per-channel termination switches are found at the middle left part of the card.
|
||||
|
||||
Regardless of switch configurations, the differential input signals are separately terminated with 100k\textOmega~to the PCB ground.
|
||||
Switching on the termination switch adds a 50\textOmega~termination between the differential input signals.
|
||||
|
||||
\vspace*{\fill}
|
||||
Regardless of the switch configurations, the differential input signals are separately terminated with 100k\textOmega~to the PCB ground.
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
@ -508,41 +592,48 @@ Regardless of switch configurations, the differential input signals are separate
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\codesection{5108 ADC Sampler}
|
||||
\newpage
|
||||
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 5108 ADC Sampler card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
\subsection{Get input voltage}
|
||||
The following example initializes the Sampler card with 1x gain on all ADC channels. At the end all ADC channels are sampled.
|
||||
The following example initializes the Sampler card with 1x gain on all ADC channels.
|
||||
Sample all ADC channels at the end.
|
||||
|
||||
\inputcolorboxminted{firstline=9,lastline=21}{examples/sampler.py}
|
||||
|
||||
\newpage
|
||||
|
||||
\subsection{Voltage-controlled DDS amplitude (SU-Servo only)}
|
||||
SU-Servo configuration can be enabled by integrating the 5108 ADC Sampler with 4410 DDS Urukul. Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function:
|
||||
\subsection{Voltage-controlled DDS Amplitude (SU-Servo Only)}
|
||||
The SU-Servo feature can be enabled by integrating the 5108 ADC Sampler with 4410 DDS Urukuls.
|
||||
Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function.
|
||||
\[H(s)=k_p+\frac{k_i}{s+\frac{k_i}{g}}\]
|
||||
In the following example, the amplitude of DDS is proportional to the ADC input from Sampler.
|
||||
|
||||
First, initialize the RTIO, SU-Servo and its channel with 1x gain.
|
||||
|
||||
\inputcolorboxminted{firstline=10,lastline=17}{examples/suservo.py}
|
||||
|
||||
Next, set up the PI control as an IIR filter. It has -1 proportional gain $k_p$ and no integrator gain $k_i$.
|
||||
Next, setup the PI control as an IIR filter. It has -1 proportional gain $k_p$ and no integrator gain $k_i$.
|
||||
|
||||
\inputcolorboxminted{firstline=18,lastline=25}{examples/suservo.py}
|
||||
|
||||
Then, configure the DDS frequency to 10 MHz with 3V input offset. When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
|
||||
Then, configure the DDS frequency to 10 MHz with 3V input offset.
|
||||
When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
|
||||
|
||||
\inputcolorboxminted{firstline=26,lastline=30}{examples/suservo.py}
|
||||
|
||||
SU-Servo encodes the ADC voltage in a linear scale [-1, 1]. Therefore, 3V is converted to 0.3. Note that the ASF of all DDS channels are capped at 1.0; the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
|
||||
SU-Servo encodes the ADC voltage in a linear scale [-1, 1].
|
||||
Therefore, 3V is converted to 0.3.
|
||||
Note that the ASF of all DDS channels are capped at 1.0, the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
|
||||
|
||||
Finally, enable the SU-Servo channel with the IIR filter programmed beforehand:
|
||||
Finally, enable the SU-Servo channel with the IIR filter programmed beforehand.
|
||||
|
||||
\inputcolorboxminted{firstline=32,lastline=33}{examples/suservo.py}
|
||||
|
||||
\newpage
|
||||
|
||||
A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC. The RMS voltage of the DDS channel against the ADC voltage is plotted. The DDS channel is terminated with 50\textOmega.
|
||||
A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC.
|
||||
The RMS voltage of the DDS channel against the ADC voltage is plotted.
|
||||
The DDS channel is terminated with 50\textOmega.
|
||||
|
||||
\begin{center}
|
||||
\begin{tikzpicture}[
|
||||
@ -575,10 +666,16 @@ A 10 MHz DDS signal is generated from the example above, with amplitude controll
|
||||
\end{tikzpicture}
|
||||
\end{center}
|
||||
|
||||
DDS signal should be attenuated. High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power. 15 dB attenuation at the digital attenuator was applied in this example.
|
||||
DDS signal should be attenuated.
|
||||
High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power.
|
||||
15 dB attenuation at the digital attenuator was applied in this example.
|
||||
|
||||
\ordersection{5108 ADC Sampler}
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 5108 ADC Sampler in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\finalfootnote
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\input{footnote.tex}
|
||||
|
||||
\end{document}
|
||||
|
||||
2
Makefile
2
Makefile
@ -1,4 +1,4 @@
|
||||
inputs = 1124 1125 2118-2128 2238 2245 4410-4412 4456 5108 5432 5518-5528 5568 7210
|
||||
inputs = 1124 2118-2128 2238 2245 4410-4412 4456 5108 5432 5518-5528 5568 7210
|
||||
dir = build
|
||||
|
||||
all: $(inputs)
|
||||
|
||||
3
footnote.tex
Normal file
3
footnote.tex
Normal file
@ -0,0 +1,3 @@
|
||||
\begin{footnotesize}
|
||||
Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
|
||||
\end{footnotesize}
|
||||
Binary file not shown.
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|
Before Width: | Height: | Size: 204 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 304 KiB |
BIN
images/5108/sampler_assembly.pdf
Normal file
BIN
images/5108/sampler_assembly.pdf
Normal file
Binary file not shown.
BIN
images/5108/sampler_drawings.pdf
Normal file
BIN
images/5108/sampler_drawings.pdf
Normal file
Binary file not shown.
BIN
images/5108/sampler_noise_no_term.png
Normal file
BIN
images/5108/sampler_noise_no_term.png
Normal file
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|
After Width: | Height: | Size: 70 KiB |
BIN
images/5108/sampler_noise_term.png
Normal file
BIN
images/5108/sampler_noise_term.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 54 KiB |
22
preamble.tex
22
preamble.tex
@ -43,26 +43,18 @@
|
||||
BOMs) can be found in detail at the repositories \url{#3} and \url{#4}.
|
||||
}
|
||||
|
||||
\newcommand{\sysdescsection}{
|
||||
\section{ARTIQ System Description Entry}
|
||||
|
||||
ARTIQ/Sinara firmware/gateware is generated according to a JSON system description file, allowing gateware to be specific to and optimized for a certain system configuration.
|
||||
% It isn't possible to use verbatim environments within \newcommand macros
|
||||
% so the minted colorbox is easier to use directly in each file
|
||||
}
|
||||
|
||||
\newcommand{\codesection}[1]{
|
||||
\section{Example ARTIQ Code}
|
||||
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources of the #1. They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
|
||||
The full documentation for ARTIQ software and gateware, including guides for their use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
|
||||
}
|
||||
|
||||
\newcommand*{\ordersection}[1]{
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and choose #1 in the ARTIQ/Sinara hardware selection tool. Cards can be ordered as part of a fully-featured ARTIQ/Sinara crate or standalone through the 'Spare cards' option. Otherwise, orders can also be made by writing directly to \url{mailto:sales@m-labs.hk}.
|
||||
}
|
||||
|
||||
\newcommand{\codesection}[1] {
|
||||
\section{Example ARTIQ Code}
|
||||
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources of the #1. They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
|
||||
The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
|
||||
}
|
||||
|
||||
\newcommand*{\finalfootnote}{
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
@ -1,119 +0,0 @@
|
||||
\newcommand{\spectable} {
|
||||
\begin{table}[h]
|
||||
\centering
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Clock input & & & & &\\
|
||||
\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
|
||||
\cline{2-6}
|
||||
% 100R termination & 100/350/600 mV differential input after the transformer.
|
||||
& \multicolumn{3} {c|}{10/80/100/125} & MHz & RTIO clock synthesized from input \\
|
||||
\cline{2-6}
|
||||
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
|
||||
\hline
|
||||
Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
Power is to be supplied either through the barrel connector in the front panel (size 5.5 mm OD, 2.5 mm ID) or the Molex connector at the back of the card (compatible with e.g. Sinara 1106 EEM AC Power Module). It is passed on to daughtercards through the EEM connections. Locking barrel connectors are supported.
|
||||
}
|
||||
|
||||
\newcommand{\artiqsection} {
|
||||
\section{Firmware/ARTIQ}
|
||||
|
||||
ARTIQ is open-source and can be found in the repository \url{https://github.com/m-labs/artiq}. Orders of Sinara hardware are normally preflashed with suitable firmware and gateware binaries. Long-term support for ARTIQ systems can also be purchased, including updated binaries through AFWS (the ARTIQ Firmware Service).
|
||||
}
|
||||
|
||||
\newcommand{\noteondrtio}[1]{
|
||||
|
||||
\subsection{Note on distributed RTIO (DRTIO)}
|
||||
|
||||
DRTIO is the time and data transfer system which allows ARTIQ RTIO channels to be distributed among several core device carrier boards, synchronized and controlled by a central master device. The system itself is described in more detail in the ARTIQ documentation\footnote{\label{manual-drtio}\url{https://m-labs.hk/artiq/manual/drtio.html}}. Within ARTIQ, core devices, including #1, can take one of three roles:
|
||||
\begin{enumerate}%[topsep=2pt, itemsep=2pt]
|
||||
\item \textbf{Master} \\
|
||||
A DRTIO system must contain one DRTIO master. It controls its own local RTIO channels and the downstream DRTIO satellite(s). It requires a direct network connection to the host machine. It may make downstream connections to satellites.
|
||||
\item \textbf{Satellite} \\
|
||||
Other core devices in a DRTIO system are DRTIO satellites. They require an upstream connection to one other core device, master or satellite, through which communications are carried to the master. They may make further downstream connections to other satellites. They may control their local RTIO channels directly through subkernels or simply pass on communications from the master.
|
||||
\item \textbf{Standalone}\\
|
||||
When run in a non-distributed ARTIQ configuration, with a single central core device but without satellites, that core device is known as standalone.
|
||||
\end{enumerate}
|
||||
|
||||
}
|
||||
|
||||
\newcommand{\clockingsection}[2]{
|
||||
|
||||
\section{Clock Routing}
|
||||
|
||||
\subsection{Standalone/Master}
|
||||
|
||||
The RTIO clock is typically synthesized by the Si5324 clock multiplier and distributed by the ADCLK948 clock fanout buffer to both the #2 and the MMCX connectors. Alternatively, an external reference can be supplied through the front panel SMA connector. It is then buffered in the #2 and sent to the Si5324 for clock synthesis. #1 supports a set of RTIO clock options:
|
||||
|
||||
\begin{table}[H]
|
||||
\centering
|
||||
\begin{tabular}{|c|c|c|}
|
||||
\hline
|
||||
RTIO frequency & Configuration & Clock generation \\ \hline
|
||||
100 MHz & \texttt{int\char`_100} & internal crystal oscillator using PLL, 100 MHz output \\ \hline
|
||||
\multirow{5}{*}{125 MHz} & \texttt{int\char`_125} & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
|
||||
& \texttt{ext0\char`_synth0\char`_10to125} & external 10 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
|
||||
& \texttt{ext0\char`_synth0\char`_80to125} & external 80 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
|
||||
& \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
|
||||
& \texttt{ext0\char`_synth0\char`_125to125} & external 125 MHz reference using PLL, 125 MHz output \\ \hline
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
The clock synthesizer may also be bypassed, using the \texttt{ext0\char`_bypass} option, which will accept a RTIO clock directly supplied to the SMA connector. The resulting signal is then routed to both the RTIO system and downstream satellites.
|
||||
|
||||
Clocking options in a running system should be configured by setting the value of the \texttt{rtio\char`_clock} key to the desired configuration through the ARTIQ \texttt{artiq\char`_coremgmt} command. For example, a RTIO frequency of 125MHz will be synthesized from an external 10 MHz signal after issuing the following command:
|
||||
|
||||
\begin{center}
|
||||
\texttt{artiq\_coremgmt config write -s rtio\_clock ext0\_synth0\_10to125}
|
||||
\end{center}
|
||||
|
||||
and rebooting.
|
||||
|
||||
\subsection{Satellite}
|
||||
The RTIO clock is recovered from the SFP transceiver connected to the upstream device. The resulting signal is then cleaned up by the Si5324 and routed to both the RTIO system and downstream satellites.
|
||||
|
||||
\subsection{WRPLL}
|
||||
|
||||
#1 can be configured to use WRPLL, a clock recovery method making use of White Rabbit's DDMTD (Digital Dual Mixer Time Difference) and the card's Si549 oscillators, both to lock the main RTIO clock and to lock satellite clocks to master.
|
||||
}
|
||||
|
||||
\newcommand{\coresysdesc}{ % again including the minted JSON snippet through a macro isn't practical
|
||||
|
||||
where the \texttt{peripherals} list contains the corresponding entries for peripherals (daughtercards) in use.
|
||||
|
||||
For all accepted keys and values, see the JSON schema \texttt{coredevice\_generic.schema.json} in the ARTIQ repository.\footnote{\url{https://github.com/m-labs/artiq/blob/release-8/artiq/coredevice/coredevice_generic.schema.json}}.
|
||||
}
|
||||
|
||||
\newcommand{\coredevicecode}[1] {
|
||||
\codesection{#1}
|
||||
|
||||
\subsection{Direct Memory Access (DMA)}
|
||||
|
||||
Instead of directly emitting RTIO events, sequences of RTIO events can be recorded in advance and stored in the local SDRAM. The event sequence can then be replayed at a specified timestamp. This is of special advantage in cases where RTIO events are too closely placed to be generated as they are executed, as events can be replayed at a higher speed than the on-FPGA CPU alone is capable of.
|
||||
|
||||
The following example records an LED event sequence and replays it twice consecutively using \texttt{CoreDMA}. When run, the LED should blink twice.
|
||||
|
||||
\inputcolorboxminted{firstline=10,lastline=29}{examples/dma.py}
|
||||
|
||||
Stored waveforms can be referenced and replayed in different kernels, but cannot be retrieved and must be regenerated if the core device is rebooted.
|
||||
|
||||
\subsection{Dataset manipulation with core device cache}
|
||||
Experiments may require values computed or found in previously executed kernels. To avoid invoking an RPC or sacrificing the pre-computation in \texttt{prepare()} stage, data can be stored in the core device cache.
|
||||
|
||||
The following code snippets describe two experiments, in which the data from the first experiment is cached. The data is then retrieved and printed in hexadecimal form in the second experiment.
|
||||
|
||||
\inputcolorboxminted{firstline=9,lastline=16}{examples/cache.py}
|
||||
\inputcolorboxminted{firstline=24,lastline=35}{examples/cache.py}
|
||||
|
||||
Similar to DMA, cached data is no longer retrievable once the core device has been rebooted.
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user