Compare commits
No commits in common. "480e8b29665092f5a20d03df4e2ec789cfde97a7" and "4bc2d4ee6d84794d8156ddc46e75011eec6add07" have entirely different histories.
480e8b2966
...
4bc2d4ee6d
5
1124.tex
5
1124.tex
|
|
@ -277,7 +277,10 @@ Kasli 2.0 supplies three user LEDs for debugging purposes. Two are located on th
|
|||
|
||||
\newpage
|
||||
|
||||
\codesection{Kasli 2.0 1124 carrier}
|
||||
\section{Example ARTIQ Code}
|
||||
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources on the Kasli 2.0 1124 carrier board. They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
|
||||
The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material on the functions and structures used here.
|
||||
|
||||
\subsection{Direct Memory Access (DMA)}
|
||||
Instead of directly emitting RTIO events, sequences of RTIO events can be recorded in advance and stored in the local SDRAM. The event sequence can then be replayed at a specified timestamp. This is of special advantage in cases where RTIO events are too closely placed to be generated as they are executed, as events can be replayed at a higher speed than the on-FPGA CPU alone is capable of.
|
||||
|
|
|
|||
274
2118-2128.tex
274
2118-2128.tex
|
|
@ -1,5 +1,5 @@
|
|||
\input{preamble.tex}
|
||||
\graphicspath{{images/2118-2128}{images}}
|
||||
\include{preamble.tex}
|
||||
\graphicspath{{images}}
|
||||
|
||||
\title{2118 BNC-TTL / 2128 SMA-TTL}
|
||||
\author{M-Labs Limited}
|
||||
|
|
@ -13,30 +13,31 @@
|
|||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{8 TTL channels}
|
||||
\item{Input- and output-capable}
|
||||
\item{Galvanically isolated}
|
||||
\item{3ns minimum pulse width}
|
||||
\item{BNC or SMA connectors}
|
||||
\item{8 channels.}
|
||||
\item{Input and output capable.}
|
||||
\item{Galvanically isolated.}
|
||||
\item{3ns minimum pulse width.}
|
||||
\item{BNC or SMA connectors.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Photon counting.}
|
||||
\item{External equipment trigger.}
|
||||
\item{Optical shutter control.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 2118 BNC-TTL card is a 8hp EEM module, while the 2128 SMA-TTL card is a 4hp EEM module.
|
||||
Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
||||
|
||||
Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely.
|
||||
|
||||
Both cards are capable of a minimum pulse width of 3ns.
|
||||
Each card provides two banks of four digital channels each, with BNC (2118) or SMA (2128) connectors.
|
||||
Each bank has individual ground isolation.
|
||||
The direction (input or output) of each bank can be selected using DIP switches.
|
||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
|
||||
Outputs tolerate short circuits indefinitely.
|
||||
The card support a minimum pulse width of 3ns.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
|
@ -88,6 +89,8 @@ Both cards are capable of a minimum pulse width of 3ns.
|
|||
\draw (0,0) circle(0.8);
|
||||
\end{scope}
|
||||
|
||||
|
||||
|
||||
\draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus1) {};
|
||||
|
||||
\draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso1) {};
|
||||
|
|
@ -294,41 +297,47 @@ Both cards are capable of a minimum pulse width of 3ns.
|
|||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=1.8in]{photo2118-2128.jpg }
|
||||
\caption{BNC-TTL and SMA-TTL cards}%
|
||||
\includegraphics[angle=90, height=0.7in]{DIO_BNC_FP.jpg}
|
||||
\includegraphics[angle=90, height=0.4in]{DIO_SMA_FP.jpg}
|
||||
\caption{BNC-TTL and SMA-TTL front panels}%
|
||||
\subfloat[\centering BNC-TTL]{{
|
||||
\includegraphics[height=1.8in]{2118-2128/DIO_BNC_FP.jpg}
|
||||
\includegraphics[height=1.8in]{2118-2128/photo2118.jpg}
|
||||
}}%
|
||||
\subfloat[\centering SMA-TTL]{{
|
||||
\includegraphics[height=1.8in]{2118-2128/DIO_SMA_FP.jpg}
|
||||
\includegraphics[height=1.8in]{2118-2128/photo2128.jpg}
|
||||
}}%
|
||||
\caption{BNC-TTL/SMA-TTL Card photos}%
|
||||
\label{fig:example}%
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesectiond{2118 BNC-TTL}{2128 SMA-TTL}{https://github.com/sinara-hw/DIO_BNC}{https://github.com/sinara-hw/DIO_SMA}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
|
||||
Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
|
||||
Specifications are based on the bus transceivers IC (SN74BCT25245DW\footnote{\label{transceiver}https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf})
|
||||
and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}).
|
||||
The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}https://github.com/sinara-hw/sinara/issues/187}.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
|
||||
High-level input voltage\repeatfootnote{transceiver} & $V_{IH}$ & 2 & & 5.5* & V & \\
|
||||
\hline
|
||||
Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
|
||||
Low-level input voltage\repeatfootnote{transceiver} & $V_{IL}$ & -0.5 & & 0.8 & V & \\
|
||||
\hline
|
||||
Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
|
||||
Input clamp current\repeatfootnote{transceiver} & $I_{OH}$ & & & -18 & mA & termination disabled \\
|
||||
\hline
|
||||
High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
|
||||
High-level output current\repeatfootnote{transceiver} & $I_{OH}$ & & & -160 & mA & \\
|
||||
\hline
|
||||
Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
|
||||
Low-level output current\repeatfootnote{transceiver} & $I_{OL}$ & & & 376 & mA & \\
|
||||
\thickhline
|
||||
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
|
@ -336,69 +345,185 @@ Specifications were derived based on the datasheets of the bus transceiver IC (S
|
|||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
High-level output voltage\repeatfootnote{transceiver} & 2 & & & V & $I_{OH}$=-160mA \\
|
||||
& 2.7 & & & V & $I_{OH}$=-6mA \\
|
||||
High-level output voltage\repeatfootnote{transceiver} & $V_{OH}$ & 2 & & & V & $I_{OH}$=-160mA \\
|
||||
& & 2.7 & & & V & $I_{OH}$=-6mA \\
|
||||
\hline
|
||||
Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
|
||||
& & & 0.7 & V & $I_{OL}$=376mA \\
|
||||
Low-level output voltage\repeatfootnote{transceiver} & $V_{OL}$ & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
|
||||
& & & & 0.7 & V & $I_{OL}$=376mA \\
|
||||
\hline
|
||||
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
|
||||
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & & 3 & 5 & ns & \\
|
||||
\hline
|
||||
Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns & \\
|
||||
Pulse width distortion\repeatfootnote{isolator} & $PWD$ & & 0.2 & 4.5 & ns & \\
|
||||
\hline
|
||||
Peak jitter\repeatfootnote{isolator} & & 350 & & ps & \\
|
||||
Peak jitter\repeatfootnote{isolator} & $T_{JIT(PK)}$ & & 350 & & ps & \\
|
||||
\hline
|
||||
Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
|
||||
Data rate\repeatfootnote{isolator} & & 0 & & 150 & Mbps & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
|
||||
\newpage
|
||||
|
||||
\begin{figure}[ht]
|
||||
Minimum pulse width was measured\repeatfootnote{sinara187}.
|
||||
Pulses were generated from a DDS generator as an input of a BNC-TTL card.
|
||||
The input BNC-TTL card is connected to another BNC-TTL card as an output.
|
||||
The output signal is measured and shown.
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
|
||||
\includegraphics[height=3in]{2118-2128/bnc_ttl_min_pulse_width.png}
|
||||
\caption{Minimum pulse width required for BNC-TTL card}
|
||||
\label{fig:pulsewidth}
|
||||
\end{figure}
|
||||
|
||||
The red trace refers to the input pulses from the DDS generator, while the blue trace is the measured signal from the output BNC-TTL card.
|
||||
Note that the first input (red) pulse could not propagate through the signal chain.
|
||||
The first output (blue) pulse is the result of the second input (red, 3ns width) pulse.
|
||||
|
||||
\newpage
|
||||
|
||||
The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly.
|
||||
\section{Front Panel Drawings}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.8in]{2118-2128/bnc_ttl_drawings.pdf}
|
||||
\captionof{figure}{2118 BNC-TTL front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=2.8in]{2118-2128/bnc_ttl_assembly.pdf}
|
||||
\captionof{figure}{2118 BNC-TTL front panel assembly}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (2118 Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90560220 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
|
||||
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (2118 Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90457987 & 4 & CSCR M2.5*12.3 PAN PHL SS \\ \hline
|
||||
2 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
3 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
4 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
5 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
|
||||
6 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
|
||||
7 & 3207076 & 0.01 & SCR M2.5*16 PAN 100 21101-222 \\ \hline
|
||||
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
|
||||
9 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
|
||||
10 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT(100PCS) \\ \hline
|
||||
11 & 90560220 & 1 & FP-LYKJ 3U8HP PANEL \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=3in]{2118-2128/sma_ttl_drawings.pdf}
|
||||
\captionof{figure}{2128 SMA-TTL front panel drawings}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=3in]{2118-2128/sma_ttl_assembly.pdf}
|
||||
\captionof{figure}{2128 SMA-TTL front panel assembly}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\begin{multicols}{2}
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (2128 Standalone)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90531967 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
|
||||
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
|
||||
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\columnbreak
|
||||
|
||||
\begin{center}
|
||||
\captionof{table}{Bill of Material (2128 Assembled)}
|
||||
\tiny
|
||||
\begin{tabular}{|c|c|c|c|}
|
||||
\hline
|
||||
Index & Part No. & Qty & Description \\ \hline
|
||||
1 & 90531967 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
|
||||
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
|
||||
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
|
||||
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
|
||||
5 & 3001012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
|
||||
6 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
|
||||
7 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
|
||||
8 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
|
||||
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
\end{multicols}
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
The termination and IO direction can be configured by switches.
|
||||
The per-channel termination and per-bank IO direction switches are found at the middle-left and middle-right of both cards respectively.
|
||||
|
||||
IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank.
|
||||
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
|
||||
|
||||
IO direction switches partly decides the IO direction of each bank.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\item Closed switch (ON) \\
|
||||
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item Opened switch (OFF) \\
|
||||
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\subfloat[\centering BNC-TTL]{{
|
||||
\includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
|
||||
\includegraphics[height=1.5in]{2118-2128/bnc_ttl_switches.jpg}
|
||||
}}%
|
||||
\subfloat[\centering SMA-TTL]{{
|
||||
\includegraphics[height=1.5in]{sma_ttl_switches.jpg}
|
||||
\includegraphics[height=1.5in]{2118-2128/sma_ttl_switches.jpg}
|
||||
}}%
|
||||
\caption{Position of switches}%
|
||||
\end{figure}
|
||||
|
||||
\newpage
|
||||
\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 2118 BNC-TTL/2128 SMA-TTL card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
|
|
@ -410,13 +535,15 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
|
|||
|
||||
\newpage
|
||||
\subsection{Sub-coarse-RTIO-cycle pulse}
|
||||
With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
|
||||
With the use of the ARTIQ RTIO, only 1 event can be enqueued per coarse RTIO cycle, which is typically 8ns.
|
||||
Therefore, to emit a pulse that is less than 8ns, additional delay is needed such that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted at different coarse RTIO cycles.
|
||||
The TTL pulse must satisfy the minimum pulse width stated in the electircal specifications.
|
||||
|
||||
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
|
||||
|
||||
\subsection{Edge counting in a 1ms window}
|
||||
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
|
||||
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
|
||||
The channel should be configured as input in both the gateware and hardware. Invoke one of the 3 methods to start edge detection.
|
||||
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
|
||||
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
|
||||
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
|
||||
|
|
@ -424,34 +551,41 @@ The detected edges are registered to the RTIO input FIFO. By default, the FIFO c
|
|||
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
|
||||
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
|
||||
|
||||
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
|
||||
The RTIO system can report at most 1 edge detection event for every coarse RTIO cycle.
|
||||
For example, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is 1 coarse RTIO cycle (typically 8 ns) with consideration of the RTIO specification alone.
|
||||
However, both the electircal specifications and the possibility of triggering \texttt{RTIOOverflow} should be considered.
|
||||
|
||||
\newpage
|
||||
\subsection{Edge counting using \texttt{EdgeCounter}}
|
||||
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
This example code uses the gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
|
||||
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
|
||||
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
|
||||
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle.
|
||||
Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
|
||||
|
||||
\subsection{Responding to an external trigger}
|
||||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
|
||||
|
||||
\subsection{62.5 MHz clock signal generation}
|
||||
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
|
||||
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal.
|
||||
Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle.
|
||||
Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2. \\
|
||||
|
||||
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
|
||||
|
||||
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
\subsection{Minimum sustained event separation}
|
||||
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
|
||||
\subsection{Minimum Sustained Event Separation}
|
||||
The minimum sustained event separation is the least amount of time separation between input gated events, in which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions.
|
||||
The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
|
||||
|
||||
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
|
||||
|
||||
\begin{center}
|
||||
\begin{table}[H]
|
||||
\captionof{table}{Minimum sustained event separation of different carriers}
|
||||
\captionof{table}{Minimum sustained event separation of different carrier}
|
||||
\centering
|
||||
\begin{tabular}{|c|c|c|}
|
||||
\hline
|
||||
|
|
@ -461,8 +595,12 @@ The minimum sustained event separation is the least time separation between inpu
|
|||
\end{table}
|
||||
\end{center}
|
||||
|
||||
\ordersection{2118 BNC-TTL/2128 SMA-TTL}
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\finalfootnote
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\input{footnote.tex}
|
||||
|
||||
\end{document}
|
||||
|
|
|
|||
114
2238.tex
114
2238.tex
|
|
@ -1,6 +1,5 @@
|
|||
\input{preamble.tex}
|
||||
\include{preamble.tex}
|
||||
\graphicspath{{images/2238}{images}}
|
||||
|
||||
\title{2238 MCX-TTL}
|
||||
\author{M-Labs Limited}
|
||||
\date{January 2022}
|
||||
|
|
@ -13,28 +12,31 @@
|
|||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{16 MCX-TTL channels}
|
||||
\item{Input and output capable}
|
||||
\item{No galvanic isolation}
|
||||
\item{High speed and low jitter}
|
||||
\item{MCX connectors}
|
||||
\item{16 channels.}
|
||||
\item{Input and output capable.}
|
||||
\item{No galvanic isolation.}
|
||||
\item{High speed and low jitter.}
|
||||
\item{MCX connectors.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Photon counting.}
|
||||
\item{External equipment trigger.}
|
||||
\item{Optical shutter control.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 2238 MCX-TTL card is a 4hp EEM module.
|
||||
It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
|
||||
|
||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||
Each card provides four banks of four digital channels each, with MCX connectors, controlled through 2 EEM connectors.
|
||||
Each EEM connector controls two banks independently.
|
||||
Single EEM operation is possible.
|
||||
The direction (input or output) of each bank can be selected using DIP switches.
|
||||
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
|
||||
This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
|
@ -437,66 +439,65 @@ Each channel supports 50\textOmega~terminations individually controllable using
|
|||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[height=1.8in]{DIO_MCX_FP.pdf}
|
||||
\includegraphics[height=2in]{photo2238.jpg}
|
||||
\caption{MCX-TTL card}
|
||||
\includegraphics[angle=90, height=0.6in]{DIO_MCX_FP.pdf}
|
||||
\caption{MCX-TTL front panel}
|
||||
\caption{MCX-TTL Card photo}
|
||||
\end{figure}
|
||||
|
||||
% For wide tables, a single column layout is better. It can be switched
|
||||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{2238 MCX-TTL}{https://github.com/sinara-hw/DIO_MCX/wiki}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
|
||||
Both recommended operating conditions and electrical characteristics are based on the datasheet of the bus transceivers IC (74LVT162245MTD\footnote{\label{transceiver}https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}).
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Recommended Operating Conditions}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input voltage & 0 & & 5.5* & V \\
|
||||
Input voltage & $V_{I}$ & 0 & & 5.5* & V \\
|
||||
\hline
|
||||
High-level output current & & & -24 & mA \\
|
||||
High-level output current & $I_{OH}$ & & & -24 & mA \\
|
||||
\hline
|
||||
Low-level output current & & & 24 & mA \\
|
||||
Low-level output current & $I_{OL}$ & & & 24 & mA \\
|
||||
\hline
|
||||
Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
|
||||
Input edge rate & $\frac{\Delta t}{\Delta V}$ & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
|
||||
\thickhline
|
||||
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
|
||||
All specifications are in the recommended operating temperature range unless otherwise noted.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{Electrical Characteristics}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
|
||||
Input clamp diode voltage & $V_{IK}$ & & & -1.2 & V & $I_I =-36 mA$ \\
|
||||
\hline
|
||||
Input high voltage & 2.0 & & & V & \\
|
||||
Input high voltage & $V_{IH}$ & 2.0 & & & V & \\
|
||||
\hline
|
||||
Input low voltage & & & 0.8 & V & \\
|
||||
Input low voltage & $V_{IL}$ & & & 0.8 & V & \\
|
||||
\hline
|
||||
Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
|
||||
& 3.1 & & & V & $I_{OH}=-200\mu A$ \\
|
||||
Output high voltage & $V_{OH}$ & 2.0 & & & V & $I_{OH}=-24mA$ \\
|
||||
& & 3.1 & & & V & $I_{OH}=-200\mu A$ \\
|
||||
\hline
|
||||
Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
|
||||
& & & 0.2 & V & $I_{OL}=-200\mu A$ \\
|
||||
Output low voltage & $V_{OL}$ & & & 0.8 & V & $I_{OL}=-24mA$ \\
|
||||
& & & & 0.2 & V & $I_{OL}=-200\mu A$ \\
|
||||
\hline
|
||||
Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
|
||||
& & & 2 & \textmu A & $V_I=3.3V$ \\
|
||||
& & & -10 & \textmu A & $V_I=0V$ \\
|
||||
Input current & $I_I$ & & & 20 & \textmu A & $V_I=5.5V$ \\
|
||||
& & & & 2 & \textmu A & $V_I=3.3V$ \\
|
||||
& & & & -10 & \textmu A & $V_I=0V$ \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
|
|
@ -505,16 +506,18 @@ All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherw
|
|||
\newpage
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
|
||||
The termination and IO direction can be configured by switches.
|
||||
The per-channel termination and per-bank IO direction switches are found at the top and middle of the card respectively.
|
||||
\begin{multicols}{2}
|
||||
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
|
||||
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
|
||||
|
||||
IO direction switches partly decides the IO direction of each bank.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\item Closed switch (ON) \\
|
||||
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item Opened switch (OFF) \\
|
||||
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
|
|
@ -525,9 +528,12 @@ Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note th
|
|||
\end{multicols}
|
||||
|
||||
\newpage
|
||||
\codesection{2238 MCX-TTL card}
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
|
|
@ -538,8 +544,8 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
|
|||
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
|
||||
|
||||
\newpage
|
||||
\subsection{Edge counting in an 1ms window}
|
||||
The channel should be configured as input in both gateware and hardware.
|
||||
\subsection{Counting rising edges in a 1ms window}
|
||||
The channel should be configured as input in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
|
|
@ -550,8 +556,12 @@ If the gateware counter is enabled on the TTL channel, it can typically count up
|
|||
One channel needs to be configured as input, and the other as output.
|
||||
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
|
||||
|
||||
\ordersection{2238 MCX-TTL}
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 2238 MCX-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\finalfootnote
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\input{footnote.tex}
|
||||
|
||||
\end{document}
|
||||
|
|
|
|||
154
2245.tex
154
2245.tex
|
|
@ -1,4 +1,4 @@
|
|||
\input{preamble.tex}
|
||||
\include{preamble.tex}
|
||||
\graphicspath{{images/2245}{images}}
|
||||
|
||||
\usepackage{tikz-timing}
|
||||
|
|
@ -16,28 +16,35 @@
|
|||
\section{Features}
|
||||
|
||||
\begin{itemize}
|
||||
\item{16 LVDS-TTL channels.}
|
||||
\item{Input- and output-capable}
|
||||
\item{No galvanic isolation}
|
||||
\item{High speed and low jitter}
|
||||
\item{RJ45 connectors}
|
||||
\item{16 LVDS channels.}
|
||||
\item{Input and output capable.}
|
||||
\item{No galvanic isolation.}
|
||||
\item{High speed and low jitter.}
|
||||
\item{RJ45 connectors.}
|
||||
\end{itemize}
|
||||
|
||||
\section{Applications}
|
||||
|
||||
\begin{itemize}
|
||||
\item{Photon counting}
|
||||
\item{External equipment trigger}
|
||||
\item{Optical shutter control}
|
||||
\item{Serial communication with remote devices}
|
||||
\item{Photon counting.}
|
||||
\item{External equipment trigger.}
|
||||
\item{Optical shutter control.}
|
||||
\item{Serial communication to remote devices.}
|
||||
\end{itemize}
|
||||
|
||||
\section{General Description}
|
||||
The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
The 2245 LVDS-TTL card is a 4hp EEM module.
|
||||
It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
||||
|
||||
Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
|
||||
Each card provides sixteen digital channels each, controlled through 2 EEM connectors.
|
||||
Each EEM connector controls eight channels independently.
|
||||
Single EEM operation is possible.
|
||||
Each RJ45 connector exposes four digital channels in the LVDS format.
|
||||
The direction (input or output) of each channel can be selected using DIP switches.
|
||||
Outputs are intended to drive 100\textOmega~loads, inputs are 100\textOmega~terminated.
|
||||
This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
|
||||
Only shielded Ethernet Cat-6 cables should be connected.
|
||||
|
||||
Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
|
||||
|
||||
% Switch to next column
|
||||
\vfill\break
|
||||
|
|
@ -296,9 +303,9 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
|
|||
|
||||
\begin{figure}[hbt!]
|
||||
\centering
|
||||
\includegraphics[angle=90, height=1.7in]{photo2245.jpg}
|
||||
\includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
|
||||
\caption{LVDS-TTL card and front panel}
|
||||
\includegraphics[height=2.1in]{DIO_RJ45_FP.pdf}
|
||||
\includegraphics[height=2.1in]{photo2245.jpg}
|
||||
\caption{LVDS-TTL Card photo}
|
||||
\end{figure}
|
||||
|
||||
|
||||
|
|
@ -306,11 +313,9 @@ Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~t
|
|||
% page-by-page.
|
||||
\onecolumn
|
||||
|
||||
\sourcesection{2245 LVDS-TTL}{https://github.com/sinara-hw/DIO_LVDS_RJ45/wiki}
|
||||
|
||||
\section{Electrical Specifications}
|
||||
|
||||
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
|
||||
Information in this section is based on the datasheet of the repeaters IC (FIN1101K8X\footnote{\label{repeaters}https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}).
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
|
|
@ -331,7 +336,9 @@ All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherw
|
|||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
|
||||
|
||||
All specifications are in the recommended operating temperature range unless otherwise noted.
|
||||
All typical values of DC specifications are at $T_A = 25\degree C$.
|
||||
|
||||
\begin{table}[h]
|
||||
|
|
@ -342,7 +349,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
|
|||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
|
||||
Output differentiual Voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
|
||||
\cline{0-5}
|
||||
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
|
||||
\cline{0-5}
|
||||
|
|
@ -352,35 +359,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
|
|||
\hline
|
||||
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
|
||||
\hline
|
||||
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{AC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
|
||||
(20\% to 80\%) & & & & & \\
|
||||
\cline{0-5}
|
||||
Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
|
||||
(80\% to 20\%) & & & & & \\
|
||||
\cline{0-5}
|
||||
Pulse width distortion & & 0.01 & 0.2 & ns & \\
|
||||
\hline
|
||||
LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
|
||||
deterministic & & & & & 800 Mbps\\
|
||||
\hline
|
||||
LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
|
||||
random (RMS) & & & & & \\
|
||||
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended Input Voltage \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
|
|
@ -388,18 +367,46 @@ All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 30
|
|||
|
||||
\newpage
|
||||
|
||||
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise specified.
|
||||
|
||||
\begin{table}[h]
|
||||
\begin{threeparttable}
|
||||
\caption{AC Specifications}
|
||||
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
|
||||
\thickhline
|
||||
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
||||
\textbf{Unit} & \textbf{Conditions} \\
|
||||
\hline
|
||||
Differential Output Rise Time & \multirow{2}{*}{$t_{TLHD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & duty Cycle = 50\%.\\
|
||||
(20\% to 80\%) & & & & & & \\
|
||||
\cline{0-5}
|
||||
Differential Output Fall Time & \multirow{2}{*}{$t_{THLD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
|
||||
(80\% to 20\%) & & & & & & \\
|
||||
\cline{0-5}
|
||||
Pulse width distortion & $PWD$ & & 0.01 & 0.2 & ns & \\
|
||||
\hline
|
||||
LVDS data jitter, & \multirow{2}{*}{$t_{DJ}$} & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
|
||||
deterministic & & & & & & 800 Mbps\\
|
||||
\hline
|
||||
LVDS clock jitter, & \multirow{2}{*}{$t_{RJ}$} & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
|
||||
random (RMS) & & & & & & \\
|
||||
\thickhline
|
||||
\end{tabularx}
|
||||
\end{threeparttable}
|
||||
\end{table}
|
||||
|
||||
\section{Configuring IO Direction \& Termination}
|
||||
The IO direction can be configured by switches, which are found at the top of the card.
|
||||
\begin{multicols}{2}
|
||||
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
|
||||
IO direction switches partly decides the IO direction of each bank.
|
||||
\begin{itemize}
|
||||
\itemsep0em
|
||||
\item IO direction switch closed (\texttt{ON}) \\
|
||||
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item IO direction switch open (OFF) \\
|
||||
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
|
||||
\item Closed switch (ON) \\
|
||||
Fix the corresponding channel to output. The direction cannot be changed by I\textsuperscript{2}C.
|
||||
\item Opened switch (OFF) \\
|
||||
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
|
||||
\end{itemize}
|
||||
|
||||
\vspace*{\fill}\columnbreak
|
||||
\columnbreak
|
||||
\begin{center}
|
||||
\centering
|
||||
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
|
||||
|
|
@ -409,12 +416,15 @@ The IO direction of each channel can be configured by DIP switches, which are fo
|
|||
|
||||
\newpage
|
||||
|
||||
\codesection{2245 LVDS-TTL card}
|
||||
\section{Example ARTIQ code}
|
||||
The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
|
||||
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||||
|
||||
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
|
||||
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
|
||||
|
||||
\subsection{One pulse per second}
|
||||
The channel should be configured as output in both gateware and hardware.
|
||||
The channel should be configured as output in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
|
||||
|
||||
\subsection{Morse code}
|
||||
|
|
@ -423,7 +433,7 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
|
|||
|
||||
\newpage
|
||||
\subsection{Counting rising edges in a 1ms window}
|
||||
The channel should be configured as input in both gateware and hardware.
|
||||
The channel should be configured as input in both the gateware and hardware.
|
||||
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
|
||||
|
||||
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
|
||||
|
|
@ -449,7 +459,8 @@ One channel needs to be configured as input, and the other as output.
|
|||
|
||||
\newpage
|
||||
\subsection{SPI Master Device}
|
||||
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
|
||||
If a EEM port is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices.
|
||||
Invocation of an SPI transfer follows this pattern:
|
||||
\begin{enumerate}
|
||||
% The config register can be set using set_config.
|
||||
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
|
||||
|
|
@ -482,7 +493,7 @@ The list of configurations supported in the gateware are listed as below:
|
|||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves.
|
||||
The following ARTIQ example demonstrates the flow of an SPI transcation with a typical SPI setup with 3 homogeneous slaves.
|
||||
The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
|
||||
\begin{center}
|
||||
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
|
||||
|
|
@ -566,11 +577,14 @@ The baseline configuration for an \texttt{SPIMaster} instance can be defined as
|
|||
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
|
||||
|
||||
\subsubsection{SPI frequency}
|
||||
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
|
||||
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor from [2, 257].
|
||||
In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
|
||||
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
|
||||
|
||||
\subsubsection{SPI write}
|
||||
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
|
||||
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves.
|
||||
Suppose the instruction and data are 8 bits and 32 bits respectively.
|
||||
The timing diagram of such write operation is shown in the following.
|
||||
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
|
|
@ -591,11 +605,11 @@ Typically, an SPI write operation involves sending an instruction and data to th
|
|||
\end{center}
|
||||
|
||||
\newpage
|
||||
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
|
||||
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transcation can be performed by the following code.
|
||||
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
|
||||
|
||||
\subsubsection{SPI read}
|
||||
A 32-bit read is represented by the following timing diagram:
|
||||
A 32-bits read is represented by the following timing diagram.
|
||||
|
||||
\begin{center}
|
||||
\begin{tikztimingtable}
|
||||
|
|
@ -620,8 +634,12 @@ Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This S
|
|||
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
|
||||
|
||||
\newpage
|
||||
\ordersection{2245 LVDS-TTL}
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and select the 2245 LVDS-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||||
|
||||
\finalfootnote
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
||||
\input{footnote.tex}
|
||||
|
||||
\end{document}
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
Before Width: | Height: | Size: 208 KiB After Width: | Height: | Size: 80 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 360 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 81 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 82 KiB |
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
Before Width: | Height: | Size: 226 KiB After Width: | Height: | Size: 82 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 108 KiB After Width: | Height: | Size: 81 KiB |
13
preamble.tex
13
preamble.tex
|
|
@ -37,24 +37,11 @@
|
|||
#1, like all the Sinara hardware family, is open-source hardware, and design files (schematics, PCB layouts, BOMs) can be found in detail at the repository \url{#2}.
|
||||
}
|
||||
|
||||
\newcommand*{\sourcesectiond}[4]{
|
||||
\section{Source}
|
||||
#1 and #2, like all the Sinara hardware family, are open-source hardware, and design files (schematics, PCB layouts,
|
||||
BOMs) can be found in detail at the repositories \url{#3} and \url{#4}.
|
||||
}
|
||||
|
||||
\newcommand*{\ordersection}[1]{
|
||||
\section{Ordering Information}
|
||||
To order, please visit \url{https://m-labs.hk} and choose #1 in the ARTIQ/Sinara hardware selection tool. Cards can be ordered as part of a fully-featured ARTIQ/Sinara crate or standalone through the 'Spare cards' option. Otherwise, orders can also be made by writing directly to \url{mailto:sales@m-labs.hk}.
|
||||
}
|
||||
|
||||
\newcommand{\codesection}[1] {
|
||||
\section{Example ARTIQ Code}
|
||||
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources of the #1. They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||||
|
||||
The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
|
||||
}
|
||||
|
||||
\newcommand*{\finalfootnote}{
|
||||
\section*{}
|
||||
\vspace*{\fill}
|
||||
|
|
|
|||
Loading…
Reference in New Issue