From ebc1235847116d1ad1c108ce686ef942eb4dcf6d Mon Sep 17 00:00:00 2001 From: occheung Date: Thu, 11 Aug 2022 10:48:50 +0800 Subject: [PATCH] 1124: add insn for clock configuation setup --- 1124.tex | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/1124.tex b/1124.tex index 57a3a27..a77e515 100644 --- a/1124.tex +++ b/1124.tex @@ -273,6 +273,12 @@ Kasli 2.0 supports a set of clock systhesizing options for the (D)RTIO system: Alternatively, the clock synthesizer can be bypassed using the \texttt{ext0\char`_bypass} clocking option, where the RTIO clock is directly supplied to the SMA connector. The resulting clock signal is then routed to both the RTIO system and downstream DRTIO satellites. +Clocking options should be configured by setting the value of the \texttt{rtio} key to the desired configuration through \texttt{artiq\char`_coremgmt}. +For example, the RTIO frequency is synthesized from the external 10 MHz from the SMA connector after issuing the following command. +\begin{minted}{bash} + artiq_coremgmt config write -s rtio ext0_synth0_10to125 +\end{minted} + \subsection{DRTIO Satellite} The RTIO clock is first recovered from the SFP transceiver connected to the upstream device. The signal is then cleaned by Si5324 clock synthesizer. The resulting clock signal is then routed to the RTIO system and downstream DRTIO satellties.