From e109ec2b6f80ebce2eca16d87d6fa4035a92cb20 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Mon, 6 Dec 2021 13:03:59 +0800
Subject: [PATCH] 4410-4412: fix performance data condition

The condition should now align with wiki and sinara issue 354 / urukul issue 3.
---
 4410-4412.tex | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/4410-4412.tex b/4410-4412.tex
index 63bc1ea..b0a2696 100644
--- a/4410-4412.tex
+++ b/4410-4412.tex
@@ -357,7 +357,13 @@ RF switches (1ns temporal resolution) on each channel provides 70 dB isolation.
 
 \newpage
 
-All performance data are produced using 1 GHz PLL unless otherwise noted.
+All performance data are produced using the following setup unless otherwise noted.
+\begin{itemize}
+    \item 100 MHz input clock into SMA, 10 dBm.
+    \item Input clock divided by 4.
+    \item PLL with x40 multiplier.
+    \item Output frequency at 80 MHz or 81 MHz.
+\end{itemize}
 
 \begin{table}[h]
 \begin{threeparttable}