From c1c078671b24b2ecee3a50ffba80fe7330e25da9 Mon Sep 17 00:00:00 2001 From: occheung Date: Thu, 16 Jun 2022 16:00:22 +0800 Subject: [PATCH] examples: move SPI examples to spi.py --- 2245.tex | 8 ++++---- examples/spi.py | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ examples/ttl.py | 47 ----------------------------------------------- 3 files changed, 53 insertions(+), 51 deletions(-) create mode 100644 examples/spi.py diff --git a/2245.tex b/2245.tex index e4ac475..5aa7e22 100644 --- a/2245.tex +++ b/2245.tex @@ -621,13 +621,13 @@ The following examples will assume the SPI communication has the following prope \item Full duplex \end{itemize} The base line configuration for an \texttt{SPIMaster} instance can be defined as such: -\inputcolorboxminted[0]{firstline=105,lastline=110}{examples/ttl.py} +\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py} The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example. \subsubsection{SPI frequency} Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor from [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125. -\inputcolorboxminted[0]{firstline=112,lastline=112}{examples/ttl.py} +\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py} \subsubsection{SPI write} Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. @@ -654,7 +654,7 @@ The timing diagram of such write operation is shown in the following. \newpage Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transcation can be performed by the following code. -\inputcolorboxminted{firstline=119,lastline=128}{examples/ttl.py} +\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py} \subsubsection{SPI read} A 32-bits read is represented by the following timing diagram. @@ -679,7 +679,7 @@ A 32-bits read is represented by the following timing diagram. \end{center} Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code. -\inputcolorboxminted{firstline=136,lastline=150}{examples/ttl.py} +\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py} \newpage \section{Ordering Information} diff --git a/examples/spi.py b/examples/spi.py new file mode 100644 index 0000000..3139e04 --- /dev/null +++ b/examples/spi.py @@ -0,0 +1,49 @@ +from artiq.experiment import * +from artiq.coredevice import spi2 as spi + + +SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END | + 0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY | + 0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE | + 0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX) + +CLK_DIV = 125 + + +class SPIWrite(EnvExperiment): + def build(self): + self.setattr_device("core") + self.spi = self.get_device("dio_spi0") + + @kernel + def run(self): + self.core.reset() + self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110) + self.spi.write(0x13 << 24) # Shift the bits to the MSBs. + # Since SPI_LSB_FIRST is NOT set, + # SPI Machine will shift out bits from + # the MSB of the `data` register.` + self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110) + self.spi.write(0xDEADBEEF) + + +class SPIRead(EnvExperiment): + def build(self): + self.setattr_device("core") + self.spi = self.get_device("dio_spi0") + + @kernel + def run(self): + self.core.reset() + self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001) + self.spi.write(0x81 << 24) # Shift the bits to the MSBs. + # Since SPI_LSB_FIRST is NOT set, + # SPI Machine will shift out bits from + # the MSB of the `data` register.` + self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, + 32, CLK_DIV, 0b001) + self.spi.write(0) # write() performs the SPI transfer. + # As suggested by the timing diagram, + # the exact value of this argument + # does not matter. + print(self.spi.read()) diff --git a/examples/ttl.py b/examples/ttl.py index aba0f04..c86ad50 100644 --- a/examples/ttl.py +++ b/examples/ttl.py @@ -101,50 +101,3 @@ class ClockGen(EnvExperiment): def run(self): self.core.reset() self.ttl0.set(62.5*MHz) - -from artiq.coredevice import spi2 as spi - -SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END | - 0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY | - 0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE | - 0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX) - -CLK_DIV = 125 - -class SPIWrite(EnvExperiment): - def build(self): - self.setattr_device("core") - self.spi = self.get_device("dio_spi0") - - @kernel - def run(self): - self.core.reset() - self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110) - self.spi.write(0x13 << 24) # Shift the bits to the MSBs. - # Since SPI_LSB_FIRST is NOT set, - # SPI Machine will shift out bits from - # the MSB of the `data` register.` - self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110) - self.spi.write(0xDEADBEEF) - - -class SPIRead(EnvExperiment): - def build(self): - self.setattr_device("core") - self.spi = self.get_device("dio_spi0") - - @kernel - def run(self): - self.core.reset() - self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001) - self.spi.write(0x81 << 24) # Shift the bits to the MSBs. - # Since SPI_LSB_FIRST is NOT set, - # SPI Machine will shift out bits from - # the MSB of the `data` register.` - self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, - 32, CLK_DIV, 0b001) - self.spi.write(0) # write() performs the SPI transfer. - # As suggested by the timing diagram, - # the exact value of this argument - # does not matter. - print(self.spi.read())