From b42fbc9b761420528c00b73dff94ea6bf39c9768 Mon Sep 17 00:00:00 2001 From: architeuthis Date: Fri, 24 Jan 2025 15:32:16 +0100 Subject: [PATCH] ttls: add sysdesc section --- 2118-2128.tex | 31 +++++++++++++++++---- 2238.tex | 30 ++++++++++++++++++++ 2245.tex | 76 +++++++++++++++++++++++++++++++++++++++------------ 3 files changed, 114 insertions(+), 23 deletions(-) diff --git a/2118-2128.tex b/2118-2128.tex index eca349b..c208863 100644 --- a/2118-2128.tex +++ b/2118-2128.tex @@ -370,11 +370,11 @@ \newpage - The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly. + The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly. \section{Configuring IO Direction \& Termination} - IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank. + IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank. \begin{itemize} \itemsep0em @@ -395,7 +395,24 @@ \caption{Position of switches}% \end{figure} -\newpage +\sysdescsection + + 2118 BNC-TTL and 2128 SMA-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format: + + \begin{tcolorbox}[colback=white] + \begin{minted}{json} + "name" : { + "type": "dio", + "board": "DIO_BNC", // or "DIO_SMA", optional + "ports": [0], + "edge_counter": true, // optional + "bank_direction_low": "input", // or "output" + "bank_direction_high": "output" // or "input" + } + \end{minted} + \end{tcolorbox} + + Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. \codesection{2118 BNC-TTL/2128 SMA-TTL cards} @@ -405,21 +422,23 @@ The channel should be configured as output in both the gateware and hardware. \inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py} +\newpage + \subsection{Morse code} This example demonstrates some basic algorithmic features of the ARTIQ-Python language. \inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py} -\newpage - \subsection{Sub-coarse-RTIO-cycle pulse} With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles. \inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py} +\newpage + \subsection{Edge counting in a 1ms window} The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively. The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection. - \inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py} + \inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py} Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel. \inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py} diff --git a/2238.tex b/2238.tex index ed231a8..e5a835a 100644 --- a/2238.tex +++ b/2238.tex @@ -530,6 +530,36 @@ \end{multicols} +\sysdescsection + + 2238 MCX-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format: + + \begin{tcolorbox}[colback=white] + \begin{minted}{json} + { + "type": "dio", + "board": "DIO_MCX", // optional + "ports": [0], + "edge_counter": true, // optional + "bank_direction_low": "input", // or "output" + "bank_direction_high": "output" // or "input" + }, + { + "type": "dio", + "board": "DIO_MCX", + "ports": [1], + "bank_direction_low": "output", + "bank_direction_high": "output" + } + \end{minted} + \end{tcolorbox} + + Note that due to its high channel account and double EEM connections 2238 MCX-TTL is entered into a system description as two peripheral entries, each representing two banks. + + The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry. + + For single-EEM operation, use only one of two peripheral entries. + \newpage \codesection{2238 MCX-TTL card} diff --git a/2245.tex b/2245.tex index 221fde2..580c9b3 100644 --- a/2245.tex +++ b/2245.tex @@ -312,7 +312,7 @@ All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}). - \begin{table}[h] + \begin{table}[h!] \begin{threeparttable} \caption{Recommended Input Voltage} \begin{tabularx}{\textwidth}{l | c | c c c | c | X} @@ -334,7 +334,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$. - \begin{table}[h] + \begin{table}[h!] \begin{threeparttable} \caption{DC Specifications} \begin{tabularx}{\textwidth}{l | c | c c c | c | X} @@ -360,7 +360,7 @@ All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given. - \begin{table}[h] + \begin{table}[h!] \begin{threeparttable} \caption{AC Specifications} \begin{tabularx}{\textwidth}{l | c c c | c | X} @@ -379,15 +379,27 @@ LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\ deterministic & & & & & 800 Mbps\\ \hline - LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\ - random (RMS) & & & & & \\ - \thickhline \end{tabularx} \end{threeparttable} \end{table} \newpage + \begin{table}[h!] + \begin{threeparttable} + \caption{AC Specifications, cont.} + \begin{tabularx}{\textwidth}{l | c c c | c | X} + \thickhline + \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} & + \textbf{Unit} & \textbf{Conditions} \\ + \hline + LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\ + random (RMS) & & & & & \\ + \thickhline + \end{tabularx} + \end{threeparttable} + \end{table} + \section{Configuring IO Direction \& Termination} \begin{multicols}{2} @@ -411,6 +423,36 @@ \end{multicols} +\sysdescsection + + 2245 LVDS-TTL should be entered in the \texttt{peripherals} list of the corresponding core device in the following format: + + \begin{tcolorbox}[colback=white] + \begin{minted}{json} + { + "type": "dio", + "board": "DIO_LVDS", // optional + "ports": [0], + "edge_counter": true, // optional + "bank_direction_low": "input", // or "output" + "bank_direction_high": "output" // or "input" + }, + { + "type": "dio", + "board": "DIO_LVDS", + "ports": [1], + "bank_direction_low": "output", + "bank_direction_high": "output" + } + \end{minted} + \end{tcolorbox} + + Note that due to its high channel account and double EEM connections 2245 LVDS-TTL is entered into a system description as two peripheral entries, each representing two banks. + + The \texttt{edge\_counter} field is boolean and may be specified true or false; a setting \texttt{true} will make a corresponding ARTIQ \texttt{edge\_counter} module available and consume a corresponding amount of additonal gateware resources. If not included, its default value is false. Both \texttt{edge\_counter} and IO direction can be specified separately for each entry. + + For single-EEM operation, use only one of two peripheral entries. + \newpage \codesection{2245 LVDS-TTL card} @@ -425,7 +467,8 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python language. \inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py} - \newpage +\newpage + \subsection{Counting rising edges in a 1ms window} The channel should be configured as input in both gateware and hardware. \inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py} @@ -451,8 +494,6 @@ \noindent\strut\usebox0\par \egroup} -\newpage - \subsection{SPI Master Device} If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern: \begin{enumerate} @@ -487,8 +528,10 @@ \end{tabular} \end{table} - The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves. - The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on. + The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves. The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on. + +\newpage + \begin{center} \begin{circuitikz}[european, scale=1, every label/.append style={align=center}] % SPI master @@ -556,8 +599,6 @@ \end{circuitikz} \end{center} -\newpage - \subsubsection{SPI Configuration} The following examples will assume the SPI communication has the following properties: \begin{itemize} @@ -567,6 +608,9 @@ \item Most significant bit (MSB) first \item Full duplex \end{itemize} + +\newpage + The baseline configuration for an \texttt{SPIMaster} instance can be defined as such: \inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py} The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example. @@ -596,11 +640,11 @@ \end{tikztimingtable}% \end{center} -\newpage - Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code: \inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py} +\newpage + \subsubsection{SPI read} A 32-bit read is represented by the following timing diagram: @@ -626,8 +670,6 @@ Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code. \inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py} -\newpage - \ordersection{2245 LVDS-TTL} \finalfootnote