diff --git a/4410-4412.tex b/4410-4412.tex
index f4a7be1..733f432 100644
--- a/4410-4412.tex
+++ b/4410-4412.tex
@@ -407,7 +407,7 @@ The full documentation for the ARTIQ software and gateware is available at \url{
 % Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
 
 \subsection{10 MHz Sinusoidal Wave}
-Generate a 10MHz sinusoid from RF0 with full scale amplitude and 0.25 turns phase, attenuated by 6 dB.
+Generate a 10MHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB.
 Both the CPLD and the DDS channels should be initialized.
 
 \begin{minted}{python}
@@ -418,7 +418,7 @@ def run(self):
     self.dds0.init()
     self.dds0.cfg_sw(True)
     self.dds0.set_att(6.)
-    self.dds0.set(10*MHz, amplitude=1.0, phase=0.25)
+    self.dds0.set(10*MHz, amplitude=1.0)
 \end{minted}
 
 If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized.