diff --git a/4410.tex b/4410.tex new file mode 100644 index 0000000..9f3772b --- /dev/null +++ b/4410.tex @@ -0,0 +1,397 @@ +\documentclass[10pt]{datasheet} +\usepackage{palatino} +\usepackage{textgreek} +\usepackage{minted} +\usepackage{tcolorbox} +\usepackage{etoolbox} +\BeforeBeginEnvironment{minted}{\begin{tcolorbox}[colback=white]}% +\AfterEndEnvironment{minted}{\end{tcolorbox}}% + +\usepackage[justification=centering]{caption} + +\usepackage[utf8]{inputenc} +\usepackage[english]{babel} +\usepackage[english]{isodate} + +\usepackage{graphicx} +\usepackage{subfigure} + +\usepackage{tikz} +\usepackage{pgfplots} +\usepackage{circuitikz} +\usetikzlibrary{calc} +\usetikzlibrary{fit,backgrounds} + +\title{4410 Urukul} +\author{M-Labs Limited} +\date{November 2021} +\revision{Revision 1} +\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}} + +\begin{document} +\maketitle + +\section{Features} + +\begin{itemize} +\item{4 channels 1GS/s DDS.} +\item{Output frequency ranges from \textless 1 to \textgreater 400 MHz.} +\item{Sub-Hz frequency resolution.} +\item{Controlled phase steps.} +\item{Accurate output amplitude control.} +\end{itemize} + +\section{Applications} + +\begin{itemize} +\item{Agile local oscillator (LO) frequency synthesis.} +\item{Programmable clock generators.} +\item{FM chirp source for radar and scanning systems.} +\end{itemize} + +\section{General Description} +The 4410 Urukul card is a 4hp EEM module part of the ARTIQ Sinara family. +It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. + +It provides 4 channels of DDS at 1GS/s. +Output frequency from \textless 1 to \textgreater 400 MHz are supported. +The nominal maximum output power of each channel is 10dBm. +Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. +RF switches (1ns temporal resolution) on each channel provides 70 dB isolation. +Urukul comes with either AD9910 or AD9912 chips. + + +% Switch to next column +\vfill\break + +\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}} +\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}} + +\begin{figure}[h] + \centering + \scalebox{0.88}{ + \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}] + + \begin{scope}[] + + % Node to pin-point the locations of SMA symbols + \draw[color=white, text=black] (-0.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (ext_clk) {}; + \draw[color=white, text=black] (-0.1, -0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx) {}; + \draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf0) {}; + \draw[color=white, text=black] (-0.1, -2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf1) {}; + \draw[color=white, text=black] (-0.1, -3.15) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf2) {}; + \draw[color=white, text=black] (-0.1, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf3) {}; + + % Labels for female EXT_CLK, MMCX, RF {0, 1, 2, 3} + \node [label=left:\tiny{EXT CLK}] at (0.35, 0) {}; + \node [label=left:\tiny{MMCX}] at (0.35, -0.35) {}; + \node [label=left:\tiny{RF 0}] at (0.35, -1.75) {}; + \node [label=left:\tiny{RF 1}] at (0.35, -2.45) {}; + \node [label=left:\tiny{RF 2}] at (0.35, -3.15) {}; + \node [label=left:\tiny{RF 3}] at (0.35, -3.85) {}; + + % draw female EXT_CLK, MMCX, RF {0, 1, 2, 3} + \begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm] + \draw (0,0.65) -- (0,3); + \clip (-1.5,0) rectangle (1.5,1.5); + \draw (0,0) circle(1.5); + \clip (-0.8,0) rectangle (0.8,0.8); + \draw (0,0) circle(0.8); + \end{scope} + \begin{scope}[scale=0.07 , rotate=-90, xshift=5cm, yshift=2cm] + \draw (0,0.65) -- (0,3); + \clip (-1.5,0) rectangle (1.5,1.5); + \draw (0,0) circle(1.5); + \clip (-0.8,0) rectangle (0.8,0.8); + \draw (0,0) circle(0.8); + \end{scope} + \begin{scope}[scale=0.07 , rotate=-90, xshift=25cm, yshift=2cm] + \draw (0,0.65) -- (0,3); + \clip (-1.5,0) rectangle (1.5,1.5); + \draw (0,0) circle(1.5); + \clip (-0.8,0) rectangle (0.8,0.8); + \draw (0,0) circle(0.8); + \end{scope} + \begin{scope}[scale=0.07 , rotate=-90, xshift=35cm, yshift=2cm] + \draw (0,0.65) -- (0,3); + \clip (-1.5,0) rectangle (1.5,1.5); + \draw (0,0) circle(1.5); + \clip (-0.8,0) rectangle (0.8,0.8); + \draw (0,0) circle(0.8); + \end{scope} + \begin{scope}[scale=0.07 , rotate=-90, xshift=45cm, yshift=2cm] + \draw (0,0.65) -- (0,3); + \clip (-1.5,0) rectangle (1.5,1.5); + \draw (0,0) circle(1.5); + \clip (-0.8,0) rectangle (0.8,0.8); + \draw (0,0) circle(0.8); + \end{scope} + \begin{scope}[scale=0.07 , rotate=-90, xshift=55cm, yshift=2cm] + \draw (0,0.65) -- (0,3); + \clip (-1.5,0) rectangle (1.5,1.5); + \draw (0,0) circle(1.5); + \clip (-0.8,0) rectangle (0.8,0.8); + \draw (0,0) circle(0.8); + \end{scope} + + % Draw the internal oscillator + \draw (0.02, -0.8) node[twoportshape, t={OSC}, circuitikz/bipoles/twoport/width=0.8, scale=0.4] (xo) {}; + + % Draw the clock buffers as selector + % \tikzset{demux/.style={muxdemux, muxdemux def={Lh=6, Rh=6, NL=3, NT=1, NB=0, NR=1, w=2.5}, no input leads, scale=0.4}}; + % \draw (1.55, -0.35) node[demux]{\rotatebox[origin=c]{-90}{CLK BUFFERS}}; + \draw (1.45, -0.35) node[twoportshape, t={CLK Buffers}, circuitikz/bipoles/twoport/width=2.2, scale=0.4, rotate=-90] (clk_buf) {}; + + % Connect CLK_IN to DDS clock buffers + \draw [-latexslim] (ext_clk.east) -- ++(1,0); + \draw [-latexslim] (mmcx.east) -- ++(1,0); + \draw [-latexslim] (xo.east) -- ++(1,0); + + % Connect CPLD clk_sel to DDS clock buffers + \draw [-latexslim] (clk_buf.east) -- ++(0,-0.42); + + % Signal path: From control signals / clock of DDS to output of the RF switches + \draw (1.85, -1.75) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig0) {}; + \draw (1.85, -2.45) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig1) {}; + \draw (1.85, -3.15) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig2) {}; + \draw (1.85, -3.85) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig3) {}; + + % Extra node to expand the dotted area eastward + \draw[color=white, text=black] (2.6, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=0.4, scale=0.4 ] (sig3_east) {}; + + % Connect RF to DDS block + \draw [latexslim-] (rf0.east) -- ++(1,0); + \draw [latexslim-] (rf1.east) -- ++(1,0); + \draw [latexslim-] (rf2.east) -- ++(1,0); + \draw [latexslim-] (rf3.east) -- ++(1,0); + + % DDS signal path dotted area + \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(rf3)(sig0)(sig3_east.east)] (abs_dds) {}; + \node[fill=white, rotate=-90, scale=0.7] at (abs_dds.west) {DDS Channels}; + + % CPLD + \draw (3.8, -0.35) node[twoportshape, t={CPLD}, circuitikz/bipoles/twoport/width=1.1, scale=0.8, rotate=-90] (cpld) {}; + + % Synthronization clock buffer for DDS block + \draw (3.8, -2.5) node[twoportshape, t=\MymyLabel{Sync}{Buffer}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (sync_buf) {}; + + % Connect CPLD to: + % DDS clock buffer + \draw [latexslim-] (clk_buf.north) -- (cpld.south); + % DDS signal path + \draw [latexslim-latexslim] (3.4, -0.7) -- ++ (-1.5, 0) -- ++ (0,-0.72); + % Draw to intersection point, then complete the connection to sync buffer + \draw [-] (4.2, -0.7) -- (4.55, -0.7) -- (4.55, -2.5); + \draw [-latexslim] (4.55, -2.5) -- (sync_buf.east); + + % Connect sync buffer to DDS block + \draw [-latexslim] (sig0.east) -- (3.65, -1.75) -- ++ (0, -0.5); + \draw [-latexslim] (sync_buf.south) -- ++ (0, -0.3) -- ++ (-0.85, 0); + + % LVDS Transceivers + \draw (6, 0) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds0) {}; + \draw (6, -0.7) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds1) {}; + \draw (6, -2.5) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds2) {}; + \draw (6, -3.2) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds3) {}; + + % Connect CPLD to transceivers + \draw [latexslim-latexslim] (lvds0.west) -- ++ (-1.13, 0); + \draw [latexslim-latexslim] (lvds1.west) -- ++ (-0.35, 0) -- ++ (0, 0.6) -- ++ (-0.78, 0); + \draw [latexslim-latexslim] (lvds2.west) -- ++ (-0.45, 0) -- ++ (0, 2.3) -- ++ (-0.68, 0); + \draw [latexslim-latexslim] (lvds3.west) -- ++ (-0.55, 0) -- ++ (0, 2.9) -- ++ (-0.58, 0); + + % EEPROMs + \draw (6, -1.4) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (eeprom0) {}; + \draw (6, -3.9) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (eeprom1) {}; + + % Repeaters for DDS0 sync clock & DDS sync output from sync buffer + \draw (3.8, -3.85) node[twoportshape, t={Repeaters}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (rep) {}; + + % Connect DDS0 to repeaters + \draw [-latexslim] (sig0.east) -- ++ (0.3, 0) -- ++ (0, -1.55) -- (3.65, -3.3) -- ++ (0, -0.3); + + % Connect sync_buf to repeaters + \draw [-latexslim] (sync_buf.south) -- ++ (0, -0.3) -- ++ (0.15, 0) -- ++ (0, -0.55); + + % EEMs + \draw (8, -0.9) node[twoportshape, t={EEM Port 0}, circuitikz/bipoles/twoport/width=3.2, scale=0.5, rotate=-90] (eem0) {}; + \draw (8, -3.4) node[twoportshape, t={EEM Port 1}, circuitikz/bipoles/twoport/width=3.2, scale=0.5, rotate=-90] (eem1) {}; + + % Connect LVDS and EEM + \draw [latexslim-latexslim] (lvds0.east) -- (7.75, 0); + \draw [latexslim-latexslim] (lvds1.east) -- (7.75, -0.7); + \draw [latexslim-latexslim] (lvds2.east) -- (7.75, -2.5); + \draw [latexslim-latexslim] (lvds3.east) -- (7.75, -3.2); + + % Connect EEPROM to EEM + \draw [latexslim-latexslim] (eeprom0.east) -- (7.75, -1.4); + \draw [latexslim-latexslim] (eeprom1.east) -- (7.75, -3.9); + + % Connect EEM0 to sync_buf + \draw [latexslim-] (3.95, -2.25) -- (3.95, -1.85) -- (7.75, -1.85); + + % Connect repeaters output to EEM1 + \draw [-latexslim] (rep.south) -- (3.8, -4.35) -- (7.75, -4.35); + + \end{scope} + + \end{circuitikz} + } + + \caption{Simplified Block Diagram} +\end{figure} + +\begin{figure}[h] + \centering + \scalebox{0.88}{ + \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}] + + \begin{scope}[] + % RF switches {0, 1, 2, 3} for SMA {0, 1, 2, 3} + \draw (1.4, 0) node[twoportshape, t={RF Switch}, circuitikz/bipoles/twoport/width=1.5, scale=0.6] (sw) {}; + + % Amplifiers {0, 1, 2, 3} for RF switches {0, 1, 2, 3} + \draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {}; + + % Attenuators {0, 1, 2, 3} for amplifiers {0, 1, 2, 3} + \draw (4.6, 0) node[twoportshape, t=\MymyLabel{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {}; + + % DDS {0, 1, 2, 3} for attenuators {0, 1, 2, 3} + \draw (6.6, 0) node[twoportshape, t={DDS}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (dds) {}; + + % Connect main signal path + \draw [-latexslim] (dds.west) -- (att.north); + \draw [-latexslim] (att.south) -- (amp.west); + \draw [-latexslim] (amp.east) -- (sw.east); + + % Connect abstract DDS clock input + \node [label=above:\tiny{CLK Buffers}] at (8, -0.2) {}; + \draw [latexslim-] (dds.east) -- (8, 0); + + % Insert CPLD signal to relevant components + \node [label=above:\tiny{CPLD}] at (8, 1.1) {}; + \draw [-] (1.4, 1.3) -- (8, 1.3); + \draw [-latexslim] (1.4, 1.3) -- (sw.north); + \draw [-latexslim] (4.6, 1.3) -- (att.west); + \draw [-latexslim] (6.6, 1.3) -- (dds.north); + + % Connect sync_buf signal to DDS + \draw [latexslim-] (6.9, -1.35) -- (6.9, -0.35); + \draw [-latexslim] (6.3, -1.35) -- (6.3, -0.35); + \node [label=below:\tiny{Sync Buffer /}] at (6.6, -1.15) {}; + \node [label=below:\tiny{Repeaters}] at (6.6, -1.4) {}; + \node [label={[rotate=-90]above:\tiny{DDS 0}}] at (6.8, -0.9) {}; + \node [label={[rotate=-90]above:\tiny{Only}}] at (6.55, -0.9) {}; + + \end{scope} + + \end{circuitikz} + } + + \caption{Simplified DDS Signal Path} +\end{figure} + +\begin{figure}[h] + \centering + \includegraphics[width=1.8in]{photo4410.jpg} + \caption{Urukul Card photo} +\end{figure} + +% For wide tables, a single column layout is better. It can be switched +% page-by-page. +\onecolumn + +\section{Electrical Specifications} +TODO + +\section{Example ARTIQ code} +The sections below demonstrate simple usage scenarios of the 4410 Urukul card with the ARTIQ control system. +They do not exhaustively demonstrate all the features of the ARTIQ system. +The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}. + +% Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system. + +\subsection{10 MHz Sinusoidal Wave} +Both the CPLD and the DDS channels should be initialized. + +\begin{minted}{python} +@kernel +def run(self): + self.core.reset() + self.cpld.init() + self.dds0.init() + self.dds0.cfg_sw(True) + self.dds0.set_att(6.) + self.dds0.set(10*MHz) +\end{minted} + +If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized. +For example, synchronized RF signal can be produced on both channel 0 and channel 1 after configuring an appropriate phase mode. +\begin{minted}{python} +@kernel +def run(self): + self.core.reset() + self.cpld.init() + + self.dds0.init() + self.dds0.cfg_sw(True) + self.dds0.set_phase_mode(PHASE_MODE_TRACKING) + self.dds0.set_att(6.) + self.dds1.init() + self.dds1.cfg_sw(True) + self.dds1.set_phase_mode(PHASE_MODE_TRACKING) + self.dds1.set_att(6.) + + self.dds0.set(10*MHz) + self.dds1.set(10*MHz) +\end{minted} + +\newpage +\subsection{DDS RAM Modulation} +Only available to AD9910 variants. Set field \texttt{dds} as an Urukul channel, \texttt{cpld} as the corresponding Urukul CPLD. + +\begin{minted}{python} +from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP + +@kernel +def run(self): + self.core.reset() + self.core.break_realtime() + self.cpld.init() + self.dds.init() + + self.core.break_realtime() + self.profile0_set() + self.dds.set_att(6.) + self.dds.sw.on() + + self.cpld.set_profile(0) + +@kernel +def profile0_set(self): + self.dds.set_cfr1(ram_enable = 0) + self.cpld.set_profile(0) + amp_ram = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order + asf_ram = [0] * len(amp_ram) + self.dds.set_profile_ram(start=0, end=len(amp_ram)-1, + step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP) + self.cpld.io_update.pulse_mu(8) + self.dds.amplitude_to_ram(amp_ram, asf_ram) + self.dds.write_ram(asf_ram) + self.dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF) + self.dds.set_frequency(10*MHz) + self.cpld.io_update.pulse_mu(8) +\end{minted} + +\section{Ordering Information} +To order, please visit \url{https://m-labs.hk} and select the 4410 Urukul in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}. + +\section*{} +\vspace*{\fill} + +\begin{footnotesize} +Information furnished by M-Labs Limited is believed to be accurate and reliable. However, no responsibility is assumed by M-Labs Limited for its use, nor for any infringements of patents or other rights of third parties that may result from its use. +Specifications subject to change without notice. +\end{footnotesize} + +\end{document} diff --git a/photo4410.jpg b/photo4410.jpg new file mode 100644 index 0000000..ade7307 Binary files /dev/null and b/photo4410.jpg differ