From 75f3a328db7931854935f9d5e1e1655f4fde3a4f Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Mon, 14 Feb 2022 10:38:28 +0800
Subject: [PATCH] 4456: dds -> pll

---
 4456.tex | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/4456.tex b/4456.tex
index 1322af1..82e657d 100644
--- a/4456.tex
+++ b/4456.tex
@@ -182,12 +182,12 @@ RF switches on each channel provides at least 50 dB isolation.
             % Draw the clock buffers
             \draw (1.6, 0) node[twoportshape, t={CLK Buffers}, circuitikz/bipoles/twoport/width=2.2, scale=0.5, rotate=-90] (clk_buf) {};
 
-            % Connect CLK_IN to DDS clock buffers
+            % Connect CLK_IN to PLL clock buffers
             \draw [-latexslim] (ext_clk.east) -- (1.35, 0.35);
             \draw [-latexslim] (mmcx.east) -- (1.35, 0);
             \draw [-latexslim] (xo.east) -- (1.35, -0.45);
 
-            % Connect CPLD clk_sel to DDS clock buffers
+            % Connect CPLD clk_sel to PLL clock buffers
             \draw [-latexslim] (clk_buf.east) -- (1.6, -1.35);
 
             % Signal path: From control signals / clock of PLL to output of the RF switches
@@ -196,7 +196,7 @@ RF switches on each channel provides at least 50 dB isolation.
             \draw (1.6, -3.15) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig2) {};
             \draw (1.6, -3.85) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig3) {};
 
-            % Connect RF to DDS block
+            % Connect RF to PLL block
             \draw [latexslim-] (rf0.east) -- (sig0.west);
             \draw [latexslim-] (rf1.east) -- (sig1.west);
             \draw [latexslim-] (rf2.east) -- (sig2.west);
@@ -278,7 +278,7 @@ RF switches on each channel provides at least 50 dB isolation.
             \draw [-latexslim] (att.south) -- (amp.west);
             \draw [-latexslim] (amp.east) -- (sw.east);
 
-            % Connect abstract DDS clock input
+            % Connect abstract PLL clock input
             \node [label=above:\tiny{CLK Buffers}] at (8, -0.2) {};
             \draw [latexslim-] (pll.east) -- (8, 0);
 
@@ -302,7 +302,7 @@ RF switches on each channel provides at least 50 dB isolation.
     \end{circuitikz}
     }
 
-    \caption{Simplified DDS Signal Path}
+    \caption{Simplified PLL Signal Path}
 \end{figure}
 
 \begin{figure}[hbt!]