5716: init

5716.tex

@@ -0,0 +1,200 @@
+\input{preamble.tex}
+\input{shared/coredevice.tex}
+\graphicspath{{images}{images/5716}}
+
+\title{5716 DAC Shuttler}
+\author{M-Labs Limited}
+\date{January 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+\begin{itemize}
+    \item{16-channel 125 MSPS DAC}
+    \item{14-bit resolution, $<1$ LSB DNL}
+    \item{Remote analog front end}
+    \item{EEM carrier with Artix-7 FPGA core}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+    \item{Driving DC electrodes in ion traps}
+    \item{Ion splitting, ion shuttling}
+\end{itemize}
+
+\section{General Description}
+
+    The 5716 DAC Shuttler is an 8hp EEM module, shipped with associated remote analog front-end (AFE), part of the ARTIQ/Sinara family. It consists of the Shuttler FMC paired with an 8hp Sinara EEM FMC Carrier, which is capable of running as an ARTIQ satellite through DRTIO-over-EEM.
+
+    ARTIQ gateware implements NIST PDQ-style waveform synthesizer which supports the use of sigma-delta modulation to increase effective resolution to 18 bits.
+
+    Digital communication between FMC and remote AFE is provided through mini-SAS HD cables. The AFE supports +/- 10v output and 50MHz 3dB bandwidth, using onboard 24-bit ADC for calibration.
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+%
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2in]{photo5716.jpg}
+    \caption{Shuttler FMC}
+    \includegraphics[height=1.5in]{shuttler_afe.jpg}
+    \caption{Shuttler AFE}
+    \includegraphics[height=1.5in]{fmc_side.jpg}
+    \caption{Sinara EEM FMC carrier}
+    \includegraphics[height=2.5in, angle=90]{fp5716.pdf}
+    \caption{Shuttler front panel diagram}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{5716 DAC Shuttler}{https://github.com/sinara-hw/FMC_Shuttler} The same repository also includes the AFE card. Design files for the Sinara EEM FMC Carrier can be found at \url{https://github.com/sinara-hw/EEM_FMC_Carrier}.
+
+\section{Electrical Specifications}
+
+    AD9117 datasheet: \url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9114_9115_9116_9117.pdf}
+
+    \begin{table}[h]
+        \centering
+        \begin{threeparttable}
+        \caption{Output Specifications}
+        \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+        \end{table}
+
+    \begin{table}[h]
+            \centering
+            \begin{threeparttable}
+            \caption{Electrical Characteristics}
+            \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+                \thickhline
+                \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+                \textbf{Unit} & \textbf{Conditions / Comments} \\
+                \hline
+                \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+% re: bandwidth ? https://github.com/sinara-hw/FMC_Shuttler/issues/36#issuecomment-1481233357
+
+    Power to Shuttler is supplied over EEM. Power to the AFE is to be supplied over a 4-pin circular M8 connector placed between the mini-SAS HD ports. The AFE output port is 25-pin DSUB.
+
+\artiqsection
+
+    The Sinara EEM FMC Carrier features an XC7A200T-3FBG484E Xilinx Artix-7 FPGA, usually configured as an ARTIQ satellite core. Firmware and gateware for the Sinara EEM FMC Carrier is similar to that used for 1124 Kasli 2.0 satellites. The specific binary generation target can be found in the module \texttt{artiq.gateware.targets.efc}.
+
+\sysdescsection
+
+    5716 Shuttler should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+        {
+        "type": "shuttler",
+        "ports": 0
+        }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port number used on the core device. Any port can be used. On the other side, the Sinara EEM FMC Carrier possesses two EEM ports, but only one is necessary for Shuttler. This should always be \texttt{EEM0}.
+
+    Since Shuttler acts as a DRTIO satellite, the DRTIO type of the core device should be specified as master, not standalone.
+
+    It is also necessary to configure a DRTIO routing table. DRTIO-over-EEM for Shuttler is automatically assigned destination number \#4. Destination numbers count up correspondingly for additional Shuttlers. See the ARTIQ manual\footnote{\url{https://m-labs.hk/artiq/manual/using_drtio_subkernels.html}} for instructions on configuring a routing table.
+
+\section{Clocking}
+
+    Clock input can be provided to FMC Carrier via SMA connector on front panel, MMCX connector at back of board (top right, above \texttt{EEM0}), PE CLK, or generated by internal oscillator. Shuttler FMC features a front panel MCX connector for clock input; however, it is currently unused by ARTIQ firmware/gateware.
+
+    \begin{multicols}{2}
+        FMC Carrier clock source must be configured by setting the DIP switches on back of the board, under the following schema:
+
+        \begin{center}
+            \begin{tabular}{ | c | c | c | } \thickhline
+            \textbf{Clock Source} & \textbf{CLK\_SEL0} & \textbf{CLK\_SEL1} \\
+            \thickhline
+            Front panel SMA & 0 & 0 \\ \hline
+            Internal oscillator & 1 & 0 \\ \hline
+            Back MMCX & 0 & 1 \\ \hline
+            PE CLK & 1 & 1 \\ \hline
+            \end{tabular}
+        \end{center}
+
+        \vspace*{\fill}
+
+    \columnbreak
+
+        \begin{center}
+            \centering
+            \includegraphics[height=1.7in]{shuttler_dip_switches.jpg}
+            \captionof{figure}{Position of DIP switches}
+        \end{center}
+
+    \end{multicols}
+
+    Clock input supplied to Shuttler must be share a common source with that used by the connected core
+
+    At first power-up, FMC Carrier and connected core device will determine the clock skew over EEM transceiver and store the result in memory (flash or SD card). As of ARTIQ-8, there is no way to reset this value manually. If EEM cable or clocking cables are changed, or if either device is reflashed for any reason, both devices must be reflashed in order to force reevaluation of clock skew value.
+
+\section{LEDs}
+
+    The EEM FMC Carrier provides two user LEDs, \texttt{L0} and \texttt{L1}, located on the front panel, which are accessible in ARTIQ gateware and can be used for testing.
+
+    The Shuttler AFE provides twenty LEDs in two banks. The four-LED bank to the right of the mini-SAS connectors indicate power status. The sixteen-LED bank to the left of the mini-SAS connectors indicate output relay status. DAC output is only valid when corresponding relay LEDs are on.
+
+\codesection{5716 DAC Shuttler}
+
+    Shuttler is capable of generating a waveform in the following equation:
+
+    \[ w(t) = a(t) + b(t) * cos(c(t)) \]
+
+    where $a(t)$ and $b(t)$ are cubic splines and $c(t)$ is a quadratic spline\footnote{See also the PDQ documentation hosted at the following link: \url{https://pdq.readthedocs.io/}}.
+
+    The following code initializes relay and ADC and resets all channels.
+
+    \inputcolorboxminted{firstline=21,lastline=65}{examples/shuttler.py}
+
+    \subsection{Generating a basic waveform}
+
+    The following code generates a basic sine wave of approx 10MHz on the \texttt{DAC0 I} channel. The value of \texttt{0x147AE148} used for $c_1$ sets the frequency as $c_1 / 2^{32} * 125$ MHz.
+
+    \inputcolorboxminted{firstline=67,lastline=85}{examples/shuttler.py}
+
+    \begin{figure}[!hbt]
+        \centering
+        \includegraphics[height=3in]{sine_wave.jpg}
+        \caption{Produced waveform, measured at \texttt{AFE0} output resistor R36A, R39A.}
+    \end{figure}
+
+    For more example waveforms see also the folder \texttt{kasli\_shuttler} in the ARTIQ \texttt{examples} directory.
+
+\ordersection{5716 DAC Shuttler}
+
+\finalfootnote
+
+\end{document}

Makefile

@@ -1,4 +1,5 @@
-inputs = 1124 1125 2118-2128 2238 2245 4410-4412 4456 5108 5432 5518-5528 5568 7210
+inputs = 1124 1125 2118-2128 2238 2245 4410-4412 4456 5108 5432 5518-5528 5568 5716 7210
+
 dir = build
 
 all: $(inputs)

examples/shuttler.py

@@ -0,0 +1,85 @@
+from artiq.experiment import *
+
+class SineWave(EnvExperiment):
+
+    def build(self):
+        self.setattr_device("core")
+        self.shuttler0_leds = (
+            [ self.get_device("shuttler0_led{}".format(i)) for i in range(2) ]
+        )
+        self.setattr_device("shuttler0_config")
+        self.setattr_device("shuttler0_trigger")
+        self.shuttler0_dcbias = (
+            [ self.get_device("shuttler0_dcbias{}".format(i)) for i in range(16) ]
+        )
+        self.shuttler0_dds = (
+            [ self.get_device("shuttler0_dds{}".format(i)) for i in range(16) ]
+        )
+        self.setattr_device("shuttler0_relay")
+        self.setattr_device("shuttler0_adc")
+
+    @kernel
+    def relay_init(self):
+        self.shuttler0_relay.init()
+        self.shuttler0_relay.enable(0x0000)
+
+    @kernel
+    def adc_init(self):
+        delay_mu(int64(self.core.ref_multiplier))
+        self.shuttler0_adc.power_up()
+
+        delay_mu(int64(self.core.ref_multiplier))
+        assert self.shuttler0_adc.read_id() >> 4 == 0x038d
+
+        delay_mu(int64(self.core.ref_multiplier))
+        # The actual output voltage is limited by the hardware,
+        # the calculated calibration gain and offset.
+        # For example, if the system has a calibration gain of
+        # 1.06, then the max output voltage = 10 / 1.06 = 9.43V.
+        # Setting a value larger than 9.43V will result in overflow.
+        self.shuttler0_adc.calibrate(
+            self.shuttler0_dcbias, self.shuttler0_trigger, self.shuttler0_config)
+
+    @kernel
+    def shuttler_channel_reset(self, ch):
+        self.shuttler0_dcbias[ch].set_waveform(
+            a0=0, a1=0, a2=0, a3=0,
+        )
+        self.shuttler0_dds[ch].set_waveform(
+            b0=0, b1=0, b2=0, b3=0,
+            c0=0, c1=0, c2=0,
+        )
+        self.shuttler0_trigger.trigger(1 << ch)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+
+        self.relay_init()
+        self.adc_init()
+
+        for i in range(16):
+            self.shuttler_channel_reset(i)
+            # To avoid RTIO Underflow
+            delay(50*us)
+
+    @kernel
+    def sine(self):
+        for i in range(2):
+            self.shuttler0_dcbias[i].set_waveform(
+                a0=0,
+                a1=0,
+                a2=0,
+                a3=0,
+            )
+            self.shuttler0_dds[i].set_waveform(
+                b0=0x0FFF,
+                b1=0,
+                b2=0,
+                b3=0,
+                c0=0,
+                c1=0x147AE148, # Frequency = 10MHz
+                c2=0,
+            )
+        self.shuttler0_trigger.trigger(0xFFFF)