1124: update fixes

1124.tex

@@ -49,11 +49,11 @@
 \end{itemize}
 
 \section{General Description}
-The 1124 Kasli 2.0 Carrier card is an 8hp EEM module, designed to run ARTIQ kernels sent from a host machine over the network. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up to three SFP connections to satellite carriers.
+The 1124 Kasli 2.0 Carrier card is an 8hp EEM module, designed to run ARTIQ kernels sent from a host machine over the network. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections, used for comunications with other carriers and/or Ethernet.
 
 Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
 
-4 SFP Gb/s slots are provided for Ethernet or DRTIO communications. Communication with a host machine is supported over Ethernet, while the Distributed Real-Time Input/Output (DRTIO) system allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the DRTIO master.
+4 SFP 6Gb/s slots are provided. One may be used for Ethernet, which supports communication with a host machine. Remaining slots can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the \mbox{DRTIO} master.
 
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 \vfill\break
@@ -231,11 +231,11 @@ Power is to be supplied through the barrel connector in the front panel, size 5.
 
 \section{FPGA}
 
-Kasli 2.0 features an XC7A100T-2FGG484I Xilink Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.
+Kasli 2.0 features an XC7A100T-3FGG484E Xilink Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.
 
 ARTIQ is open-source and can be found in the repository \url{https://github.com/m-labs/artiq}. Orders of Sinara hardware are normally accompanied with precompiled binaries. Long-term support for ARTIQ systems can also be purchased.
 
-A micro-USB located at the back of the Kasli 2.0 board is equipped for JTAG, I2C, and UART serial output.
+A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
 
 \subsection{Note on distributed RTIO (DRTIO)}
 
@@ -251,7 +251,7 @@ When run in a non-distributed ARTIQ configuration, with a single central core de
 
 \section{Communication interfaces}
 
-Communication between devices is implemented using 10000Base-X small form-factor pluggable (SFP) interfaces. Four are available on the Kasli 2.0. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
+Communication between devices is implemented using 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on the Kasli 2.0. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
 
 \subsection{Upstream connection}
 
@@ -269,7 +269,7 @@ Kasli 2.0 supports up to 3 DRTIO satellite connections per device. Any of the 3
 
 \section{Clock Routing}
 \subsection{Standalone/Master}
-The RTIO clock is typically synthesized by the Si5324 clock multiplier and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors. Alternatively, an external reference can be supplied through the front panel SMA connector. It is then buffered in the PFGA and sent to the Si5324 for clock synthesis. Kasli 2.0 supports a set of RTIO clock options:
+The RTIO clock is typically synthesized by the Si5324 clock multiplier and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors. Alternatively, an external reference can be supplied through the front panel SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis. Kasli 2.0 supports a set of RTIO clock options:
 \begin{table}[H]
     \centering
     \begin{tabular}{|c|c|c|}
@@ -295,11 +295,11 @@ Clocking options in a running system should be configured by setting the value o
 and rebooting.
 
 \subsection{Satellite}
-The RTIO clock is recovered from the SFP transceiver connected to the upstream device. The resulting signal is then cleaned by the Si5324 and routed to both the RTIO system and downstream satellites.
+The RTIO clock is recovered from the SFP transceiver connected to the upstream device. The resulting signal is then cleaned up by the Si5324 and routed to both the RTIO system and downstream satellites.
 
 \subsection{WRPLL}
 
-Kasli 2.0 can be configured to use WRPLL, a clock recovery method making use of White Rabbit's DDMTD (Digital Dual Mixer Time Difference) and the card's Si549 oscillator, both to lock the main RTIO clock and to lock satellite clocks to master.
+Kasli 2.0 can be configured to use WRPLL, a clock recovery method making use of White Rabbit's DDMTD (Digital Dual Mixer Time Difference) and the card's Si549 oscillators, both to lock the main RTIO clock and to lock satellite clocks to master.
 
 \section{User LEDs}