diff --git a/4456.tex b/4456.tex
index b3c8b21..9aa4c36 100644
--- a/4456.tex
+++ b/4456.tex
@@ -431,7 +431,7 @@ They do not exhaustively demonstrate all the features of the ARTIQ system.
 The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
 
 \subsection{1 GHz Sinusoidal Wave}
-Generate a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB.
+Generate a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB.
 Both the CPLD and the PLL channels should be initialized.
 
 \inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
diff --git a/examples/pll.py b/examples/pll.py
index 58d2ffc..dc07ff1 100644
--- a/examples/pll.py
+++ b/examples/pll.py
@@ -13,7 +13,7 @@ class MirnyEnv(EnvExperiment):
         self.cpld.init()
         self.pll0.init()
         self.pll0.set_frequency(1*GHz)
-        self.pll0.set_att_mu(0b11001100)
+        self.pll0.set_att(12*dB)
         self.pll0.sw.on()