From 011d63f3eb55cc9fd0dcd7ddc5566295bdcddd5f Mon Sep 17 00:00:00 2001 From: occheung Date: Tue, 7 Dec 2021 16:21:53 +0800 Subject: [PATCH] 4410: modify ram example * Use `prepare()` to init the arrays, would be great if the value can be prepared there. However, the type check was not happy about it. * Separate RAM configuration into a separate function * Separate DDS init, digital attenuation & switch config in an init function * Use `dds.set()`. It is supposed to look simple. All these are to avoid repeating the long code in the coming RAM+SYNC example. --- 4410-4412.tex | 56 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 23 deletions(-) diff --git a/4410-4412.tex b/4410-4412.tex index b1bf4a1..4a3cf6f 100644 --- a/4410-4412.tex +++ b/4410-4412.tex @@ -457,39 +457,49 @@ It can be negated by adjusting the \texttt{phase} parameter. \newpage \subsection{DDS RAM Modulation (AD9910 Only)} This examples demonstrates that the RF signal can be modulated by amplitude using the RAM modulation feature of AD9910. -Set field \texttt{dds} as an Urukul channel, \texttt{cpld} as the corresponding Urukul CPLD. +By default, RAM profiles are programmed to profile 0. \begin{minted}{python} from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP +def prepare(self): + self.amp = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order + self.asf_ram = [0] * len(self.amp) + +@kernel +def init_dds(self, dds): + self.core.break_realtime() + dds.init() + dds.set_att(6.) + dds.cfg_sw(True) + +@kernel +def configure_ram_mode(self, dds): + self.core.break_realtime() + dds.set_cfr1(ram_enable=0) + self.cpld.io_update.pulse_mu(8) + self.cpld.set_profile(0) # Enable the corresponding RAM profile + # Profile 0 is the default + dds.set_profile_ram(start=0, end=len(self.asf_ram)-1, + step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP) + self.cpld.io_update.pulse_mu(8) + dds.amplitude_to_ram(self.amp, self.asf_ram) + dds.write_ram(self.asf_ram) + + dds.set(10*MHz, profile=-1) + # Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM + dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF) + + self.cpld.io_update.pulse_mu(8) + @kernel def run(self): self.core.reset() self.core.break_realtime() self.cpld.init() - self.dds.init() - self.core.break_realtime() - self.profile0_set() - self.dds.set_att(6.) - self.dds.sw.on() - - self.cpld.set_profile(0) - -@kernel -def profile0_set(self): - self.dds.set_cfr1(ram_enable = 0) - self.cpld.set_profile(0) - amp_ram = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order - asf_ram = [0] * len(amp_ram) - self.dds.set_profile_ram(start=0, end=len(amp_ram)-1, - step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP) - self.cpld.io_update.pulse_mu(8) - self.dds.amplitude_to_ram(amp_ram, asf_ram) - self.dds.write_ram(asf_ram) - self.dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF) - self.dds.set_frequency(10*MHz) - self.cpld.io_update.pulse_mu(8) + self.init_dds(self.dds0) + self.configure_ram_mode(self.dds0) \end{minted} The generated RF output of the above example consists of the following features in sequence: