398 lines
17 KiB
TeX
398 lines
17 KiB
TeX
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\documentclass[10pt]{datasheet}
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\usepackage{palatino}
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\usepackage{textgreek}
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\usepackage{minted}
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\usepackage{tcolorbox}
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\usepackage{etoolbox}
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\BeforeBeginEnvironment{minted}{\begin{tcolorbox}[colback=white]}%
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\AfterEndEnvironment{minted}{\end{tcolorbox}}%
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\usepackage[justification=centering]{caption}
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\usepackage[utf8]{inputenc}
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\usepackage[english]{babel}
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\usepackage[english]{isodate}
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\usepackage{graphicx}
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\usepackage{subfigure}
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\usepackage{tikz}
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\usepackage{pgfplots}
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\usepackage{circuitikz}
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\usetikzlibrary{calc}
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\usetikzlibrary{fit,backgrounds}
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\title{4410 Urukul}
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\author{M-Labs Limited}
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\date{November 2021}
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\revision{Revision 1}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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\begin{itemize}
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\item{4 channels 1GS/s DDS.}
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\item{Output frequency ranges from \textless 1 to \textgreater 400 MHz.}
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\item{Sub-Hz frequency resolution.}
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\item{Controlled phase steps.}
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\item{Accurate output amplitude control.}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{Agile local oscillator (LO) frequency synthesis.}
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\item{Programmable clock generators.}
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\item{FM chirp source for radar and scanning systems.}
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\end{itemize}
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\section{General Description}
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The 4410 Urukul card is a 4hp EEM module part of the ARTIQ Sinara family.
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It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
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It provides 4 channels of DDS at 1GS/s.
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Output frequency from \textless 1 to \textgreater 400 MHz are supported.
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The nominal maximum output power of each channel is 10dBm.
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Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator.
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RF switches (1ns temporal resolution) on each channel provides 70 dB isolation.
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Urukul comes with either AD9910 or AD9912 chips.
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% Switch to next column
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\vfill\break
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\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
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\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
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\begin{figure}[h]
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\centering
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\scalebox{0.88}{
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\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
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\begin{scope}[]
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% Node to pin-point the locations of SMA symbols
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\draw[color=white, text=black] (-0.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (ext_clk) {};
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\draw[color=white, text=black] (-0.1, -0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx) {};
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\draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf0) {};
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\draw[color=white, text=black] (-0.1, -2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf1) {};
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\draw[color=white, text=black] (-0.1, -3.15) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf2) {};
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\draw[color=white, text=black] (-0.1, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf3) {};
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% Labels for female EXT_CLK, MMCX, RF {0, 1, 2, 3}
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\node [label=left:\tiny{EXT CLK}] at (0.35, 0) {};
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\node [label=left:\tiny{MMCX}] at (0.35, -0.35) {};
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\node [label=left:\tiny{RF 0}] at (0.35, -1.75) {};
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\node [label=left:\tiny{RF 1}] at (0.35, -2.45) {};
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\node [label=left:\tiny{RF 2}] at (0.35, -3.15) {};
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\node [label=left:\tiny{RF 3}] at (0.35, -3.85) {};
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% draw female EXT_CLK, MMCX, RF {0, 1, 2, 3}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=5cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=25cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=35cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=45cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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\begin{scope}[scale=0.07 , rotate=-90, xshift=55cm, yshift=2cm]
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\draw (0,0.65) -- (0,3);
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\clip (-1.5,0) rectangle (1.5,1.5);
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\draw (0,0) circle(1.5);
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\clip (-0.8,0) rectangle (0.8,0.8);
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\draw (0,0) circle(0.8);
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\end{scope}
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% Draw the internal oscillator
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\draw (0.02, -0.8) node[twoportshape, t={OSC}, circuitikz/bipoles/twoport/width=0.8, scale=0.4] (xo) {};
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% Draw the clock buffers as selector
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% \tikzset{demux/.style={muxdemux, muxdemux def={Lh=6, Rh=6, NL=3, NT=1, NB=0, NR=1, w=2.5}, no input leads, scale=0.4}};
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% \draw (1.55, -0.35) node[demux]{\rotatebox[origin=c]{-90}{CLK BUFFERS}};
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\draw (1.45, -0.35) node[twoportshape, t={CLK Buffers}, circuitikz/bipoles/twoport/width=2.2, scale=0.4, rotate=-90] (clk_buf) {};
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% Connect CLK_IN to DDS clock buffers
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\draw [-latexslim] (ext_clk.east) -- ++(1,0);
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\draw [-latexslim] (mmcx.east) -- ++(1,0);
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\draw [-latexslim] (xo.east) -- ++(1,0);
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% Connect CPLD clk_sel to DDS clock buffers
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\draw [-latexslim] (clk_buf.east) -- ++(0,-0.42);
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% Signal path: From control signals / clock of DDS to output of the RF switches
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\draw (1.85, -1.75) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig0) {};
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\draw (1.85, -2.45) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig1) {};
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\draw (1.85, -3.15) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig2) {};
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\draw (1.85, -3.85) node[twoportshape, t={DDS Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.4] (sig3) {};
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% Extra node to expand the dotted area eastward
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\draw[color=white, text=black] (2.6, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=0.4, scale=0.4 ] (sig3_east) {};
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% Connect RF to DDS block
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\draw [latexslim-] (rf0.east) -- ++(1,0);
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\draw [latexslim-] (rf1.east) -- ++(1,0);
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\draw [latexslim-] (rf2.east) -- ++(1,0);
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\draw [latexslim-] (rf3.east) -- ++(1,0);
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% DDS signal path dotted area
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\node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(rf3)(sig0)(sig3_east.east)] (abs_dds) {};
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\node[fill=white, rotate=-90, scale=0.7] at (abs_dds.west) {DDS Channels};
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% CPLD
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\draw (3.8, -0.35) node[twoportshape, t={CPLD}, circuitikz/bipoles/twoport/width=1.1, scale=0.8, rotate=-90] (cpld) {};
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% Synthronization clock buffer for DDS block
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\draw (3.8, -2.5) node[twoportshape, t=\MymyLabel{Sync}{Buffer}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (sync_buf) {};
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% Connect CPLD to:
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% DDS clock buffer
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\draw [latexslim-] (clk_buf.north) -- (cpld.south);
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% DDS signal path
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\draw [latexslim-latexslim] (3.4, -0.7) -- ++ (-1.5, 0) -- ++ (0,-0.72);
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% Draw to intersection point, then complete the connection to sync buffer
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\draw [-] (4.2, -0.7) -- (4.55, -0.7) -- (4.55, -2.5);
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\draw [-latexslim] (4.55, -2.5) -- (sync_buf.east);
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% Connect sync buffer to DDS block
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\draw [-latexslim] (sig0.east) -- (3.65, -1.75) -- ++ (0, -0.5);
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\draw [-latexslim] (sync_buf.south) -- ++ (0, -0.3) -- ++ (-0.85, 0);
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% LVDS Transceivers
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\draw (6, 0) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds0) {};
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\draw (6, -0.7) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds1) {};
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\draw (6, -2.5) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds2) {};
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\draw (6, -3.2) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (lvds3) {};
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% Connect CPLD to transceivers
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\draw [latexslim-latexslim] (lvds0.west) -- ++ (-1.13, 0);
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\draw [latexslim-latexslim] (lvds1.west) -- ++ (-0.35, 0) -- ++ (0, 0.6) -- ++ (-0.78, 0);
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\draw [latexslim-latexslim] (lvds2.west) -- ++ (-0.45, 0) -- ++ (0, 2.3) -- ++ (-0.68, 0);
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\draw [latexslim-latexslim] (lvds3.west) -- ++ (-0.55, 0) -- ++ (0, 2.9) -- ++ (-0.58, 0);
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% EEPROMs
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\draw (6, -1.4) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (eeprom0) {};
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\draw (6, -3.9) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (eeprom1) {};
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% Repeaters for DDS0 sync clock & DDS sync output from sync buffer
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\draw (3.8, -3.85) node[twoportshape, t={Repeaters}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (rep) {};
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% Connect DDS0 to repeaters
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\draw [-latexslim] (sig0.east) -- ++ (0.3, 0) -- ++ (0, -1.55) -- (3.65, -3.3) -- ++ (0, -0.3);
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% Connect sync_buf to repeaters
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\draw [-latexslim] (sync_buf.south) -- ++ (0, -0.3) -- ++ (0.15, 0) -- ++ (0, -0.55);
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% EEMs
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\draw (8, -0.9) node[twoportshape, t={EEM Port 0}, circuitikz/bipoles/twoport/width=3.2, scale=0.5, rotate=-90] (eem0) {};
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\draw (8, -3.4) node[twoportshape, t={EEM Port 1}, circuitikz/bipoles/twoport/width=3.2, scale=0.5, rotate=-90] (eem1) {};
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% Connect LVDS and EEM
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\draw [latexslim-latexslim] (lvds0.east) -- (7.75, 0);
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\draw [latexslim-latexslim] (lvds1.east) -- (7.75, -0.7);
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\draw [latexslim-latexslim] (lvds2.east) -- (7.75, -2.5);
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\draw [latexslim-latexslim] (lvds3.east) -- (7.75, -3.2);
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% Connect EEPROM to EEM
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\draw [latexslim-latexslim] (eeprom0.east) -- (7.75, -1.4);
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\draw [latexslim-latexslim] (eeprom1.east) -- (7.75, -3.9);
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% Connect EEM0 to sync_buf
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\draw [latexslim-] (3.95, -2.25) -- (3.95, -1.85) -- (7.75, -1.85);
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% Connect repeaters output to EEM1
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\draw [-latexslim] (rep.south) -- (3.8, -4.35) -- (7.75, -4.35);
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\end{scope}
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\end{circuitikz}
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}
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\caption{Simplified Block Diagram}
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\end{figure}
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\begin{figure}[h]
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\centering
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\scalebox{0.88}{
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\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
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\begin{scope}[]
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% RF switches {0, 1, 2, 3} for SMA {0, 1, 2, 3}
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\draw (1.4, 0) node[twoportshape, t={RF Switch}, circuitikz/bipoles/twoport/width=1.5, scale=0.6] (sw) {};
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% Amplifiers {0, 1, 2, 3} for RF switches {0, 1, 2, 3}
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\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
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% Attenuators {0, 1, 2, 3} for amplifiers {0, 1, 2, 3}
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\draw (4.6, 0) node[twoportshape, t=\MymyLabel{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
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% DDS {0, 1, 2, 3} for attenuators {0, 1, 2, 3}
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\draw (6.6, 0) node[twoportshape, t={DDS}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (dds) {};
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% Connect main signal path
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\draw [-latexslim] (dds.west) -- (att.north);
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\draw [-latexslim] (att.south) -- (amp.west);
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\draw [-latexslim] (amp.east) -- (sw.east);
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% Connect abstract DDS clock input
|
||
|
|
\node [label=above:\tiny{CLK Buffers}] at (8, -0.2) {};
|
||
|
|
\draw [latexslim-] (dds.east) -- (8, 0);
|
||
|
|
|
||
|
|
% Insert CPLD signal to relevant components
|
||
|
|
\node [label=above:\tiny{CPLD}] at (8, 1.1) {};
|
||
|
|
\draw [-] (1.4, 1.3) -- (8, 1.3);
|
||
|
|
\draw [-latexslim] (1.4, 1.3) -- (sw.north);
|
||
|
|
\draw [-latexslim] (4.6, 1.3) -- (att.west);
|
||
|
|
\draw [-latexslim] (6.6, 1.3) -- (dds.north);
|
||
|
|
|
||
|
|
% Connect sync_buf signal to DDS
|
||
|
|
\draw [latexslim-] (6.9, -1.35) -- (6.9, -0.35);
|
||
|
|
\draw [-latexslim] (6.3, -1.35) -- (6.3, -0.35);
|
||
|
|
\node [label=below:\tiny{Sync Buffer /}] at (6.6, -1.15) {};
|
||
|
|
\node [label=below:\tiny{Repeaters}] at (6.6, -1.4) {};
|
||
|
|
\node [label={[rotate=-90]above:\tiny{DDS 0}}] at (6.8, -0.9) {};
|
||
|
|
\node [label={[rotate=-90]above:\tiny{Only}}] at (6.55, -0.9) {};
|
||
|
|
|
||
|
|
\end{scope}
|
||
|
|
|
||
|
|
\end{circuitikz}
|
||
|
|
}
|
||
|
|
|
||
|
|
\caption{Simplified DDS Signal Path}
|
||
|
|
\end{figure}
|
||
|
|
|
||
|
|
\begin{figure}[h]
|
||
|
|
\centering
|
||
|
|
\includegraphics[width=1.8in]{photo4410.jpg}
|
||
|
|
\caption{Urukul Card photo}
|
||
|
|
\end{figure}
|
||
|
|
|
||
|
|
% For wide tables, a single column layout is better. It can be switched
|
||
|
|
% page-by-page.
|
||
|
|
\onecolumn
|
||
|
|
|
||
|
|
\section{Electrical Specifications}
|
||
|
|
TODO
|
||
|
|
|
||
|
|
\section{Example ARTIQ code}
|
||
|
|
The sections below demonstrate simple usage scenarios of the 4410 Urukul card with the ARTIQ control system.
|
||
|
|
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
||
|
|
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
||
|
|
|
||
|
|
% Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
|
||
|
|
|
||
|
|
\subsection{10 MHz Sinusoidal Wave}
|
||
|
|
Both the CPLD and the DDS channels should be initialized.
|
||
|
|
|
||
|
|
\begin{minted}{python}
|
||
|
|
@kernel
|
||
|
|
def run(self):
|
||
|
|
self.core.reset()
|
||
|
|
self.cpld.init()
|
||
|
|
self.dds0.init()
|
||
|
|
self.dds0.cfg_sw(True)
|
||
|
|
self.dds0.set_att(6.)
|
||
|
|
self.dds0.set(10*MHz)
|
||
|
|
\end{minted}
|
||
|
|
|
||
|
|
If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized.
|
||
|
|
For example, synchronized RF signal can be produced on both channel 0 and channel 1 after configuring an appropriate phase mode.
|
||
|
|
\begin{minted}{python}
|
||
|
|
@kernel
|
||
|
|
def run(self):
|
||
|
|
self.core.reset()
|
||
|
|
self.cpld.init()
|
||
|
|
|
||
|
|
self.dds0.init()
|
||
|
|
self.dds0.cfg_sw(True)
|
||
|
|
self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
|
||
|
|
self.dds0.set_att(6.)
|
||
|
|
self.dds1.init()
|
||
|
|
self.dds1.cfg_sw(True)
|
||
|
|
self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
|
||
|
|
self.dds1.set_att(6.)
|
||
|
|
|
||
|
|
self.dds0.set(10*MHz)
|
||
|
|
self.dds1.set(10*MHz)
|
||
|
|
\end{minted}
|
||
|
|
|
||
|
|
\newpage
|
||
|
|
\subsection{DDS RAM Modulation}
|
||
|
|
Only available to AD9910 variants. Set field \texttt{dds} as an Urukul channel, \texttt{cpld} as the corresponding Urukul CPLD.
|
||
|
|
|
||
|
|
\begin{minted}{python}
|
||
|
|
from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP
|
||
|
|
|
||
|
|
@kernel
|
||
|
|
def run(self):
|
||
|
|
self.core.reset()
|
||
|
|
self.core.break_realtime()
|
||
|
|
self.cpld.init()
|
||
|
|
self.dds.init()
|
||
|
|
|
||
|
|
self.core.break_realtime()
|
||
|
|
self.profile0_set()
|
||
|
|
self.dds.set_att(6.)
|
||
|
|
self.dds.sw.on()
|
||
|
|
|
||
|
|
self.cpld.set_profile(0)
|
||
|
|
|
||
|
|
@kernel
|
||
|
|
def profile0_set(self):
|
||
|
|
self.dds.set_cfr1(ram_enable = 0)
|
||
|
|
self.cpld.set_profile(0)
|
||
|
|
amp_ram = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order
|
||
|
|
asf_ram = [0] * len(amp_ram)
|
||
|
|
self.dds.set_profile_ram(start=0, end=len(amp_ram)-1,
|
||
|
|
step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
|
||
|
|
self.cpld.io_update.pulse_mu(8)
|
||
|
|
self.dds.amplitude_to_ram(amp_ram, asf_ram)
|
||
|
|
self.dds.write_ram(asf_ram)
|
||
|
|
self.dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
|
||
|
|
self.dds.set_frequency(10*MHz)
|
||
|
|
self.cpld.io_update.pulse_mu(8)
|
||
|
|
\end{minted}
|
||
|
|
|
||
|
|
\section{Ordering Information}
|
||
|
|
To order, please visit \url{https://m-labs.hk} and select the 4410 Urukul in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
||
|
|
|
||
|
|
\section*{}
|
||
|
|
\vspace*{\fill}
|
||
|
|
|
||
|
|
\begin{footnotesize}
|
||
|
|
Information furnished by M-Labs Limited is believed to be accurate and reliable. However, no responsibility is assumed by M-Labs Limited for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
|
||
|
|
Specifications subject to change without notice.
|
||
|
|
\end{footnotesize}
|
||
|
|
|
||
|
|
\end{document}
|