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master
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fastino_fl
10
README.md
10
README.md
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@ -33,9 +33,7 @@ Tips for adding hardware instructions:
|
|||
for images with transparent background)
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||||
3. Add link to the new chapter to the `src/SUMMARY.md`
|
||||
4. Do not forget to tell about all hidden/non-obvious obstacles and pitfalls
|
||||
5. Avoid using uncommon, complex, or hard-to-understand words, phrases, or grammar (e.g., ❌constituent -> ✔️component).
|
||||
Keep in mind that these guides may be used by people with different backgrounds and levels of English proficiency.
|
||||
6. Add testing steps, even the "obvious" ones
|
||||
7. Add JSON sample if needed
|
||||
8. Add hardware setup (e.g. pins, switches) steps if needed
|
||||
9. View changed and added pages with `mdbook build` (see building instructions above)
|
||||
5. Add testing steps, even the "obvious" ones
|
||||
6. Add JSON sample if needed
|
||||
7. Add hardware setup (e.g. pins, switches) steps if needed
|
||||
8. View changed and added pages with `mdbook build` (see building instructions above)
|
||||
|
|
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|||
|
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@ -2,16 +2,16 @@
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|||
"nodes": {
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||||
"nixpkgs": {
|
||||
"locked": {
|
||||
"lastModified": 1710695816,
|
||||
"narHash": "sha256-3Eh7fhEID17pv9ZxrPwCLfqXnYP006RKzSs0JptsN84=",
|
||||
"lastModified": 1697851979,
|
||||
"narHash": "sha256-lJ8k4qkkwdvi+t/Xc6Fn74kUuobpu9ynPGxNZR6OwoA=",
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||||
"owner": "NixOS",
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||||
"repo": "nixpkgs",
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||||
"rev": "614b4613980a522ba49f0d194531beddbb7220d3",
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||||
"rev": "5550a85a087c04ddcace7f892b0bdc9d8bb080c8",
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||||
"type": "github"
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||||
},
|
||||
"original": {
|
||||
"owner": "NixOS",
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||||
"ref": "nixos-23.11",
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||||
"ref": "nixos-23.05",
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||||
"repo": "nixpkgs",
|
||||
"type": "github"
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||||
}
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||||
|
|
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|||
|
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@ -1,7 +1,7 @@
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|||
{
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||||
description = "Sinara assembly and test instructions";
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||||
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||||
inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-23.11;
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inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-23.05;
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||||
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||||
outputs = { self, nixpkgs }:
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||||
|
|
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@ -2,7 +2,6 @@
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||||
- [Build and test firmware](./build_test_firmware.md)
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- [Hardware](./hw/hardware.md)
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- [Sinara Kasli](./hw/kasli.md)
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- [Sinara Kasli-SOC](./hw/kasli_soc.md)
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- [Sinara 4624 AWG Phaser (Upconverter/Baseband)](./hw/phaser.md)
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- [Sinara 4456 synthesizer Mirny / Sinara 4457 Almazny Mezzanine card](./hw/mirny_almazny.md)
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@ -20,7 +19,6 @@
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- [Sinara 8451 Thermostat](./hw/thermostat.md)
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- [Sinara 2245 LVDS DIO](./hw/lvds_dio.md)
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- [Software/Support](./sw_sup/software_support.md)
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- [Starting with ARTIQ](./sw_sup/artiq_start.md)
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- [Building legacy firmware](./sw_sup/artiq_legacy.md)
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- [Networking](./sw_sup/networking.md)
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- [DRTIO](./sw_sup/drtio.md)
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@ -13,8 +13,8 @@
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"hw_rev": "vX.Y", // optional
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"ports": [<port num>],
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"edge_counter": <bool>,
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"bank_direction_low": "input", // or "output"
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"bank_direction_high": "output" // or "input"
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"bank_direction_low": "input",
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"bank_direction_high": "output"
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}
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```
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@ -4,11 +4,20 @@
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## JSON
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Not present in the JSON.
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Put the `ext_ref_frequency` field into the JSON description if the Kasli is going to use an external frequency:
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Peripherals typically should choose `"clk_sel": 2` for MMCX connection and `"clk_sel": 1` for external SMA connection.
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Refer to the [official docs](https://m-labs.hk/artiq/manual/core_drivers_reference.html) by searching for `clk_sel`.
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You may also need to add `"refclk": <number>` field to the target card.
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```json
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||||
{
|
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"hw_rev": "<hw rev>",
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"base": "<base>",
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||||
...
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||||
"ext_ref_frequency": <freq in Hz>,
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||||
...
|
||||
"peripherals": [...]
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||||
}
|
||||
```
|
||||
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||||
On peripherals you should choose `"clk_sel": 2` on connected devices.
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## Setup external clocker
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||||
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||||
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|
@ -32,12 +41,12 @@ Here is example setup for SynthNV RF signal generator:
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1. Switch `CLK SEL` pin to `EXT`/`INT` according to customer needs
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2. Connect MMCx cables according to the customer needs and boards specifications (see image below for reference):
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if the `INT` source is chosen, connect MMCx cable to `INT CLK`, otherwise connect external clocker to SMA `EXT CLK`
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3. Connect the Clocker to the Kasli via 30-pin ports, or via external power supply
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3. Connect the Clocker to the Kasli via 30-pin ports
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||||
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4. Connect the Clocker's SMA output to the Kasli's `CLK`/`CLK IN` SMA pin
|
||||
5. After assembling the crates and flashing the firmware, start Kasli and set config if needed:
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||||
5. After assembling the crates and flashing the firmware, start Kasli and write config as follows:
|
||||
`artiq_coremgmt config write -s rtio_clock ext0_bypass`. Please refer to the [official manual](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device)
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for the details and available options. In most cases you may skip this step.
|
||||
for the details and available options
|
||||
6. Reboot either via `artiq_coremgmt reboot` or via power supply if the board's firmware doesn't have such command
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## Testing
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@ -1,9 +0,0 @@
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# Kasli
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## Mounting fan onto heatsink
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1. ⚠️ Verify the fan has the **correct polarity (powering on with wrong polarity will burn the MOSFET in series💥)**
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2. Place the fan on a heatsink
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3. Tap 3 threads on the heatsink using M2.5 pointy tapping screws (e.g. front panel screws)
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4. Replace the tapping screws with M2.5x14mm screws
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5. Verify the fan is secure
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@ -5,12 +5,4 @@
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Check the BOOT mode switches - they both should be at SD if the Kasli-SoC going to be shipped to customer.
|
||||
POR jumper needs only for JTAG mode.
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||||
|
||||
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||||
|
||||
## Mounting fan onto heatsink
|
||||
|
||||
1. ⚠️ Verify the fan has the **correct polarity (powering on with wrong polarity will burn the MOSFET in series💥)**
|
||||
2. Place the fan on a heatsink
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||||
3. Tap 3 threads on the heatsink using M2.5 pointy tapping screws (e.g. front panel screws)
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||||
4. Replace the tapping screws with M2.5x14mm screws
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5. Verify the fan is secure
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||||
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||||
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@ -31,49 +31,8 @@ Be aware of the reversed EEM order on the card:
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|||
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||||
Switch DIPs in required position per each channel individually. Each RJ45 have 4 channels.
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||||
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||||
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||||
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||||
## Testing
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||||
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||||
```bash
|
||||
*** Testing TTL inputs.
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||||
TTL device to use as stimulus (default: ttl0): ttl0
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||||
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||||
Connect ttl0 to ttl4. Press ENTER when done.
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||||
|
||||
PASSED # <--------
|
||||
Connect ttl0 to ttl5. Press ENTER when done.
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||||
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||||
FAILED
|
||||
Connect ttl0 to ttl6. Press ENTER when done.
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||||
|
||||
FAILED
|
||||
Connect ttl0 to ttl7. Press ENTER when done.
|
||||
|
||||
FAILED
|
||||
...
|
||||
|
||||
*** Testing TTL inputs.
|
||||
TTL device to use as stimulus (default: ttl0): ttl1
|
||||
|
||||
Connect ttl1 to ttl4. Press ENTER when done.
|
||||
|
||||
FAILED
|
||||
Connect ttl1 to ttl5. Press ENTER when done.
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||||
|
||||
PASSED # <--------
|
||||
Connect ttl1 to ttl6. Press ENTER when done.
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||||
|
||||
FAILED
|
||||
Connect ttl1 to ttl7. Press ENTER when done.
|
||||
|
||||
FAILED
|
||||
...
|
||||
```
|
||||
1. Connect a RJ45 output port to a input port
|
||||
2. Run `artiq_sinara_tester`
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||||
3. One TTL will pass while other will fail
|
||||
4. Run `artiq_sinara_tester` again and increment the stimulus (e.g. `ttl0->ttl1->ttl2->ttl3`) until all channels on the input port passed at least once
|
||||
5. Plug into to another input port and repeat 2-4 until all input ports are tested
|
||||
|
||||
It is incompatible with other TTL cards, so you will need to use same or other LVDS card for proper testing.
|
||||
You can test channels by connecting Ethernet RJ45 cable. Since the artiq_sinara_tester allows to choose only one DIO
|
||||
port, you will need to run the test 4 times and choose different output source and track that every 4th is passing the test.
|
||||
It is also incompatible with other TTL cards, so you will need to use same or other LVDS card for proper testing.
|
||||
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|
@ -9,9 +9,7 @@
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|||
{
|
||||
"type": "mirny",
|
||||
"almazny": true, // for mirny with almazny only
|
||||
"ports": [<port num>],
|
||||
"clk_sel": 2, // optional
|
||||
"refclk": 125e6 // optional
|
||||
"ports": [<port num>]
|
||||
}
|
||||
```
|
||||
|
||||
|
|
@ -39,8 +37,8 @@ mirny0_ch3 info: {'f_outA': 1300000000.0, 'f_outB': 10400000000, 'output_divider
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|||
After running `artiq_sinara_test`:
|
||||
|
||||
1. Install gqrx `nix-shell -p gqrx`
|
||||
2. Connect HackRF One via USB cable only
|
||||
3. Run gqrx and choose `HackRF HackRF One...`
|
||||
2. Connect bladeRF via USB cable only
|
||||
3. Run gqrx and choose `BladeRF #<number>...`
|
||||
4. Default settings
|
||||
5. When gqrx loaded, start DSP processing with frequency at mirnyN_chM freq
|
||||
6. Connect the probe through attenuator to the Mirny's port
|
||||
|
|
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|||
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|
@ -25,9 +25,9 @@ phaser0 10+0 10+1 10+2 10+3 10+4 MHz
|
|||
### Upconverter
|
||||
|
||||
1. Install gqrx `nix-shell -p gqrx`
|
||||
2. Connect HackRF One via USB cable only
|
||||
3. Run gqrx and choose `HackRF HackRF One...`
|
||||
4. Default settings
|
||||
2. Connect bladeRF via USB cable only
|
||||
3. Run gqrx and choose `Nuand bladeRF SN <number>...`
|
||||
4. Input rate 20000000, other settings are default
|
||||
5. Lower the gain in `Input options`
|
||||
6. When gqrx loaded, start DSP processing with frequency near 2.875 GHz +- DUC frequencies from `artiq_sinara_test`
|
||||
in `Receiver Options`
|
||||
|
|
@ -39,7 +39,11 @@ phaser0 10+0 10+1 10+2 10+3 10+4 MHz
|
|||
|
||||
### Baseband
|
||||
|
||||
1. Connect the probe through attenuator to the Phaser's ports RF0 or RF1 (not the ADC)
|
||||
2. Find FTT (Fourier Transform) function in the oscilloscope
|
||||
3. Start processing with frequency near DUC frequencies from `artiq_sinara_test`
|
||||
4. You should see 5 tones on `artiq_sinara_test`'s frequencies
|
||||
1. Install gqrx `nix-shell -p gqrx`
|
||||
2. Connect bladeRF via USB cable only
|
||||
3. Run gqrx and choose `Nuand bladeRF SN <number>...`
|
||||
4. Input rate 15000000, other settings are default
|
||||
5. When gqrx loaded, start DSP processing with frequency near 2.875 GHz (???)
|
||||
6. Connect the probe through attenuator to the Phaser's ports RF0 or RF1 (not the ADC)
|
||||
7. You should see 5 tones on `artiq_sinara_test`'s frequencies (???):
|
||||
|
||||
|
|
|
|||
|
|
@ -32,5 +32,4 @@ PASSED
|
|||
|
||||
1. Apply 1.5V (connect the AA-battery) to the `samplerX`'s requested channel
|
||||
2. Press `Enter`, the `artiq_sinara_test` should output `PASSED`
|
||||
3. Repeat steps 1-2 for every available channel.
|
||||
4. Disassemble AA-battery tool as it risks getting corrosion
|
||||
3. Repeat steps 1-2 for every available channel.
|
||||
|
|
@ -4,76 +4,9 @@
|
|||
* [QUARTIQ Manual](https://quartiq.de/stabilizer/)
|
||||
* [Firmware](https://github.com/quartiq/stabilizer)
|
||||
|
||||
EEM is used for power only, and it can be alternatively powered by 12V barrel jack or PoE.
|
||||
|
||||
## JSON
|
||||
|
||||
Not present in the JSON.
|
||||
|
||||
## Building
|
||||
|
||||
Pick your poison - firmware version: older with Pounder support or newer with USB serial console - the first works with a hardcoded MQTT broker and (static or dynamic) IP address, the latter is configured like the booster - through a serial console.
|
||||
|
||||
There is no Nix Flake support to make things easier, so you need to set up rust and cargo manually. Start with cloning the stabilizer repository and opening a new shell with dfu-util (for flashing) and rustup (for building).
|
||||
|
||||
```
|
||||
nix-shell -p dfu-util rustup
|
||||
```
|
||||
|
||||
Set up the toolchain, this should be done only once:
|
||||
|
||||
```
|
||||
rustup target add thumbv7em-none-eabihf
|
||||
cargo install cargo-binutils
|
||||
rustup component add llvm-tools-preview
|
||||
rustup update
|
||||
rustup default stable
|
||||
```
|
||||
|
||||
Building the older version:
|
||||
|
||||
```
|
||||
BROKER="MQTT BROKER IP" cargo build --release
|
||||
BROKER="MQTT BROKER IP" cargo objcopy --release --bin dual-iir -- -O binary dual-iir.bin
|
||||
```
|
||||
|
||||
Building the newer version:
|
||||
|
||||
```
|
||||
cargo build --release
|
||||
cargo objcopy --release --bin dual-iir -- -O binary dual-iir.bin
|
||||
```
|
||||
|
||||
The newer version must be configured with USB console later (try ``help`` command first).
|
||||
|
||||
## Flashing
|
||||
|
||||
Once you have the binary (either built, or received from someone), you can now flash it.
|
||||
|
||||
Without firmware on the device or with older firmware, you need to use the jumper method:
|
||||
|
||||
1. Have the Stabilizer disconnected from power.
|
||||
2. Use a jumper of some sort to short BOOT pins on the board.
|
||||
3. Turn on the power.
|
||||
4. You can remove the jumper after few seconds.
|
||||
|
||||
With newer firmware with USB serial console:
|
||||
|
||||
1. Connect the Stabilizer to power.
|
||||
2. Connect USB cable to the Stabilizer.
|
||||
3. Connect with a serial console emulator, usually at ``/dev/ttyACM0``.
|
||||
4. Input ``platform dfu`` in the console.
|
||||
|
||||
And for both:
|
||||
|
||||
5. The device is now in DFU mode.
|
||||
6. Flash the device with the following command:
|
||||
|
||||
```
|
||||
dfu-util -a 0 -s 0x08000000:leave -R -D dual-iir.bin
|
||||
```
|
||||
|
||||
7. Look for "File downloaded successfully".
|
||||
No JSON modifications required.
|
||||
|
||||
## Testing
|
||||
|
||||
|
|
|
|||
|
|
@ -23,28 +23,6 @@ dfu-util -a 0 -s 0x08000000:leave -D thermostat.bin
|
|||
Then check that fans are working properly.
|
||||
You may also check fan controls via `fan` commands (see the firmware documentation).
|
||||
|
||||
## Test PID
|
||||
|
||||
1. For Zotino: connect 10-pins IDC 2.54mm FC cable from internal Thermostat connector to the Zotino TEC
|
||||
2. General TEC: connect external connector to the TEC
|
||||
3. Connect Ethernet and PSU
|
||||
4. Run:
|
||||
```shell
|
||||
git clone gitea@git.m-labs.hk:esavkin/thermostat.git
|
||||
cd thermostat
|
||||
git checkout zotino-tec
|
||||
nix develop
|
||||
python pytec/tec_qt.py
|
||||
```
|
||||
5. In `Output Config`, set limits:
|
||||
* `Max Cooling Current` - 400 mA
|
||||
* `Max Heating Current` - 400 mA
|
||||
* `Max Voltage Difference` - 1 V
|
||||
6. `PID Config` -> `PID Auto Tune` set desired target temperature, which should be slightly above your room temperature (+10C)
|
||||
7. Set `Thermistor Config` -> `B` and other values, according to the datasheet of the TEC module, for example for Zotino `B` is `3455 K`
|
||||
8. Run `PID Config` -> `PID Auto Tune` -> `Run` and check graphs that the measured temperature goes to the target temperature,
|
||||
and eventually stabilizes at +- 0.01 of the target
|
||||
|
||||
## Common problems
|
||||
|
||||
### Thermostat doesn't connect or doesn't enter DFU mode
|
||||
|
|
|
|||
|
|
@ -20,8 +20,7 @@
|
|||
|
||||
## Setup
|
||||
|
||||
Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clock source - either Clocker,
|
||||
Kasli or external via SMA.
|
||||
Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clocker source.
|
||||
|
||||
### Synchronization
|
||||
|
||||
|
|
@ -31,22 +30,6 @@ Synchronization requires Kasli and Urukul to be clocked from the same oscillator
|
|||
why this feature is disabled by default.
|
||||
There is no intrinsic impact on Urukul output phase noise and the synchronization process is quick and reliable when done correctly.
|
||||
|
||||
### One-EEM mode
|
||||
|
||||
Users may choose to use only one EEM port, if they want more cards to be in their crate. However following features
|
||||
will become unavailable:
|
||||
* SU-Servo
|
||||
* Low-latency RF switch control
|
||||
* Synchronization
|
||||
|
||||
RF switches are still available but the commands need to go over the SPI bus so it's higher-latency and lower-resolution.
|
||||
|
||||
### Urukul 4412
|
||||
|
||||
Urukul 4412 has higher frequency resolution (47 bit against 32 at Urukul 4410), however lacks such features:
|
||||
* SU-Servo
|
||||
* Synchronization
|
||||
|
||||
## Testing
|
||||
|
||||
After running `artiq_sinara_test`:
|
||||
|
|
@ -149,25 +132,4 @@ matches real clocker source.
|
|||
ValueError: Urukul AD9910 AUX_DAC mismatch
|
||||
```
|
||||
|
||||
Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description.
|
||||
|
||||
### Jagged signal with 1GHz external clock on AD9910
|
||||
|
||||
By default, on AD9910 external clock signal is divided by 4, while it should be not divided at all with PLL disabled.
|
||||
Change the ``clk_div`` parameter to the CPLD in the device_db file:
|
||||
|
||||
```python
|
||||
device_db["urukulX_cpld"] = {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.urukul",
|
||||
"class": "CPLD",
|
||||
"arguments": {
|
||||
"spi_device": "spi_urukul0",
|
||||
"sync_device": None,
|
||||
"io_update_device": "ttl_urukul0_io_update",
|
||||
"refclk": 1000000000.0,
|
||||
"clk_sel": 1,
|
||||
"clk_div" : 1 # <--- add this line
|
||||
}
|
||||
}
|
||||
```
|
||||
Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description.
|
||||
|
|
@ -20,7 +20,8 @@
|
|||
}
|
||||
```
|
||||
|
||||
Fastino uses one physical EEM channel, despite having two EEM ports.
|
||||
Fastino uses two physical EEM channels, but in the JSON file there should be only one channel specified,
|
||||
and it should be the one connected to Fastino's EEM0.
|
||||
|
||||
## Setup
|
||||
|
||||
|
|
@ -56,23 +57,18 @@ Press ENTER when done.
|
|||
This may happen when power-cycle is too short. Power down the crate, wait at least 30 seconds, and power up again.
|
||||
[Issue](https://github.com/sinara-hw/Zotino/issues/37).
|
||||
|
||||
### Zero/meaningless voltage output on Fastino
|
||||
### Zero voltage output on Fastino
|
||||
|
||||
Some Fastino may not output any meaningful voltage during testing, usually that means it has no gateware flashed.
|
||||
Some Fastino may not output any voltage during testing, usually that means it has no gateware.
|
||||
|
||||
Another common symptom of no gateware is that no LEDs are lit up. Whereas if the gateware has been flashed, the PG and FD LEDs will be lit green.
|
||||
|
||||
You can flash the gateware with a Kasli/Kasli-SoC, be it in the crate or standalone (no specific gateware needed for Kasli/SoC):
|
||||
You can flash the gateware with a standalone Kasli/Kasli-SoC:
|
||||
|
||||
1. Download the latest `fastino.bin` release from [quartiq/fastino](https://github.com/quartiq/fastino/releases).
|
||||
2. Run `git clone https://github.com/quartiq/kasli-i2c.git` and place `fastino.bin` in the kasli-i2c directory.
|
||||
3. Connect the Fastino's EEM0 to any available Kasli/Kasli-SoC EEM port ([**do not hot-plug**](../build_test_firmware.md#operating-hints-and-warnings)).
|
||||
You may skip this step if Fastino is connected within a crate.
|
||||
4. Power on the standalone Kasli/Kasli-SoC and connect it to the PC via data micro-USB.
|
||||
5. Run `nix-shell -p python311Packages.pyftdi`.
|
||||
6. Run `cd kasli-i2c; python flash_fastino.py 0 EEM<number> write fastino.bin` where `<number>` is the EEM port number on the Kasli/Kasli-SoC side.
|
||||
7. If PG and FD LEDs are lit green, the Fastino is ready.
|
||||
|
||||
### Fastino output is 10V
|
||||
|
||||
Fastinos by default after power up output 10V on all channels if not driven by the test otherwise. Make sure the EEM ports are specified correctly in the JSON and the EEM cable is connected to EEM0 on the Fastino.
|
||||
1. Download the latest `fastino.bin` release from [quartiq/fastino](https://github.com/quartiq/fastino/releases)
|
||||
2. Run `git clone https://github.com/quartiq/kasli-i2c.git` and place `fastino.bin` in the kasli-i2c directory
|
||||
2. Connect the Fastino's EEM0 to any available Kasli/Kasli-SoC EEM port (**do not hot-plug**)
|
||||
3. Power on the standalone Kasli/Kasli-SoC
|
||||
4. Run `nix-shell -p python311Packages.pyftdi`
|
||||
5. Run `cd kasli-i2c; python flash_fastino.py 0 EEM<number> write fastino.bin` where `<number>` is the EEM port number on the Kasli/Kasli-SoC side
|
||||
6. If PG and FD LEDs are lit green, the Fastino is ready.
|
||||
|
|
|
|||
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|
|
@ -1,38 +0,0 @@
|
|||
# Starting with ARTIQ
|
||||
|
||||
This page describes how to start with ARTIQ system for novice users.
|
||||
|
||||
## Connecting wires
|
||||
|
||||
In most cases the system is shipped with power bricks (PSU), DC splitters and SFPs enough to power and control the whole system.
|
||||
Connect them in following order:
|
||||
1. Insert Ethernet SFP into the SFP0 of the master or standalone Kasli/Kasli-SoC (Carrier)
|
||||
2. Connect these SFPs to the router or PC via Ethernet cable (in some cases, optical cable)
|
||||
3. Insert optic/direct attach SFPs into the master and satellite Carriers, respective to the numeration, [more info in DRTIO page](drtio.md)
|
||||
4. Power on PSU or EEM power module, by inserting C14 cable, attach DC splitters if available
|
||||
5. Some cards may have "External power" setting (check the quotation), in this case, insert DC connector into the port
|
||||
6. Insert remaining cables into the Carriers (not applicable in case of EEM Power Module).
|
||||
|
||||
## Set the network
|
||||
|
||||
By default standalone/master Carriers arrive with 192.168.1.75/24 set as their static address. Carrier will try to acquire this address
|
||||
from your router, and in case of failure, they will be just unavailable from the network. Check the following articles for troubleshooting network issues:
|
||||
* [Networking](networking.md)
|
||||
* [Official docs](https://m-labs.hk/artiq/manual/installing.html#setting-up-the-core-device-ip-networking)
|
||||
|
||||
## Run first experiment via artiq_run
|
||||
|
||||
Before diving in to the repository experiments management and scheduling, it is essential to try run your first experiment
|
||||
via most basic way - `artiq_run`. For this you need to enter your ARTIQ environment (console) and run:
|
||||
```shell
|
||||
artiq_run --device-db path/to/device_db.py path/to/experiment.py
|
||||
```
|
||||
|
||||
In case your directory contains relevant `device_db` file, you may omit the `--device-db path/to/device_db.py` part.
|
||||
To check this, you may run `ls .` and check if it is in the list.
|
||||
|
||||
On pre-installed NUCs, the ARTIQ commands are available everywhere, and you just need to run them.
|
||||
If you have Nix package manager or NixOS, you will just need to enter the shell with `nix develop github:m-labs/artiq\?ref=release-7`.
|
||||
If you have installed ARTIQ with Conda, you will need to activate the environment with `conda activate <name of the environment with ARTIQ>`.
|
||||
|
||||
You may check for experiments in the [official docs](https://m-labs.hk/artiq/manual/getting_started_core.html).
|
||||
|
|
@ -45,9 +45,3 @@ During the connection, the clock signal is being distributed, effectively making
|
|||
* Wrong setups - master to master, standalone to standalone. Messing up with SFP ports generally makes it unusable,
|
||||
but the connection should be established in most cases.
|
||||
* The fiber adapters are not symmetrical - if one end has 1270/1330 label, another one should be 1330/1270.
|
||||
|
||||
|
||||
### Master-satellite interrupted/unstable connection
|
||||
|
||||
This often happens due to overheating issues. Check if the Kasli/SoC fans are working properly and
|
||||
try installing rack fans to increase the air flow.
|
||||
Loading…
Reference in New Issue