README.md

@@ -33,9 +33,7 @@ Tips for adding hardware instructions:
    for images with transparent background)
 3. Add link to the new chapter to the `src/SUMMARY.md`
 4. Do not forget to tell about all hidden/non-obvious obstacles and pitfalls
-5. Avoid using uncommon, complex, or hard-to-understand words, phrases, or grammar (e.g., ❌constituent -> ✔️component).
+5. Add testing steps, even the "obvious" ones
-   Keep in mind that these guides may be used by people with different backgrounds and levels of English proficiency.
+6. Add JSON sample if needed
-6. Add testing steps, even the "obvious" ones
+7. Add hardware setup (e.g. pins, switches) steps if needed
-7. Add JSON sample if needed
+8. View changed and added pages with `mdbook build` (see building instructions above)
-8. Add hardware setup (e.g. pins, switches) steps if needed
-9. View changed and added pages with `mdbook build` (see building instructions above)

flake.lock

@@ -2,16 +2,16 @@
   "nodes": {
     "nixpkgs": {
       "locked": {
-        "lastModified": 1710695816,
+        "lastModified": 1697851979,
-        "narHash": "sha256-3Eh7fhEID17pv9ZxrPwCLfqXnYP006RKzSs0JptsN84=",
+        "narHash": "sha256-lJ8k4qkkwdvi+t/Xc6Fn74kUuobpu9ynPGxNZR6OwoA=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "614b4613980a522ba49f0d194531beddbb7220d3",
+        "rev": "5550a85a087c04ddcace7f892b0bdc9d8bb080c8",
         "type": "github"
       },
       "original": {
         "owner": "NixOS",
-        "ref": "nixos-23.11",
+        "ref": "nixos-23.05",
         "repo": "nixpkgs",
         "type": "github"
       }

flake.nix

@@ -1,7 +1,7 @@
 {
     description = "Sinara assembly and test instructions";
 
-    inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-23.11;
+    inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-23.05;
 
     outputs = { self, nixpkgs }:
 

src/SUMMARY.md

@@ -2,7 +2,6 @@
 
 - [Build and test firmware](./build_test_firmware.md)
 - [Hardware](./hw/hardware.md)
-  - [Sinara Kasli](./hw/kasli.md)
   - [Sinara Kasli-SOC](./hw/kasli_soc.md)
   - [Sinara 4624 AWG Phaser (Upconverter/Baseband)](./hw/phaser.md)
   - [Sinara 4456 synthesizer Mirny / Sinara 4457 Almazny Mezzanine card](./hw/mirny_almazny.md)
@@ -10,7 +9,6 @@
   - [Sinara 2118 BNC-TTL / 2128 SMA-TTL](./hw/bnc_sma_ttl.md)
   - [Sinara 2138 MCX-TTL](./hw/mcx_ttl.md)
   - [Sinara 5432 DAC Zotino / Sinara 5632 DAC Fastino](./hw/zotino_fastino.md)
-  - [Sinara 5716 DAC Shuttler](./hw/shuttler.md)
   - [Sinara 5518 BNC-IDC / 5528 SMA-IDC adapter](./hw/bnc_sma_idc_adapter.md)
   - [Sinara 4410/4412 DDS Urukul (AD9910/AD9912)](./hw/urukul.md)
   - [Sinara 5108 Sampler](./hw/sampler.md)
@@ -19,14 +17,10 @@
   - [Sinara 8452 DSP Stabilizer](./hw/stabilizer.md)
   - [Sinara 9805 RF Power Amplifier Booster](./hw/booster.md)
   - [Sinara 8451 Thermostat](./hw/thermostat.md)
-  - [Sinara 2245 LVDS DIO](./hw/lvds_dio.md)
 - [Software/Support](./sw_sup/software_support.md)
-  - [Starting with ARTIQ](./sw_sup/artiq_start.md)
   - [Building legacy firmware](./sw_sup/artiq_legacy.md)
   - [Networking](./sw_sup/networking.md)
   - [DRTIO](./sw_sup/drtio.md)
   - [UART Logs](./sw_sup/uart_logs.md)
   - [Flashing the Firmware](./sw_sup/flashing_firmware.md)
   - [Moninj](./sw_sup/moninj.md)
-  - [Clocking](sw_sup/clocking.md)
-  - [device_db.py](sw_sup/device_db.md)

src/build_test_firmware.md

@@ -14,17 +14,6 @@
 
 Failure to comply with this voids the warranty.
 
-## Shipping hints and warnings
-
-* 🙆 Leave the cards in the crate
-* 🙆 Ensure screws are tight
-* 🙆 Ensure cards are in card guides
-* ⚠️ Remove any cables from front panels
-* ⚠️ Remove SFP adapters and insert caps/stubs
-* 💁 Also advised to put caps on SMA connectors
-* ✅ Wrap each crate in the bubble wrap individually until you don't feel the edges of the crate (usually 10 layers of standard buble wrap)
-* 🈁 Fill in the space around the crate in the box with foamy stuff
-
 ## Kasli standalone
 
 ### Checklist
@@ -39,18 +28,13 @@ Failure to comply with this voids the warranty.
 ```shell
 mkdir <variant>
 cd <variant>/
-#nix develop github:m-labs/artiq\?ref=release-8 # not working https://github.com/m-labs/artiq/issues/2439
+nix develop github:m-labs/artiq\?ref=release-7
-git clone https://github.com/m-labs/artiq.git
-cd artiq
-git checkout release-8
 # master/standalone only
 artiq_mkfs -s ip 192.168.1.75 kasli.config
 artiq_flash storage -f kasli.config
 artiq_ddb_template -o device_db.py <variant>.json 
-python -m artiq.gateware.targets.kasli <variant>.json 
+python -m artiq.gateware.targets.kasli_generic <variant>.json 
 artiq_flash --srcbuild -d artiq_kasli/<variant>/
-artiq_rtiomap dev_map.bin
-artiq_coremgmt config write -f device_map dev_map.bin
 ```
 
 ## Kasli-SoC (zynq)
@@ -70,18 +54,15 @@ artiq_coremgmt config write -f device_map dev_map.bin
 ```shell
 mkdir <variant>
 cd <variant>/
-nix develop git+https://git.m-labs.hk/m-labs/artiq-zynq\?ref=release-8
+nix develop git+https://git.m-labs.hk/m-labs/artiq-zynq\?ref=release-7
 artiq_ddb_template -o device_db.py <variant>.json 
-nix build -L --impure --expr 'let fl = builtins.getFlake "git+https://git.m-labs.hk/m-labs/artiq-zynq?ref=release-8"; in (fl.makeArtiqZynqPackage {target="kasli_soc"; variant="[master, standalone, satellite]"; json=<full path to the json description>;}).kasli_soc-[master, standalone, satellite]-sd' 
+nix build -L --impure --expr 'let fl = builtins.getFlake "git+https://git.m-labs.hk/m-labs/artiq-zynq?ref=release-7"; in (fl.makeArtiqZynqPackage {target="kasli_soc"; variant="[master, standalone, satellite]"; json=<full path to the json description>;}).kasli_soc-[master, standalone, satellite]-sd' 
 # copy `results/boot.bin` to the SD card
 # insert SD card to the Kasli-SoC and boot
 artiq_coremgmt -D 192.168.1.56 config write -s ip 192.168.1.75 # or just place extra/CONFIG.TXT near the boot.bin on SD card
 # update firmware (alternative to copy to SD, if ARTIQ already running)
 artiq_coremgmt config write -f boot result/boot.bin
-artiq_coremgmt reboot
 # reboot via power supply
-artiq_rtiomap dev_map.bin
-artiq_coremgmt config write -f device_map dev_map.bin
 ```
 
 ## Testing (common)

src/extra/CONFIG.TXT

@@ -1,2 +1 @@
 ip=192.168.1.75
-rtio_clock=int_125

src/hw/bnc_sma_ttl.md

@@ -13,8 +13,8 @@
   "hw_rev": "vX.Y", // optional
   "ports": [<port num>],
   "edge_counter": <bool>,
-  "bank_direction_low": "input", // or "output"
+  "bank_direction_low": "input",
-  "bank_direction_high": "output" // or "input"
+  "bank_direction_high": "output"
 }
 ```
 

src/hw/booster.md

@@ -8,40 +8,9 @@
 
 ### Flashing
 
-#### Easier way
-
-Download and unpack the [booster firmware](../extra/booster/booster0.5.0.tar.xz), and then:
-```shell
-nix-shell -p dfu-util
-dfu-util -a 0 -s 0x08000000:leave --download booster0.5.0.bin
-```
-
-#### Build from source on Fedora 38
-
-Creating proper Nix shell for updated Rust is quite troublesome, so the faster way is actually to use any
-classic Linux distribution:
-
-```shell
-git clone https://github.com/quartiq/booster.git # download sources
-sudo dnf install clang dfu-util
-cd booster/
-curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh # install Rust, we need rustup
-rustup target add thumbv7em-none-eabihf
-cargo install cargo-binutils
-rustup component add llvm-tools-preview
-cargo build --release
-cargo objcopy --release -- -O binary booster.bin
-# enter dfu mode by either serial terminal or
-# press `DFU Bootloader` button while rebooting
-dfu-util -a 0 -s 0x08000000:leave --download booster.bin
-```
-
-#### For version before September 2023 on NixOS
-
 ```shell
 git clone git@github.com:quartiq/booster.git
 cd booster
-git checkout a1f83b63180511ecd68f88a04621624941d17a41 # or earlier
 nix-shell -p rustup cargo rustc dfu-util
 rustup target add thumbv7em-none-eabihf
 cargo install cargo-binutils
@@ -63,7 +32,7 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
     ```
 3. `mosquitto -c mosquitto.conf -d`
 4. Run `cutecom`
-5. Connect to the Booster via `/dev/ttyACMX` port, baud 9600, switch from LF to CR on newer version
+5. Connect to the Booster via `/dev/ttyACMX` port, baud 9600
 6. Send `help` command to check if it works
 7. Enter commands (change details if necessary):
     ```shell
@@ -75,13 +44,6 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
     # apply changes and wait until it fully rebooted
     reset
     ```
-   Newer version:
-   ```shell
-    write broker "192.168.1.123"
-    write ip "192.168.1.75"
-    # apply changes and wait until it fully rebooted
-    reset
-    ```
 8. Check the Booster connects to your broker.
 9. Download AppImage from [MQTT Explorer](https://mqtt-explorer.com/)
 10. Run it with `appimage-run /path/to/MQTT-Explorer-XXX.AppImage`
@@ -90,20 +52,15 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
 
 ## Calibration
 
-1. Assemble Kasli with one Urukul, build and flash firmware for it with [booster.json](../extra/booster/booster.json)
+1. Assemble Kasli with one Urukul, build and flash firmware for it with [booster.json](../extra/booster.json)
-2. Run [dds_for_booster.py](../extra/booster/dds_for_booster.py) experiment once
+2. Run [dds_for_booster.py](../extra/dds_for_booster.py) experiment once
 3. Attach parallel 50 Ohm load to the oscilloscope, as shown on the picture: ![](../img/50ohm_parallel_load.jpg),
 4. Configure oscilloscope for 1M Ohm impedance
 5. Attach attenuator to the Urukul's RF2
 6. `cd py/`
-7. You may also need to download or install python's `gmqtt` and `miniconf`:
+7. You may also need to download or install python's `gmqtt` and `miniconf`
-   ```shell
-   python -m venv env
-   source env/bin/activate.fish
-   pip install git+https://github.com/quartiq/miniconf.git@84cc9046bf504cc2d0d33b84d2f3133f2faf2248#subdirectory=py/miniconf-mqtt
-   ```
 8. Enable channels: `python -m booster --broker 192.168.1.123 --prefix dt/sinara/booster/xx-xx-xx-xx-xx-xx --channel N tune=0.1`
-9. Using [booster_template](../extra/booster/booster_template.ods) fill in `y0`, `y1`, `m`, `c`, values using instructions below
+9. Using [booster_template](../extra/booster_template.ods) fill in `y0`, `y1`, `m`, `c`, values using instructions below
 10. Update settings with the adjusted values
 11. Save settings with `python -m booster --broker 192.168.1.123 --prefix dt/sinara/booster/xx-xx-xx-xx-xx-xx --channel N save`
 12. Reboot and check settings are applied

src/hw/clocker.md

@@ -4,11 +4,20 @@
 
 ## JSON
 
-Not present in the JSON.
+Put the `ext_ref_frequency` field into the JSON description if the Kasli is going to use an external frequency:
 
-Peripherals typically should choose `"clk_sel": 2` for MMCX connection and `"clk_sel": 1` for external SMA connection.
+```json
-Refer to the [official docs](https://m-labs.hk/artiq/manual/core_drivers_reference.html) by searching for `clk_sel`.
+{
-You may also need to add `"refclk": <number>` field to the target card.
+  "hw_rev": "<hw rev>",
+  "base": "<base>",
+  ...
+  "ext_ref_frequency": <freq in Hz>,
+  ...
+  "peripherals": [...]
+}
+```
+
+On peripherals you should choose `"clk_sel": 2` on connected devices.
 
 ## Setup external clocker
 
@@ -32,12 +41,12 @@ Here is example setup for SynthNV RF signal generator:
 1. Switch `CLK SEL` pin to `EXT`/`INT` according to customer needs
 2. Connect MMCx cables according to the customer needs and boards specifications (see image below for reference): 
    if the `INT` source is chosen, connect MMCx cable to `INT CLK`, otherwise connect external clocker to SMA `EXT CLK` 
-3. Connect the Clocker to the Kasli via 30-pin ports, or via external power supply
+3. Connect the Clocker to the Kasli via 30-pin ports
    ![](../img/clocker_ref.jpg)
 4. Connect the Clocker's SMA output to the Kasli's `CLK`/`CLK IN` SMA pin
-5. After assembling the crates and flashing the firmware, start Kasli and set config if needed:
+5. After assembling the crates and flashing the firmware, start Kasli and write config as follows:
    `artiq_coremgmt config write -s rtio_clock ext0_bypass`. Please refer to the [official manual](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device)
-   for the details and available options. In most cases you may skip this step.
+   for the details and available options
 6. Reboot either via `artiq_coremgmt reboot` or via power supply if the board's firmware doesn't have such command
 
 ## Testing

src/hw/kasli.md

@@ -1,9 +0,0 @@
-# Kasli
-
-## Mounting fan onto heatsink
-![](../img/kasli_fan.jpg)
-1. ⚠️ Verify the fan has the **correct polarity (powering on with wrong polarity will burn the MOSFET in series💥)**
-2. Place the fan on a heatsink
-3. Tap 3 threads on the heatsink using M2.5 pointy tapping screws (e.g. front panel screws)
-4. Replace the tapping screws with M2.5x14mm screws
-5. Verify the fan is secure

src/hw/kasli_soc.md

@@ -5,12 +5,4 @@
 Check the BOOT mode switches - they both should be at SD if the Kasli-SoC going to be shipped to customer.
 POR jumper needs only for JTAG mode.
 
-![](../img/kasli_soc.jpg)
+![](../img/kasli_soc.jpg)
-
-## Mounting fan onto heatsink
-![](../img/kasli_soc_fan.jpg)
-1. ⚠️ Verify the fan has the **correct polarity (powering on with wrong polarity will burn the MOSFET in series💥)**
-2. Place the fan on a heatsink
-3. Tap 3 threads on the heatsink using M2.5 pointy tapping screws (e.g. front panel screws)
-4. Replace the tapping screws with M2.5x14mm screws
-5. Verify the fan is secure

src/hw/lvds_dio.md

@@ -1,79 +0,0 @@
-# Sinara 2245 LVDS DIO card
-
-* [Wiki](https://github.com/sinara-hw/DIO_LVDS_RJ45/wiki)
-* [Datasheet](https://m-labs.hk/docs/sinara-datasheets/2245.pdf)
-
-## JSON
-
-Be aware of the reversed EEM order on the card:
-
-```json
-[
-  {
-    "type": "dio",
-    "board": "DIO_LVDS",
-    "ports": [1],
-    "bank_direction_low": "input",
-    "bank_direction_high": "input",
-    "edge_counter": false // or true
-  }, 
-  {
-    "type": "dio",
-    "board": "DIO_LVDS",
-    "ports": [0],
-    "bank_direction_low": "output",
-    "bank_direction_high": "output"
-  }
-]
-```
-
-## Setup
-
-Switch DIPs in required position per each channel individually. Each RJ45 have 4 channels.
-
-![](../img/lvds_ttl_switches.jpg)
-
-## Testing
-
-```bash
-*** Testing TTL inputs.
-TTL device to use as stimulus (default: ttl0): ttl0
-
-Connect ttl0 to ttl4. Press ENTER when done.
-
-PASSED  # <--------
-Connect ttl0 to ttl5. Press ENTER when done.
-
-FAILED
-Connect ttl0 to ttl6. Press ENTER when done.
-
-FAILED
-Connect ttl0 to ttl7. Press ENTER when done.
-
-FAILED
-...
-
-*** Testing TTL inputs.
-TTL device to use as stimulus (default: ttl0): ttl1
-
-Connect ttl1 to ttl4. Press ENTER when done.
-
-FAILED
-Connect ttl1 to ttl5. Press ENTER when done.
-
-PASSED  # <--------
-Connect ttl1 to ttl6. Press ENTER when done.
-
-FAILED
-Connect ttl1 to ttl7. Press ENTER when done.
-
-FAILED
-...
-```
-1. Connect a RJ45 output port to a input port
-2. Run `artiq_sinara_tester`  
-3. One TTL will pass while other will fail
-4. Run `artiq_sinara_tester` again and increment the stimulus (e.g. `ttl0->ttl1->ttl2->ttl3`) until all channels on the input port passed at least once
-5. Plug into to another input port and repeat 2-4 until all input ports are tested
-
-It is incompatible with other TTL cards, so you will need to use same or other LVDS card for proper testing.

src/hw/mirny_almazny.md

@@ -9,65 +9,10 @@
 {
   "type": "mirny",
   "almazny": true, // for mirny with almazny only 
-  "ports": [<port num>],
+  "ports": [<port num>]
-  "clk_sel": 2, // optional
-  "refclk": 125e6 // optional
 }
 ```
 
-## Getting the firmware
-
-On Hydra you can find [Mirny 0.3.1 firmware](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-almazny). It contains a single ``.jed`` file that can be flashed following [flashing instructions](#flashing). This firmware supports Almazny v1.2+.
-
-If you are using a legacy Almazny (v1.0-1.1), due to different signals routed, you need to flash the older [0.2.4 firmware with Almazny support](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-legacy-almazny).
-
-### Building firmware (optional)
-
-However, if you need to make chances or build from source, follow these instructions.
-
-Once you get your hands on the firmware source code, you will need to work around few shortcomings of Nix, mainly not being able to run dynamically linked executables.
-
-You will need:
-- Xilinx ISE 14.7 installed on your system (this guide is assuming ``/opt/Xilinx`` path),
-- an environment with Migen.
-
-One way to do it is to create an FHS environment, like ARTIQ does for Vivado, within ARTIQ's ``flake.nix`` (to leverage Migen already being there), by adding these lines:
-
-```
-iseEnv = pkgs.buildFHSEnv {
-  name = "ise-env";
-  targetPkgs = vivadoDeps;
-};
-
-ise = pkgs.buildFHSEnv {
-  name = "ise";
-  targetPkgs = vivadoDeps;
-  profile = "set -e; source /opt/Xilinx/14.7/ISE_DS/settings64.sh";
-  runScript = "ise";
-};
-```
-
-Add them below ``vivadoEnv``. Then add ``iseEnv`` and ``ise`` to the dev shell's build inputs. Call ``nix develop`` on that.
-
-Then you can build Mirny:
-
-```shell
-nix develop
-ise-env
-cd ../mirny  # or wherever your source is at
-source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-python mirny_impl.py
-```
-
-### Flashing
-
-For flashing, you will need Xilinx ISE 14.7 installed on your system (here assuming ``/opt/Xilinx`` path), and ``xc3sprog`` with the appropriate HS2 JTAG adapter.
-
-```shell
-nix-shell -p xc3sprog
-xc3sprog -c jtaghs2 -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed
-```
-
 ## Testing
 
 ### Without Almazny
@@ -92,8 +37,8 @@ mirny0_ch3 info: {'f_outA': 1300000000.0, 'f_outB': 10400000000, 'output_divider
 After running `artiq_sinara_test`:
 
 1. Install gqrx `nix-shell -p gqrx`
-2. Connect HackRF One via USB cable only
+2. Connect bladeRF via USB cable only
-3. Run gqrx and choose `HackRF HackRF One...`
+3. Run gqrx and choose `BladeRF #<number>...`
 4. Default settings
 5. When gqrx loaded, start DSP processing with frequency at mirnyN_chM freq
 6. Connect the probe through attenuator to the Mirny's port
@@ -102,7 +47,7 @@ After running `artiq_sinara_test`:
 
 ![](../img/mirny_gqrx.png)
 
-### With Almazny (ARTIQ 7)
+### With Almazny
 
 At first, `artiq_sinara_test` will prompt you for testing Mirnies as the would be without Almazny.
 After that, it will prompt you with testing the Almazny:
@@ -150,8 +95,4 @@ You should also see differences in various modes, but that may require disabling
 
 ### Tips
 
-~~Mirnies often fail `ValueError: MUXOUT not high`, in that case restart the tests or reboot the board(s).~~ - fixed in [9569cfb](https://github.com/m-labs/artiq/commit/9569cfb26329c0acdc1705d3256d2506b7bccce5)
+Mirnies often fail `ValueError: MUXOUT not high`, in that case restart the tests or reboot the board(s).
-
-For Almazny v1.0 and 1.1 support, CPLD firmware 0.2.4 (linked above) must be flashed onto Mirny.
-
-For Almazny v1.2+ support, CPLD firmware 0.3.1+ (with fixes) must be flashed onto Mirny.

src/hw/phaser.md

@@ -25,9 +25,9 @@ phaser0 10+0 10+1 10+2 10+3 10+4 MHz
 ### Upconverter
 
 1. Install gqrx `nix-shell -p gqrx`
-2. Connect HackRF One via USB cable only
+2. Connect bladeRF via USB cable only
-3. Run gqrx and choose `HackRF HackRF One...`
+3. Run gqrx and choose `Nuand bladeRF SN <number>...`
-4. Default settings
+4. Input rate 20000000, other settings are default
 5. Lower the gain in `Input options`
 6. When gqrx loaded, start DSP processing with frequency near 2.875 GHz +- DUC frequencies from `artiq_sinara_test`
    in `Receiver Options`
@@ -39,7 +39,11 @@ phaser0 10+0 10+1 10+2 10+3 10+4 MHz
 
 ### Baseband
 
-1. Connect the probe through attenuator to the Phaser's ports RF0 or RF1 (not the ADC)
+1. Install gqrx `nix-shell -p gqrx`
-2. Find FTT (Fourier Transform) function in the oscilloscope
+2. Connect bladeRF via USB cable only
-3. Start processing with frequency near DUC frequencies from `artiq_sinara_test`
+3. Run gqrx and choose `Nuand bladeRF SN <number>...`
-4. You should see 5 tones on `artiq_sinara_test`'s frequencies
+4. Input rate 15000000, other settings are default
+5. When gqrx loaded, start DSP processing with frequency near 2.875 GHz (???)
+6. Connect the probe through attenuator to the Phaser's ports RF0 or RF1 (not the ADC)
+7. You should see 5 tones on `artiq_sinara_test`'s frequencies (???):
+   ![phaser_baseband.png](../img/phaser_baseband.png)

src/hw/sampler.md

@@ -32,5 +32,4 @@ PASSED
 
 1. Apply 1.5V (connect the AA-battery) to the `samplerX`'s requested channel
 2. Press `Enter`, the `artiq_sinara_test` should output `PASSED`
-3. Repeat steps 1-2 for every available channel.
+3. Repeat steps 1-2 for every available channel.
-4. Disassemble AA-battery tool as it risks getting corrosion

src/hw/shuttler.md

@@ -1,120 +0,0 @@
-# Sinara 5716 DAC Shuttler
-
-The Sinara 5716 DAC Shuttler consists of the [Shuttler](https://github.com/sinara-hw/Shuttler), [Remote AFE-Board](https://github.com/sinara-hw/Shuttler), and [EEM FMC Carrier](https://github.com/sinara-hw/EEM_FMC_Carrier) (EFC) Board. 
-
-The EFC Board has an FPGA running Kasli Satellite. DRTIO communication is established through the EEM Cable. At first power up, EFC Board and connected Kasli/Kasli-soc calibrate the clock skews on their own EEM transceiver and then store the value into the flash memory/SD Card.
-
-## JSON
-
-```json
-{
-    "type": "shuttler",
-    "ports": [<port num>]
-}
-```
-
-## Hardware Configurations and Connections
-### EEM Cable Connection 
-
-Only the EEM0 port on the EFC board is used. The EEM Cable provides power. You can ignore the barrel jack at the back of the board if it is placed.
-
-### CLK Input
-
-The EFC requires a **common** clock source with the connected device.
-
-For the EFC Board v1.0, please refer to this [issue](https://github.com/sinara-hw/EEM_FMC_Carrier/issues/44).
-
-For the EFC Board v1.1 (or later), there is a DIP switch to select the clock source.
-![efc_clk_sel](../img/efc_clk_sel.png)
-
-| Clock Source | CLK_SEL0 | CLK_SEL1 |
-|---|---|---|
-| Front Panel SMA | 0 | 0 |
-| Internal Oscillator(default) | 1 | 0 |
-| MMCX | 0 | 1 |
-| PE CLK | 1 | 1 |
-
-### VADJ Power
-
-The EFC Board has configurable Digital IO Voltage Level/PSU called VADJ. You should configure VADJ to 1.8V by fitting W1/W2 jumper accordingly.
-![efc_vadj_settings](../img/efc_vadj_settings.jpg)
-
-
-### Remote AFE Board Connections
-
-The Remote AFE Board is not installed in the crate and should be shipped separately. When you test the EFC Board, please connect the Mini SAS Cables in this orientation.
-![Mini-Sas Connections](../img/shuttler_afe_connections.jpg)
-
-There is no PSU for the Remote AFE Board at this moment. For testing purposes, you should connect the Remote AFE Board to a lab PSU supplying +15V, -15V, and +5V. Please make sure all voltages share a common GND and check the pinouts carefully. Incorrect power connections can damage the Remote AFE Board.                                                  
-
-## Building EFC Board Gateware and Firmware
-
-The EFC Board gateware and firmware are on the [Artiq](https://github.com/m-labs/artiq) repo.
-
-To build the gateware and firmware,
-```
-python -m artiq.gateware.targets.efc --hw-rev [v1.0, v1.1]
-```
-
-## Routing Table Configuration if Shuttler is Connected to Kasli Satellite
-
-When Kasli Satellite is compiled with Shuttler, Shuttler is connected to the Satellite Repeater instance. Therefore, you will need to specify the routing table on the Kasli/Kasli-soc master in order to access the Shuttler hardware. Shuttler locates at DEST 4 connecting to Repeater ID #3. The ID number goes up accordingly if more than one Shuttler is connected.
-
-Here provides an example to configure the routing table.
-You have 1 Kasli Master and 1 Kasli Satellite. Kasli Master (SFP1)(DEST1) port is connected to Kasli Satellite(SFP0)(DEST0). Shuttler is connected to Kasli Satellite with DRTIO over EEM Cable(DEST4).
-
-1. Initialize the Routing Table: ``` artiq_route rt.bin init```
-2. Add the routing table entry for Kasli Master's Peripherals: ```artiq_route rt.bin set 0 0```
-3. Add the routing table entry for Kasli Satellite's Peripherals: ```artiq_route rt.bin set 1 1 0```
-4. Add the routing table entry for Shuttler: ```artiq_route rt.bin set 4 1 4 0```
-5. Flash the routing table on Kasli Master: ```artiq_coremgmt config write -f routing_table rt.bin```
-
-## Flashing
-
-When you are building a crate with shuttler(s), you should erase the flash/sd card config on both the EFC and Kasli/Kasli-soc. Always flash the EFC Board first before flashing the Kasli/Kasli-soc.
-
-If either of the following elements is changed, you will need to **ERASE** the stored calibrated values on both the EFC and Kasli Master, or the communication between the boards cannot be established:
-1. EEM Cable
-2. Clock-Related Cable
-3. EFC Board Gateware
-4. Kasli/Kasli-Soc Master Gateware
-5. EFC Board/Kasli/Kasli-Soc PCB
-
-To erase the flash on the EFC board,
-```
-artiq_flash -t efc erase
-```
-
-To flash the gateware and firmware onto the EFC board,
-```
-artiq_flash --srcbuild -t [efc1v0, efc1v1] -d artiq_efc/shuttler
-```
-
-## Testing
-
-1. Connect the Remote AFE Card to the Shuttler
-2. Power up the Remote AFE Board and the Kasli/Kasli-Soc with the connected Shuttler.
-3. Check all Remote AFE Board Power Indicator LEDs.
-4. Run the `artiq_sinara_test`. 
-
-
-```
-*** Testing LEDs.
-Check for blinking. Press ENTER when done.
-...
-Testing LED: shuttler0_led0
-Testing LED: shuttler0_led1
-
-*** Testing Shuttler.
-Testing:  shuttler0
-Check Remote AFE Board Relay LED Indicators.
-Press Enter to Continue.
-
-Testing Shuttler DAC
-Voltages: 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8
-Press Enter to Continue.
-
-PASSED
-
-...
-```

src/hw/stabilizer.md

@@ -4,83 +4,13 @@
 * [QUARTIQ Manual](https://quartiq.de/stabilizer/)
 * [Firmware](https://github.com/quartiq/stabilizer)
 
-EEM is used for power only, and it can be alternatively powered by 12V barrel jack or PoE.
-
 ## JSON
 
-Not present in the JSON.
+No JSON modifications required.
-
-## Getting the firmware
-
-You can get the firmware from [Hydra](https://nixbld.m-labs.hk/jobset/mcu/mcu-contrib).
-
-* ``stabilizer-dual-iir`` supports Pounder v1.2 - probably you should flash this one,
-* ``stabilizer-dual-iir-pounder_v1_0`` supports Pounder 1.0 and 1.1 (legacy),
-* ``stabilizer-lockin`` is a different application which we do not usually flash.
-
-These all include changes to the mainline code to include Pounder telemetry.
-
-### Building (optional)
-
-Please keep in mind that the firmware from the official Quartiq repository does not include support for Pounder in MQTT, you may need to use a fork for that. But if the stabilizer is without a Pounder, it's also a valid option.
-
-There is no Nix Flake support to make things easier, so you need to set up rust and cargo manually. Start with cloning the stabilizer repository and opening a new shell with dfu-util (for flashing) and rustup (for building).
-
-```
-nix-shell -p dfu-util rustup
-```
-
-Set up the toolchain, this should be done only once:
-
-```
-rustup target add thumbv7em-none-eabihf
-cargo install cargo-binutils
-rustup component add llvm-tools-preview
-rustup update
-rustup default stable
-```
-
-Building:
-
-```
-cargo build --release
-cargo objcopy --release --bin dual-iir -- -O binary dual-iir.bin
-```
-
-## Flashing
-
-Once you have the binary, you can now flash it.
-
-Without firmware on the device or with older firmware (without USB serial console), you need to use the jumper method:
-
-1. Have the Stabilizer disconnected from power.
-2. Use a jumper of some sort to short BOOT pins on the board.
-3. Turn on the power.
-4. You can remove the jumper after few seconds.
-
-With newer firmware with USB serial console:
-
-1. Connect the Stabilizer to power.
-2. Connect USB cable to the Stabilizer.
-3. Connect with a serial console emulator, usually at ``/dev/ttyACM0``.
-4. Input ``platform dfu`` in the console.
-
-And for both:
-
-5. The device is now in DFU mode.
-6. Flash the device with the following command:
-
-```
-dfu-util -a 0 -s 0x08000000:leave -R -D dual-iir.bin
-```
-
-7. Look for "File downloaded successfully".
-
-For normal usage, the stabilizer must be configured with USB console later (try ``help`` command first), to set its IP address and MQTT broker address. However, for general testing (like the one below), you don't need to configure it any further.
 
 ## Testing
 
-1. Ensure that the [firmware](#getting-the-firmware) has been flashed onto the Stabilizer
+1. Ensure that the [firmware](https://github.com/quartiq/stabilizer) has been flashed onto the Stabilizer
 2. Turn on the crate/Stabilizer via EEM cable or power supply
 3. Set up the signal generator for an amplitude of 1V, frequency of 10kHz, and a sine wave
 4. Use the splitter to connect the generator's output to ADC0 and to the oscilloscope (refer to the picture below)

src/hw/thermostat.md

@@ -23,28 +23,6 @@ dfu-util -a 0 -s 0x08000000:leave -D thermostat.bin
 Then check that fans are working properly.
 You may also check fan controls via `fan` commands (see the firmware documentation).
 
-## Test PID
-
-1. For Zotino: connect 10-pins IDC 2.54mm FC cable from internal Thermostat connector to the Zotino TEC
-2. General TEC: connect external connector to the TEC
-3. Connect Ethernet and PSU
-4. Run:
-   ```shell
-   git clone gitea@git.m-labs.hk:esavkin/thermostat.git
-   cd thermostat
-   git checkout zotino-tec
-   nix develop
-   python pytec/tec_qt.py
-   ```
-5. In `Output Config`, set limits: 
-   * `Max Cooling Current` - 400 mA
-   * `Max Heating Current` - 400 mA
-   * `Max Voltage Difference` - 1 V
-6. `PID Config` -> `PID Auto Tune` set desired target temperature, which should be slightly above your room temperature (+10C)
-7. Set `Thermistor Config` -> `B` and other values, according to the datasheet of the TEC module, for example for Zotino `B` is `3455 K`
-8. Run `PID Config` -> `PID Auto Tune` -> `Run` and check graphs that the measured temperature goes to the target temperature, 
-   and eventually stabilizes at +- 0.01 of the target
-
 ## Common problems
 
 ### Thermostat doesn't connect or doesn't enter DFU mode

src/hw/urukul.md

@@ -20,8 +20,7 @@
 
 ## Setup
 
-Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clock source - either Clocker, 
+Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clocker source.
-Kasli or external via SMA.
 
 ### Synchronization
 
@@ -31,22 +30,6 @@ Synchronization requires Kasli and Urukul to be clocked from the same oscillator
 why this feature is disabled by default.
 There is no intrinsic impact on Urukul output phase noise and the synchronization process is quick and reliable when done correctly.
 
-### One-EEM mode
-
-Users may choose to use only one EEM port, if they want more cards to be in their crate. However following features
-will become unavailable:
- * SU-Servo
- * Low-latency RF switch control
- * Synchronization
-
-RF switches are still available but the commands need to go over the SPI bus so it's higher-latency and lower-resolution.
-
-### Urukul 4412
-
-Urukul 4412 has higher frequency resolution (47 bit against 32 at Urukul 4410), however lacks such features:
- * SU-Servo
- * Synchronization
-
 ## Testing
 
 After running `artiq_sinara_test`:
@@ -149,25 +132,4 @@ matches real clocker source.
 ValueError: Urukul AD9910 AUX_DAC mismatch
 ```
 
-Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description.
+Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description.
-
-### Jagged signal with 1GHz external clock on AD9910
-
-By default, on AD9910 external clock signal is divided by 4, while it should be not divided at all with PLL disabled.
-Change the ``clk_div`` parameter to the CPLD in the device_db file:
-
-```python
-device_db["urukulX_cpld"] = {
-    "type": "local",
-    "module": "artiq.coredevice.urukul",
-    "class": "CPLD",
-    "arguments": {
-        "spi_device": "spi_urukul0",
-        "sync_device": None,
-        "io_update_device": "ttl_urukul0_io_update",
-        "refclk": 1000000000.0,
-        "clk_sel": 1,
-        "clk_div" : 1 # <--- add this line
-    }
-}
-```

src/hw/zotino_fastino.md

@@ -20,7 +20,8 @@
 }
 ```
 
-Fastino uses one physical EEM channel, despite having two EEM ports.
+Fastino uses two physical EEM channels, but in the JSON file there should be only one channel specified, 
+and it should be the one connected to Fastino's EEM0.
 
 ## Setup
 
@@ -54,25 +55,4 @@ Press ENTER when done.
 ### High-freq audible noise and output values all near -0.1 on Zotino v1.4.2
 
 This may happen when power-cycle is too short. Power down the crate, wait at least 30 seconds, and power up again.
-[Issue](https://github.com/sinara-hw/Zotino/issues/37).
+[Issue](https://github.com/sinara-hw/Zotino/issues/37).
-
-### Zero/meaningless voltage output on Fastino
-
-Some Fastino may not output any meaningful voltage during testing, usually that means it has no gateware flashed.
-
-Another common symptom of no gateware is that no LEDs are lit up. Whereas if the gateware has been flashed, the PG and FD LEDs will be lit green.
-
-You can flash the gateware with a Kasli/Kasli-SoC, be it in the crate or standalone (no specific gateware needed for Kasli/SoC):
-
-1. Download the latest `fastino.bin` release from [quartiq/fastino](https://github.com/quartiq/fastino/releases).
-2. Run `git clone https://github.com/quartiq/kasli-i2c.git` and place `fastino.bin` in the kasli-i2c directory.
-3. Connect the Fastino's EEM0 to any available Kasli/Kasli-SoC EEM port ([**do not hot-plug**](../build_test_firmware.md#operating-hints-and-warnings)). 
-   You may skip this step if Fastino is connected within a crate.
-4. Power on the standalone Kasli/Kasli-SoC and connect it to the PC via data micro-USB.
-5. Run `nix-shell -p python311Packages.pyftdi`.
-6. Run `cd kasli-i2c; python flash_fastino.py 0 EEM<number> write fastino.bin` where `<number>` is the EEM port number on the Kasli/Kasli-SoC side.
-7. If PG and FD LEDs are lit green, the Fastino is ready.
-
-### Fastino output is 10V
-
-Fastinos by default after power up output 10V on all channels if not driven by the test otherwise. Make sure the EEM ports are specified correctly in the JSON and the EEM cable is connected to EEM0 on the Fastino.

src/sw_sup/artiq_legacy.md

@@ -1,6 +1,4 @@
-# Building legacy firmware
+# Building ARTIQ-6 and earlier
-
-## Building ARTIQ-6 and earlier
 
 Pre-flake ARTIQ (that is 6 and earlier) requires slightly different steps for building.
 
@@ -8,9 +6,9 @@ Pre-flake ARTIQ (that is 6 and earlier) requires slightly different steps for bu
 
 The following steps need to be done only once.
 
-First we will need to specify older nixpkg version - 21.05. Open `~/.nix-channels` with your favorite text editor.
+First we will need to specify older nixpkg version - 21.05. Open ``~/.nix-channels`` with your favorite text editor.
 
-If there are any `nixpkgs` present already, comment them out with `#`.
+If there are any ``nixpkgs`` present already, comment them out with ``#``.
 
 Then add the following line:
 
@@ -20,7 +18,7 @@ https://nixos.org/channels/nixos-21.05 nixpkgs
 
 Save and exit.
 
-Now, we need special `nix-scripts` to configure building environment, and a local copy of the artiq repository, in legacy release.
+Now, we need special ``nix-scripts`` to configure building environment, and a local copy of the artiq repository, in legacy release.
 
 ```shell
 mkdir artiq-legacy
@@ -53,9 +51,7 @@ artiq_flash -V <variant> -d artiq_kasli --srcbuild
 
 There's a slight discrepancy from usual command - ``-V <variant>`` option is not present in ARTIQ-7+, but it is necessary here.
 
-If you want to send the binaries to a customer, there's no need packing up the whole build directory - only `top.bit`, `bootloader.bin`
+If you want to send the binaries to a customer, there's no need packing up the whole build directory - only ``top.bit``, ``bootloader.bin`` and ``runtime.elf/fbi`` or ``satman.elf/fbi`` are necessary. You can use the ``prep_pkg.py`` script from extras to package them up neatly into a zip file for distributions:
-and `runtime.elf/fbi` or `satman.elf/fbi` are necessary. You can use the `prep_pkg.py` script from extras to package 
-them up neatly into a zip file for distributions:
 
 ```shell
 python prep_pkg.py -v <variant> -d artiq_kasli/
@@ -65,40 +61,4 @@ Then the customer can use ``artiq_flash`` easily, after extracting the contents:
 
 ```shell
 artiq_flash -V <variant> -d .
-```
+```
-
-## ARTIQ-7
-
-The process of building firmware for ARTIQ-7 is mostly similar to ARTIQ-8, except there are no named RTIO channels 
-and no remote reboot functionality on Kasli-SoC. DRTIO set ups are also similar to ARTIQ-8. [See reference](../build_test_firmware.md).
-
-### Kasli, Kasli 2.0
-
-```shell
-mkdir <variant>
-cd <variant>/
-nix develop github:m-labs/artiq\?ref=release-7
-# master/standalone only
-artiq_mkfs -s ip 192.168.1.75 kasli.config
-artiq_flash storage -f kasli.config
-artiq_ddb_template -o device_db.py <variant>.json 
-python -m artiq.gateware.targets.kasli_generic <variant>.json 
-artiq_flash --srcbuild -d artiq_kasli/<variant>/
-```
-
-### Kasli-SoC
-
-```shell
-mkdir <variant>
-cd <variant>/
-nix develop git+https://git.m-labs.hk/m-labs/artiq-zynq\?ref=release-7
-artiq_ddb_template -o device_db.py <variant>.json 
-nix build -L --impure --expr 'let fl = builtins.getFlake "git+https://git.m-labs.hk/m-labs/artiq-zynq?ref=release-7"; in (fl.makeArtiqZynqPackage {target="kasli_soc"; variant="[master, standalone, satellite]"; json=<full path to the json description>;}).kasli_soc-[master, standalone, satellite]-sd' 
-# copy `results/boot.bin` to the SD card
-# insert SD card to the Kasli-SoC and boot
-artiq_coremgmt -D 192.168.1.56 config write -s ip 192.168.1.75 # or just place extra/CONFIG.TXT near the boot.bin on SD card
-# update firmware (alternative to copy to SD, if ARTIQ already running)
-artiq_coremgmt config write -f boot result/boot.bin
-# reboot via power supply
-```
-

src/sw_sup/artiq_start.md

@@ -1,38 +0,0 @@
-# Starting with ARTIQ
-
-This page describes how to start with ARTIQ system for novice users.
-
-## Connecting wires
-
-In most cases the system is shipped with power bricks (PSU), DC splitters and SFPs enough to power and control the whole system.
-Connect them in following order:
-1. Insert Ethernet SFP into the SFP0 of the master or standalone Kasli/Kasli-SoC (Carrier)
-2. Connect these SFPs to the router or PC via Ethernet cable (in some cases, optical cable)
-3. Insert optic/direct attach SFPs into the master and satellite Carriers, respective to the numeration, [more info in DRTIO page](drtio.md)
-4. Power on PSU or EEM power module, by inserting C14 cable, attach DC splitters if available
-5. Some cards may have "External power" setting (check the quotation), in this case, insert DC connector into the port
-6. Insert remaining cables into the Carriers (not applicable in case of EEM Power Module).
-
-## Set the network
-
-By default standalone/master Carriers arrive with 192.168.1.75/24 set as their static address. Carrier will try to acquire this address
-from your router, and in case of failure, they will be just unavailable from the network. Check the following articles for troubleshooting network issues:
-* [Networking](networking.md)
-* [Official docs](https://m-labs.hk/artiq/manual/installing.html#setting-up-the-core-device-ip-networking)
-
-## Run first experiment via artiq_run
-
-Before diving in to the repository experiments management and scheduling, it is essential to try run your first experiment
-via most basic way - `artiq_run`. For this you need to enter your ARTIQ environment (console) and run:
-```shell
-artiq_run --device-db path/to/device_db.py path/to/experiment.py
-```
-
-In case your directory contains relevant `device_db` file, you may omit the `--device-db path/to/device_db.py` part.
-To check this, you may run `ls .` and check if it is in the list.
-
-On pre-installed NUCs, the ARTIQ commands are available everywhere, and you just need to run them.
-If you have Nix package manager or NixOS, you will just need to enter the shell with `nix develop github:m-labs/artiq\?ref=release-7`.
-If you have installed ARTIQ with Conda, you will need to activate the environment with `conda activate <name of the environment with ARTIQ>`.
-
-You may check for experiments in the [official docs](https://m-labs.hk/artiq/manual/getting_started_core.html).

src/sw_sup/clocking.md

@@ -1,84 +0,0 @@
-# Clocking
-
-This page describes ways to set up clocking. Official documentation references:
-
-* [Carrier configuration](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device)
-* Devices' [available options](https://m-labs.hk/artiq/manual/core_drivers_reference.html), [Urukul example](https://m-labs.hk/artiq/manual/core_drivers_reference.html#artiq.coredevice.urukul.CPLD)
-
-In general, any RF card and Carriers require some clock source. Most of them have both internal clock signal generator
-and external MMCX and/or SMA connectors to accept the signal. By default the internal clock is used for Carriers,
-and external MMCX is used for RF cards. However, internal clock may be not good enough for the end-user application,
-so the end-user may want to change the clock source at any time.
-
-## Kasli/Kasli-SoC
-
-For setting clocking on the Carriers you will just need to set `rtio_clock` in the core device config. Be aware, that
-setting any external clocking will require appropriate external clock signal to be supplied into `CLK IN` SMA connector
-on the front panel to boot. Therefore, firmware will be halted, the `ERR` LED will be red and **no Ethernet connection
-will be established**. Since the clock signal is distributed by DRTIO, there is generally no need in setting it up on
-satellites.
-
-If you have connection with the Carrier, you can use coremgmt command:
-
-```shell
-artiq_coremgmt config write -s rtio_clock <OPTION>
-```
-
-For available options refer to the official documentation (at the top of the page).
-
-### Setting clocking for Kasli without connection
-
-For RISC-V/legacy Kasli you will just need to connect your PC to the Kasli via _data_ micro-USB cable and run the
-following:
-
-```shell
-# you may also change IP setting here, the default is 192.168.1.75
-artiq_mkfs kasli.config -s ip xx.xx.xx.xx -s rtio_clock <OPTION> 
-# but don't forget to update `core_addr` variable in the device_db.py file if changed
-artiq_flash storage -f kasli.config
-```
-
-Be aware that all other settings will be **erased**, so you may need to restore them in the `artiq_mkfs` command.
-
-### Setting clocking for Kasli-SoC without connection
-
-For this you will need to eject micro-SD card from the Kasli-SoC, either
-by [removing the top panel](../img/rack_urukul_switch_access.jpg) or by gently pulling the Kasli-SoC from the crate,
-possibly with other cards. In any case, be cautious and follow
-the [warnings](../build_test_firmware.md#operating-hints-and-warnings). Once accessed the micro-SD card, simply
-add `rtio_clock=<OPTION>` on a new line to the existing `CONFIG.TXT` file and save it, or if it is absent, just download
-default-ish [CONFIG.TXT](../extra/CONFIG.TXT) to the SD card near (same level) `boot.bin` file.
-
-## RF Devices (Except Clocker)
-
-If you want to set the clock source specifically for RF devices, you will just need to update the JSON file
-and [regenerate device_db.py file](device_db.md).
-
-For example for Urukul, you will just need to check the manual for available variants and apply them in the JSON file,
-so Urukul entry may look like this:
-
-```json
-{
-  "type": "urukul", 
-  "dds": "ad9910", 
-  "ports": [1, 2], 
-  "refclk": 10e6, 
-  "clk_sel": 1
-}
-```
-
-So basically, `clk_sel` and `refclk` fields need to be set:
-
-* `clk_sel` selects the source clock, where 0 - internal 100MHz XO; 1 - front-panel SMA; 2 internal MMCX
-* `refclk` - reference clock frequency in Hz
-
-These settings may need to be checked with official manual and may differ from device to device.
-
-## Clocker card
-
-Main page: [clocker.md](../hw/clocker.md)
-
-Clocker card allows to distribute clock signal up to 1 GHz without additional software setup. Therefore, there is no way
-to set it to generate signal, which would be different from input. The only setup allowed is to set to accept signal
-from `EXT`/`INT` ports, front-panel SMA or card's MMCX ports respectively, by switching the `CLK SEL` switch on the
-card ![](../img/clocker_ref.jpg).

src/sw_sup/device_db.md

@@ -1,21 +0,0 @@
-# device_db.py File
-
-`device_db.py` file contains the database of the devices and their respective interfaces within the firmware/gateware.
-It is generated from JSON description file and tied with the configuration and the gateware.
-
-## Generating the device_db.py File
-
-In some cases you may need to regenerate `device_db.py`, like switching clock source or changing the configuration.
-Also it is must-do in most cases once firmware/gateware is being updated (for example, when you add, move or remove EEM
-cards).
-Luckily, it is fairly easy to do. For standalone systems:
-
-```shell
-artiq_ddb_template -o device_db.py <standalone variant>.json
-```
-
-For DRTIO systems:
-
-```shell
-artiq_ddb_template -o device_db.py -s 1 <satellite1>.json -s 2 <satellite2>.json <...> -s N <satelliteN>.json <master>.json
-```

src/sw_sup/drtio.md

@@ -45,9 +45,3 @@ During the connection, the clock signal is being distributed, effectively making
 * Wrong setups - master to master, standalone to standalone. Messing up with SFP ports generally makes it unusable,
   but the connection should be established in most cases.
 * The fiber adapters are not symmetrical - if one end has 1270/1330 label, another one should be 1330/1270.
-
-
-### Master-satellite interrupted/unstable connection
-
-This often happens due to overheating issues. Check if the Kasli/SoC fans are working properly and
-try installing rack fans to increase the air flow.