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Smal updates 

Signed-off-by: Egor Savkin <es@m-labs.hk>
This commit is contained in:
Egor Savkin 2024-08-08 17:44:41 +08:00
parent a884f3dd7e
commit e5e4de8fd7
1 changed files with 4 additions and 5 deletions
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9
src/build_test_firmware.md
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@ -48,6 +48,7 @@ python -m artiq.gateware.targets.kasli <variant>.json
artiq_flash --srcbuild -d artiq_kasli/<variant>/
artiq_rtiomap dev_map.bin
artiq_coremgmt config write -f device_map dev_map.bin
artiq_coremgmt reboot
```
## Kasli-SoC (zynq)
@ -73,10 +74,9 @@ nix build -L --impure --expr 'let fl = builtins.getFlake "git+https://git.m-labs
# copy `results/boot.bin` to the SD card
# insert SD card to the Kasli-SoC and boot
artiq_coremgmt -D 192.168.1.56 config write -s ip 192.168.1.75 # or just place extra/CONFIG.TXT near the boot.bin on SD card
# update firmware (alternative to copy to SD, if ARTIQ already running)
# update firmware (alternative to copy to SD, if ARTIQ already running and connected)
artiq_coremgmt config write -f boot result/boot.bin
artiq_coremgmt reboot
# reboot via power supply
artiq_rtiomap dev_map.bin
artiq_coremgmt config write -f device_map dev_map.bin
```
@ -98,10 +98,9 @@ you can use this book's pages, or if there is no instruction for testing your ha
## Master-satellite setups
1. Change `base` in JSON to the respective `master` or `satellite`, add `"enable_sata_drtio": true` if needed to the master,
remove `core_addr` in satellites
1. Change `base` in JSON to the respective `master` or `satellite`, remove `core_addr` in satellites
2. Build and flash firmware for each crate with JSONs (see instructions above)
3. Create composed `device_db.py`: e.g. `artiq_ddb_template -o device_db.py -s 1 <satellite1>.json -s 2 <satellite2>.json <master>.json`
3. Create combined `device_db.py`: e.g. `artiq_ddb_template -o device_db.py -s 1 <satellite1>.json -s 2 <satellite2>.json <master>.json`
4. Connect satellite crates to the master respective to their numbers via the fiber (see example picture)
![](img/master_sat_connection.jpg)
5. Ethernet is needed only for master