Add clocker, grabber (draft), almazny, sampler, fastino, master-satellite instructions

Signed-off-by: Egor Savkin <es@m-labs.hk>

README.md

@@ -28,7 +28,9 @@ Tips for adding hardware instructions:
 
 1. Compose a chapter in a new Markdown file in `src/hw`
 2. Add pictures if needed, store them in `src/img`, assure them to be clear, informative and compressed
-   (you can use `convert <INPUT IMAGE> -quality 80% -resize <width>x<height> <OUTPUT IMAGE>` for optimizing)
+   (you can use `convert <INPUT IMAGE> -quality 80% -resize <width>x<height> <OUTPUT IMAGE>` for optimizing JPEG image 
+   or `convert <INPUT IMAGE> -quality 80% -resize <width>x<height> -background white -alpha remove -alpha off <OUTPUT IMAGE>`
+   for images with transparent background)
 3. Add link to the new chapter to the `src/SUMMARY.md`
 4. Do not forget to tell about all hidden/non-obvious obstacles and pitfalls
 5. Add testing steps, even the "obvious" ones

src/SUMMARY.md

@@ -3,9 +3,12 @@
 - [Build and test firmware](./build_test_firmware.md)
 - [Hardware](./hw/hardware.md)
   - [Sinara 4624 AWG Phaser (Upconverter)](./hw/phaser_upconverter.md)
-  - [Sinara 4456 synthesizer Mirny](./hw/mirny.md)
+  - [Sinara 4456 synthesizer Mirny / Sinara 4457 Almazny Mezzanine card](./hw/mirny_almazny.md)
   - [SUServo (Sampler + Urukul)](./hw/suservo.md)
   - [Sinara 2118 BNC-TTL / 2128 SMA-TTL](./hw/bnc_sma_ttl.md)
-  - [Sinara 5432 DAC Zotino](./hw/zotino.md)
+  - [Sinara 5432 DAC Zotino / Sinara 5632 DAC Fastino](./hw/zotino_fastino.md)
   - [Sinara 5518 BNC-IDC / 5528 SMA-IDC adapter](./hw/bnc_sma_idc_adapter.md)
-  - [Sinara 4410/4412 DDS "Urukul" (AD9910/AD9912)](./hw/urukul.md)
+  - [Sinara 4410/4412 DDS Urukul (AD9910/AD9912)](./hw/urukul.md)
+  - [Sinara 5108 Sampler](./hw/sampler.md)
+  - [Sinara 6302 Grabber](./hw/grabber.md)
+  - [Sinara 7210 Clocker](./hw/clocker.md)

src/build_test_firmware.md

@@ -27,4 +27,45 @@ artiq_sinara_tester
 ```
 
 Follow `artiq_sinara_tester` instructions for testing the hardware. For more detailed information, 
-you can use this book's pages, or if there is no instruction for testing your hardware, please add them to this book.
+you can use this book's pages, or if there is no instruction for testing your hardware, please add them to this book.
+
+## Kasli-SoC (zynq)
+
+### Checklist
+
+1. Build firmware (see commands below) for SD card variant
+2. Copy `results/boot.bin` to the SD card
+3. Insert SD card to the Kasli-SoC and boot
+4. Change IP from the default one: `artiq_coremgmt -D 192.168.1.56 config write -s ip 192.168.1.75`
+5. Reboot and check it works on new IP address
+6. Test hardware
+7. Create a flash-drive with `device_db.py` file for customers (FAT32)
+
+### CLI commands
+
+```shell
+mkdir <variant>
+cd <variant>/
+git clone gitea@git.m-labs.hk:M-Labs/artiq-zynq.git
+cd artiq-zynq/
+git checkout origin/release-7
+nix develop
+artiq_ddb_template -o device_db.py <variant>.json 
+nix build -L --impure --expr 'let fl = builtins.getFlake "git+file://<path to artiq_zynq repo>"; in (fl.makeArtiqZynqPackage {target="kasli_soc"; variant="[master, standalone, satellite]"; json=<path to the json description>;}).kasli_soc-[master, standalone, satellite]-sd' 
+# copy `results/boot.bin` to the SD card
+# insert SD card to the Kasli-SoC and boot
+artiq_coremgmt -D 192.168.1.56 config write -s ip 192.168.1.75
+# reboot via power supply
+artiq_sinara_tester
+```
+
+## Master-satellite setups
+
+1. Change `base` in JSON to the respective `master` or `satellite`, add `"enable_sata_drtio": true` if needed to the master,
+   remove `core_addr` in satellites
+2. Build and flash firmware for each crate with JSONs (see instructions above)
+3. Create composed `device_db.py`: `artiq_ddb_template -o device_db.py -s 1 <satellite1>.json -s 2 <satellite2>.json <master>.json`
+4. Connect satellite crates to the master respective to their numbers via the fiber (see example picture)
+   ![](img/master_sat_connection.jpg)
+5. Ethernet is needed only for master
+6. Test hardware as it would be one crate

src/hw/bnc_sma_idc_adapter.md

@@ -3,11 +3,11 @@
 ## JSON
 
 There is no JSON description for this hardware, as it is an adapter,
-connected to the Zotino and not the Kasli. See [Zotino page](./zotino.md).
+connected to the Zotino/Fastino and not the Kasli. See [Zotino/Fastino page](./zotino_fastino.md).
 
 ## Setup
 
-BNC/SMA-IDC adapters should be connected to the Zotino with 26 pin cable only. Be aware of the order of the Zotino's ports - 
+BNC/SMA-IDC adapters should be connected to the Zotino/Fastino with 26 pin cable only. Be aware of the order of the Zotino/Fastino's ports - 
 see numbers of the channels at the board when connecting.
 
 ## Testing
@@ -15,12 +15,12 @@ see numbers of the channels at the board when connecting.
 After running `artiq_sinara_test`:
 
 ```text
-*** Testing Zotino DACs and USER LEDs.
+*** Testing Zotino/Fastino DACs and USER LEDs.
 Voltages:
-zotino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
+zotino0/fastino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
 Press ENTER when done.
 ```
 
-Similar to Zotino, check output voltages on the BNC/SMA connectors with multimeter, alongside on the Zotino itself.
+Similar to Zotino/Fastino, check output voltages on the BNC/SMA connectors with multimeter, alongside on the Zotino/Fastino itself.
 These voltages should be very close to the respective `artiq_sinara_test`'s suggested voltages.
-See [Zotino page](./zotino.md) for details.
+See [Zotino/Fastino page](./zotino_fastino.md) for details.

src/hw/clocker.md

@@ -0,0 +1,52 @@
+# Sinara 7210 Clocker
+
+[Wiki](https://github.com/sinara-hw/Clocker/wiki)
+
+## JSON
+
+Put the `ext_ref_frequency` field into the JSON description if the Clocker is going to use an external frequency:
+
+```json
+{
+  "hw_rev": "<hw rev>",
+  "base": "<base>",
+  ...
+  "ext_ref_frequency": <freq in Hz>,
+  ...
+  "peripherals": [...]
+}
+```
+
+On peripherals you should choose `"clk_sel": 2` on connected devices.
+
+## Setup
+
+For tests, you may need an external RF generator, depending on customer needs.
+Here is example setup for SynthNV RF signal generator:
+
+1. Connect SynthNV to the workstation via USB, and 
+2. Install and run `cutecom`: `nix-shell -p cutecom`
+3. Set settings as on the picture below:
+![](../img/cutecom_settings.png)
+4. Open the device, usually it is `/dev/ttyACM0`
+5. Put `?` into `Input` field and press `Enter` for current settings and help commands
+6. For changing the frequency, enter `f<freq in MHz>`, e.g. `f125.0` for 125 MHz
+7. Set RF power so that clocker would recognize the signal with `a<power>` command, e.g. `a63`
+8. Check for desired amplitude and frequency at the `RFOut` (see picture below for reference) pin via oscilloscope
+![](../img/synthnv_pins.jpg)
+9. If everything is ok, connect `RFOut` to the `CLK IN` on the Clocker (see instructions below for details)
+
+### Setup the Clocker
+
+1. Connect MMCx cables according to the customer needs and boards specifications (see image below for reference)
+2. Connect the Clocker to the Kasli via 30-pin ports
+   ![](../img/clocker_ref.jpg)
+3. Connect the Clocker's SMA output to the Kasli's `CLK`/`CLK IN` SMA pin
+4. After assembling the crates and flashing the firmware, start Kasli and write config as follows:
+   `artiq_coremgmt config write -s rtio_clock ext0_bypass`. Please refer to the [official manual](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device)
+   for the details and available options
+5. Reboot either via `artiq_coremgmt reboot` or via power supply if the board's firmware doesn't have such command
+
+## Testing
+
+Run `artiq_sinara_test` and check that it doesn't fail on the connected devices.

src/hw/grabber.md

@@ -0,0 +1,20 @@
+# Sinara 6302 Grabber
+
+## JSON
+
+```json
+{
+  "type": "grabber",
+  "ports": [<port num>, <optional port num>, <optional port num>]
+}
+```
+
+## Testing
+
+```text
+*** Testing Grabber Frame Grabbers.
+Activate the camera's frame grabber output, type 'g', press ENTER, and trigger the camera.
+Just press ENTER to skip the test.
+```
+
+**TODO**

src/hw/mirny.md

@@ -1,44 +0,0 @@
-# Sinara 4456 synthesizer Mirny
-
-[Wiki](https://github.com/sinara-hw/mirny/wiki)
-
-## JSON
-
-```json
-{
-  "type": "mirny",
-  "ports": [<port num>]
-}
-```
-
-## Testing
-
-```text
-*** Testing Mirny PLLs.
-Initializing CPLDs...
-mirny0_cpld...
-...done
-All mirny channels active.
-Frequencies:
-mirny0_ch0	1000MHz
-mirny0_ch0 info: {'f_outA': 1000000000.0, 'f_outB': 8000000000, 'output_divider': 4, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch1	1100MHz
-mirny0_ch1 info: {'f_outA': 1100000000.0, 'f_outB': 8800000000, 'output_divider': 4, 'f_vco': 4400000000, 'pll_n': 44, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch2	1200MHz
-mirny0_ch2 info: {'f_outA': 1200000000.0, 'f_outB': 9600000000, 'output_divider': 4, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch3	1300MHz
-mirny0_ch3 info: {'f_outA': 1300000000.0, 'f_outB': 10400000000, 'output_divider': 4, 'f_vco': 5200000000, 'pll_n': 52, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-```
-
-After running `artiq_sinara_test`:
-
-1. Install gqrx `nix-shell -p gqrx`
-2. Connect bladeRF via USB cable only
-3. Run gqrx and choose `BladeRF #<number>...`
-4. Default settings
-5. When gqrx loaded, start DSP processing with frequency at mirnyN_chM freq
-6. Connect the probe through attenuator to the Mirny's port
-7. You should see significant signal emission on choosen freq compared to nearby freqs (see image below)
-8. Repeat 5-7 for every channel
-
-![](../img/mirny_gqrx.png)

src/hw/mirny_almazny.md

@@ -0,0 +1,98 @@
+# Sinara 4456 synthesizer Mirny / Sinara 4457 Almazny Mezzanine card
+
+[Wiki Mirny](https://github.com/sinara-hw/mirny/wiki)
+[Wiki Almazny](https://github.com/sinara-hw/Almazny/wiki)
+
+## JSON
+
+```json
+{
+  "type": "mirny",
+  "almazny": true, // for mirny with almazny only 
+  "ports": [<port num>]
+}
+```
+
+## Testing
+
+### Without Almazny
+
+```text
+*** Testing Mirny PLLs.
+Initializing CPLDs...
+mirny0_cpld...
+...done
+All mirny channels active.
+Frequencies:
+mirny0_ch0	1000MHz
+mirny0_ch0 info: {'f_outA': 1000000000.0, 'f_outB': 8000000000, 'output_divider': 4, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny0_ch1	1100MHz
+mirny0_ch1 info: {'f_outA': 1100000000.0, 'f_outB': 8800000000, 'output_divider': 4, 'f_vco': 4400000000, 'pll_n': 44, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny0_ch2	1200MHz
+mirny0_ch2 info: {'f_outA': 1200000000.0, 'f_outB': 9600000000, 'output_divider': 4, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny0_ch3	1300MHz
+mirny0_ch3 info: {'f_outA': 1300000000.0, 'f_outB': 10400000000, 'output_divider': 4, 'f_vco': 5200000000, 'pll_n': 52, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+```
+
+After running `artiq_sinara_test`:
+
+1. Install gqrx `nix-shell -p gqrx`
+2. Connect bladeRF via USB cable only
+3. Run gqrx and choose `BladeRF #<number>...`
+4. Default settings
+5. When gqrx loaded, start DSP processing with frequency at mirnyN_chM freq
+6. Connect the probe through attenuator to the Mirny's port
+7. You should see significant signal emission on choosen freq compared to nearby freqs (see image below)
+8. Repeat 5-7 for every channel
+
+![](../img/mirny_gqrx.png)
+
+### With Almazny
+
+At first, `artiq_sinara_test` will prompt you for testing Mirnies as the would be without Almazny.
+After that, it will prompt you with testing the Almazny:
+
+```text
+*** Testing Almaznys.
+mirny1_almazny...
+Initializing Mirny CPLDs...
+mirny0_cpld...
+mirny1_cpld...
+...done
+Testing attenuators. Frequencies:
+mirny0_ch0	4000MHz
+mirny0_ch0 info: {'f_outA': 2000000000.0, 'f_outB': 8000000000, 'output_divider': 2, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny0_ch1	4100MHz
+mirny0_ch1 info: {'f_outA': 2050000000.0, 'f_outB': 8200000000, 'output_divider': 2, 'f_vco': 4100000000, 'pll_n': 41, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny0_ch2	4200MHz
+mirny0_ch2 info: {'f_outA': 2100000000.0, 'f_outB': 8400000000, 'output_divider': 2, 'f_vco': 4200000000, 'pll_n': 42, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny0_ch3	4300MHz
+mirny0_ch3 info: {'f_outA': 2150000000.0, 'f_outB': 8600000000, 'output_divider': 2, 'f_vco': 4300000000, 'pll_n': 43, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny1_ch0	4500MHz
+mirny1_ch0 info: {'f_outA': 2250000000.0, 'f_outB': 9000000000, 'output_divider': 2, 'f_vco': 4500000000, 'pll_n': 45, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny1_ch1	4600MHz
+mirny1_ch1 info: {'f_outA': 2300000000.0, 'f_outB': 9200000000, 'output_divider': 2, 'f_vco': 4600000000, 'pll_n': 46, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny1_ch2	4700MHz
+mirny1_ch2 info: {'f_outA': 2350000000.0, 'f_outB': 9400000000, 'output_divider': 2, 'f_vco': 4700000000, 'pll_n': 47, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+mirny1_ch3	4800MHz
+mirny1_ch3 info: {'f_outA': 2400000000.0, 'f_outB': 9600000000, 'output_divider': 2, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
+RF ON, all attenuators ON. Press ENTER when done.
+
+RF ON, half power attenuators ON. Press ENTER when done.
+
+RF ON, all attenuators OFF. Press ENTER when done.
+
+SR outputs are OFF. Press ENTER when done.
+
+RF ON, all attenuators are ON. Press ENTER when done.
+
+RF OFF. Press ENTER when done.
+```
+
+Similar to _Without Almazny_, check mirnies' channels emissions on defined frequencies.
+You should also see differences in various modes, but that may require disabling the gain.
+
+
+### Tips
+
+Mirnies often fail `ValueError: MUXOUT not high`, in that case restart the tests or reboot the board(s).

src/hw/sampler.md

@@ -0,0 +1,35 @@
+# Sinara 5108 Sampler
+
+## JSON
+
+```json
+{
+  "type": "sampler",
+  "ports": [<port num>, <port num>],
+  "hw_rev": "<hw rev>" // optional
+}
+```
+
+## Testing
+
+After running `artiq_sinara_test`:
+
+```text
+*** Testing Sampler ADCs.
+Testing:  samplerX
+Apply 1.5V to channel 0. Press ENTER when done.
+
+PASSED
+Apply 1.5V to channel 1. Press ENTER when done.
+
+...
+
+PASSED
+Apply 1.5V to channel 7. Press ENTER when done.
+
+PASSED
+```
+
+1. Apply 1.5V (connect the AA-battery) to the `samplerX`'s requested channel
+2. Press `Enter`, the `artiq_sinara_test` should output `PASSED`
+3. Repeat steps 1-2 for every available channel.

src/hw/suservo.md

@@ -6,8 +6,8 @@
 {
   "type": "suservo",
   "sampler_ports": [<port num>, <port num>],
-  "urukulN_ports": [<port num>, <port num>],
+  "urukul0_ports": [<port num>, <port num>],
-  "urukulM_ports": [<port num>, <port num>], // optional
+  "urukul1_ports": [<port num>, <port num>], // optional
   "clk_sel": 2
 }
 ```

src/hw/urukul.md

@@ -1,4 +1,4 @@
-# Sinara 4410/4412 DDS "Urukul" (AD9910/AD9912)
+# Sinara 4410/4412 DDS Urukul (AD9910/AD9912)
 
 * [Datasheet](https://m-labs.hk/docs/sinara-datasheets/4410-4412.pdf)
 * [Wiki](https://github.com/sinara-hw/Urukul/wiki)

src/hw/zotino.md

@@ -1,29 +0,0 @@
-# Sinara 5432 DAC Zotino
-
-* [Datasheet](https://m-labs.hk/docs/sinara-datasheets/5432.pdf)
-* [Wiki](https://github.com/sinara-hw/Zotino/wiki)
-
-## JSON
-
-```json
-{
-  "type": "zotino",
-  "ports": [<port num>]
-}
-```
-
-## Testing
-
-After running `artiq_sinara_test`:
-
-```text
-*** Testing Zotino DACs and USER LEDs.
-Voltages:
-zotino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
-Press ENTER when done.
-```
-
-1. Touch with multimeter/DC voltmeter each pair of pins from bottom to top (left pins are ground)
-2. Check that respective pins have voltages as described by `artiq_sinara_test`
-3. If there are [BNC/SMA-IDC adapters](./bnc_sma_idc_adapter.md), also check their voltages - they should be the same
-4. Check LEDs are on

src/hw/zotino_fastino.md

@@ -0,0 +1,47 @@
+# Sinara 5432 DAC Zotino / Sinara 5632 DAC Fastino
+
+* [Datasheet Zotino](https://m-labs.hk/docs/sinara-datasheets/5432.pdf)
+* [Wiki Zotino](https://github.com/sinara-hw/Zotino/wiki)
+* [Wiki Fastino](https://github.com/sinara-hw/Fastino/wiki)
+
+## JSON
+
+```json
+{
+  "type": "zotino",
+  "ports": [<port num>]
+}
+```
+```json
+{
+  "type": "fastino",
+  "hw_rev": "v1.2", // optional
+  "ports": [<port num>]
+}
+```
+
+## Setup
+
+Connect the BNC/SMA-IDC adapters to the Zotino/Fastino with 26-pin cable if needed by customer. Be aware of the ports order - 
+see reference numbers on the board.
+
+## Testing
+
+After running `artiq_sinara_test`:
+
+```text
+*** Testing Zotino DACs and USER LEDs.
+Voltages:
+zotino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
+Press ENTER when done.
+
+*** Testing Fastino DACs and USER LEDs.
+Voltages:
+fastino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7 0.8 -0.8 0.9 -0.9 1.0 -1.0 1.1 -1.1 1.2 -1.2 1.3 -1.3 1.4 -1.4 1.5 -1.5 1.6 -1.6
+Press ENTER when done.
+```
+
+1. Touch with multimeter/DC voltmeter each pair of pins from bottom to top (left pins are ground)
+2. Check that respective pins have voltages as described by `artiq_sinara_test`
+3. If there are [BNC/SMA-IDC adapters](./bnc_sma_idc_adapter.md), also check their voltages - they should be the same
+4. Check LEDs are on