From 7cb7061c5f43f035b171313ad4e3ff9e56f5e146 Mon Sep 17 00:00:00 2001 From: Egor Savkin Date: Wed, 14 Aug 2024 10:37:10 +0800 Subject: [PATCH] Update links Signed-off-by: Egor Savkin --- src/hw/clocker.md | 2 +- src/sw_sup/artiq_start.md | 4 ++-- src/sw_sup/clocking.md | 2 +- src/sw_sup/flashing_firmware.md | 2 +- src/sw_sup/moninj.md | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/hw/clocker.md b/src/hw/clocker.md index 89993e9..57a58d0 100644 --- a/src/hw/clocker.md +++ b/src/hw/clocker.md @@ -36,7 +36,7 @@ Here is example setup for SynthNV RF signal generator: ![](../img/clocker_ref.jpg) 4. Connect the Clocker's SMA output to the Kasli's `CLK`/`CLK IN` SMA pin 5. After assembling the crates and flashing the firmware, start Kasli and set config if needed: - `artiq_coremgmt config write -s rtio_clock ext0_bypass`. Please refer to the [official manual](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device) + `artiq_coremgmt config write -s rtio_clock ext0_bypass`. Please refer to the [official manual](https://m-labs.hk/artiq/manual/core_device.html#clocking) for the details and available options. In most cases you may skip this step. 6. Reboot either via `artiq_coremgmt reboot` or via power supply if the board's firmware doesn't have such command diff --git a/src/sw_sup/artiq_start.md b/src/sw_sup/artiq_start.md index 60e26d4..8cad18f 100644 --- a/src/sw_sup/artiq_start.md +++ b/src/sw_sup/artiq_start.md @@ -18,7 +18,7 @@ Connect them in following order: By default standalone/master Carriers arrive with 192.168.1.75/24 set as their static address. Carrier will try to acquire this address from your router, and in case of failure, they will be just unavailable from the network. Check the following articles for troubleshooting network issues: * [Networking](networking.md) -* [Official docs](https://m-labs.hk/artiq/manual/installing.html#setting-up-the-core-device-ip-networking) +* [Official docs](https://m-labs.hk/artiq/manual/configuring.html) ## Run first experiment via artiq_run @@ -32,7 +32,7 @@ In case your directory contains relevant `device_db` file, you may omit the `--d To check this, you may run `ls .` and check if it is in the list. On pre-installed NUCs, the ARTIQ commands are available everywhere, and you just need to run them. -If you have Nix package manager or NixOS, you will just need to enter the shell with `nix develop github:m-labs/artiq\?ref=release-7`. +If you have Nix package manager or NixOS, you will just need to enter the shell with `nix develop github:m-labs/artiq\?ref=release-8`. If you have installed ARTIQ with Conda, you will need to activate the environment with `conda activate `. You may check for experiments in the [official docs](https://m-labs.hk/artiq/manual/getting_started_core.html). \ No newline at end of file diff --git a/src/sw_sup/clocking.md b/src/sw_sup/clocking.md index 0b55cfd..5100cec 100644 --- a/src/sw_sup/clocking.md +++ b/src/sw_sup/clocking.md @@ -2,7 +2,7 @@ This page describes ways to set up clocking. Official documentation references: -* [Carrier configuration](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device) +* [Carrier configuration](https://m-labs.hk/artiq/manual/core_device.html#clocking) * Devices' [available options](https://m-labs.hk/artiq/manual/core_drivers_reference.html), [Urukul example](https://m-labs.hk/artiq/manual/core_drivers_reference.html#artiq.coredevice.urukul.CPLD) In general, any RF card and Carriers require some clock source. Most of them have both internal clock signal generator diff --git a/src/sw_sup/flashing_firmware.md b/src/sw_sup/flashing_firmware.md index 0dbf013..bdca734 100644 --- a/src/sw_sup/flashing_firmware.md +++ b/src/sw_sup/flashing_firmware.md @@ -6,7 +6,7 @@ Here are some extra steps needed for flashing the firmware. ### Windows -From the [official manual](https://m-labs.hk/artiq/manual/installing.html#configuring-openocd): +From the [official manual](https://m-labs.hk/artiq/manual/flashing.html#installing-and-configuring-openocd): On Windows, a third-party tool, Zadig, is necessary. Use it as follows: 1. Make sure the FPGA board’s JTAG USB port is connected to your computer. diff --git a/src/sw_sup/moninj.md b/src/sw_sup/moninj.md index c1bfe90..982c687 100644 --- a/src/sw_sup/moninj.md +++ b/src/sw_sup/moninj.md @@ -3,7 +3,7 @@ The official documentation lacks the description of MONitor/INJector, but it is a common mistake when running the ARTIQ-7. Basically it is a service that consists of two parts - one runs on the host PC, another on the Kasli. It allows to watch and control the state of the devices, so you can see it on the dashboard. -That's why the dashboard may emit errors about not working moninj. To fix this, you just need [to run it with Kasli's IP](https://m-labs.hk/artiq/manual/utilities.html#moninj-proxy): +That's why the dashboard may emit errors about not working moninj. To fix this, you just need [to run it with Kasli's IP](https://m-labs.hk/artiq/manual/utilities.html#module-artiq.frontend.aqctl_moninj_proxy): ```shell aqctl_moninj_proxy CORE_ADDRESS