Add assembly instructions for Shuttler

src/hw/shuttler.md

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+# Sinara 5716 DAC Shuttler
+The Sinara 5716 DAC Shuttler consists of the [Shuttler](https://github.com/sinara-hw/Shuttler), [Remote AFE-Board](https://github.com/sinara-hw/Shuttler), and [EEM FMC Carrier](https://github.com/sinara-hw/EEM_FMC_Carrier) (EFC) Board. The EFC Board has an FPGA on board that requires special attention when flashing.
+
+## JSON
+
+```json
+{
+    "type": "shuttler",
+    "ports": [<port num>]
+}
+```
+
+## Hardware Configurations and Connections
+### EEM Cable Connection 
+Only the EEM0 port on the EFC board is used. The EEM Cable will provide power. You can ignore the barrel jack at the back of the board.
+
+### CLK Input
+The EFC requires a common clock source with the Kasli/Kasli-Soc Master.
+
+For the EFC Board v1.0, please refer to this [issue](https://github.com/sinara-hw/EEM_FMC_Carrier/issues/44).
+
+For the EFC Board v1.1 (or later), there is a DIP switch to select the clock source.
+![issue](../img/efc_clk_sel.png).
+
+| Clock Source | CLK_SEL0 | CLK_SEL1 |
+|---|---|---|
+| Front Panel SMA | 0 | 0 |
+| Internal Oscillator(default) | 1 | 0 |
+| MMCX | 0 | 1 |
+| PE CLK | 1 | 1 |
+
+### VADJ Power
+You should fit the W1 with a jumper to set VADJ to 1.8V.
+
+### Remote AFE Board Connections
+The Remote AFE Board is not installed in the crate and should be shipped separately. When you test the EFC, please connect the **Impedance Matched Pair** of Mini SAS Cables in this orientation.
+![Mini-Sas Connections](../img/shuttler_afe_connections.jpg)
+
+There is no PSU for the Remote AFE Board at this moment. For testing purposes, you should connect the Remote AFE Board to a lab PSU supplying +15V, -15V, and +5V. Please ensure all voltages share a common GND and check the pinout carefully. Incorrect power connections can damage the AFE Board.                                                  
+
+## Building
+The EFC Board gateware and firmware are on the Artiq repo.
+
+To build the gateware and firmware,
+```
+python -m artiq.gateware.targets.efc
+```
+
+## Flashing
+The EFC and Kasli/Kasli-Soc Master will calibrate each other's IO signal delay at the first startup and then store the calibrated value in the flash memory.
+
+When a crate is built, you should erase the flash on both the EFC and Kasli/Kasli-Soc. Flash the EFC Board first before flashing the Kasli/Kasli-Soc.
+
+If either of these elements is changed, you will need to **ERASE** the stored calibrated values on both the EFC and Kasli/Kasli-Soc Master, or the communication between the boards cannot be established:
+1. EEM Cable
+2. Clock-Related Cable
+3. EFC Board Gateware
+4. Kasli/Kasli-Soc Master Gateware
+5. EFC Board/Kasli/Kasli-Soc Master replacement
+
+To erase the flash on the EFC board,
+```
+artiq_flash -t efc erase
+```
+
+To flash the gateware and firmware onto the EFC board,
+```
+artiq_flash --srcbuild -t efc -d artiq_efc/shuttler
+```
+
+## Testing
+1. Power up both boards. 
+2. After calibration is completed, power cycle the boards.
+3. Run the test
+
+`artiq_sinara_test` is not developed yet. Please run Shuttler's core device example code on the Artiq repo for a basic test and look at the waveform output at OUT0 and OUT1 on the D-Sub connector.