diff --git a/README.md b/README.md
index f6a1ea6..51fc21a 100644
--- a/README.md
+++ b/README.md
@@ -21,7 +21,7 @@ The output files will be in `book` directory.
### Alternative way
-Since the docs builder depends only on mdBook, you may get it from anywhere you like - `nix-shell -p mdbook`,
+Since the docs builder depends only on mdBook, you may get it from anywhere you like - `nix-shell -p mdbook`,
`snap install mdbook`, `cargo install mdbook` or any other from your OS.
After that you will be able to do:
@@ -40,7 +40,7 @@ Tips for adding hardware instructions:
1. Compose a chapter in a new Markdown file in `src/hw`
2. Add pictures if needed, store them in `src/img`, assure them to be clear, informative and compressed
- (you can use `convert x ` for optimizing JPEG image
+ (you can use `convert x ` for optimizing JPEG image
or `convert x -background white -alpha remove -alpha off `
for images with transparent background)
3. Add link to the new chapter to the `src/SUMMARY.md`
@@ -51,3 +51,10 @@ Tips for adding hardware instructions:
7. Add JSON sample if needed
8. Add hardware setup (e.g. pins, switches) steps if needed
9. View changed and added pages with `mdbook build` (see building instructions above)
+10. Check your contributions with linter:
+
+ ```shell
+ nix-shell -p nodejs
+ npm install
+ npx markdownlint-cli2 "src/**/*.md" --fix
+ ```
diff --git a/package-lock.json b/package-lock.json
new file mode 100644
index 0000000..cf6366e
--- /dev/null
+++ b/package-lock.json
@@ -0,0 +1,460 @@
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+ },
+ "funding": {
+ "url": "https://github.com/sponsors/sindresorhus"
+ }
+ }
+ }
+}
diff --git a/package.json b/package.json
new file mode 100644
index 0000000..5c312f2
--- /dev/null
+++ b/package.json
@@ -0,0 +1,13 @@
+{
+ "devDependencies": {
+ "markdownlint-cli2": "^0.14.0"
+ },
+ "markdownlint-cli2": {
+ "config": {
+ "line_length": {
+ "line_length": 120,
+ "code_blocks": false
+ }
+ }
+ }
+}
diff --git a/src/SUMMARY.md b/src/SUMMARY.md
index 77b41b8..652da33 100644
--- a/src/SUMMARY.md
+++ b/src/SUMMARY.md
@@ -32,4 +32,4 @@
- [device_db.py](sw_sup/device_db.md)
- [Setup your PC for building ARTIQ firmware](sw_sup/setup_build_pc.md)
- [AFWS client](sw_sup/afws_client.md)
- - [Integration with PyCharm](sw_sup/pycharm.md)
\ No newline at end of file
+ - [Integration with PyCharm](sw_sup/pycharm.md)
diff --git a/src/build_test_firmware.md b/src/build_test_firmware.md
index a237d78..8a02a14 100644
--- a/src/build_test_firmware.md
+++ b/src/build_test_firmware.md
@@ -5,10 +5,11 @@
* 😡 **Always** use grounding strap during dis/assembly or other cards' physical operation
* 😡 **Always** power off devices before un/plugging
* 🧐 If needed to power-cycle the crate, wait at least 30 seconds before turning them on
-* 🙅 Avoid the boards touching conductive materials - wires, metals. Use at
+* 🙅 Avoid the boards touching conductive materials - wires, metals. Use at
least plastic ESD bags if you need the cards to be put at the desk or any other surface.
* 💁 Be gentle to the EEM ports and any other connectors. Support them when plugging, hold when unplugging
-* 🙆 If you need to take the cards out, take them out one-by-one from the end, unplug EEM and cables if you feel high tension
+* 🙆 If you need to take the cards out, take them out one-by-one from the end, unplug EEM and cables
+ if you feel high tension
* 🙆 Use dedicated power supplies for each crate, preferably given or equivalent to given by us
* 🙅 Avoid unnecessary inserts and pullouts, especially of MMCX cables
@@ -22,19 +23,20 @@ Failure to comply with this voids the warranty.
* ⚠️ Remove any cables from front panels
* ⚠️ Remove SFP adapters and insert caps/stubs
* 💁 Also advised to put caps on SMA connectors
-* ✅ Wrap each crate in the bubble wrap individually until you don't feel the edges of the crate (usually 10 layers of standard buble wrap)
+* ✅ Wrap each crate in the bubble wrap individually until you don't feel the edges of the crate
+ (usually 10 layers of standard buble wrap)
* 🈁 Fill in the space around the crate in the box with foamy stuff
## Kasli standalone
-### Checklist
+### Checklist for Kasli
1. Build firmware (see commands below)
2. Flash firmware and settings
3. Test hardware with the PSU, which is going to be shipped
4. Create a flash-drive with `device_db.py` file for customers (FAT32)
-### CLI commands - build and flash
+### CLI commands - build and flash for Kasli
```shell
mkdir
@@ -53,7 +55,7 @@ artiq_coremgmt reboot
## Kasli-SoC (zynq)
-### Checklist
+### Checklist for Kasli-SoC
1. Build firmware (see commands below) for SD card variant
2. Copy `results/boot.bin` to the SD card
@@ -63,7 +65,7 @@ artiq_coremgmt reboot
6. Test hardware with the PSU, which is going to be shipped
7. Create a flash-drive with `device_db.py` file for customers (FAT32)
-### CLI commands - build and flash
+### CLI commands - build and flash for Kasli-SoC
```shell
mkdir
@@ -83,25 +85,27 @@ artiq_coremgmt config write -f device_map dev_map.bin
## Testing (common)
-```
+```shell
artiq_sinara_tester
```
-Follow `artiq_sinara_tester` instructions for testing the hardware. For more detailed information,
+Follow `artiq_sinara_tester` instructions for testing the hardware. For more detailed information,
you can use this book's pages, or if there is no instruction for testing your hardware, please add them to this book.
### Known issues
-* ~~[artiq-zynq#197](https://git.m-labs.hk/M-Labs/artiq-zynq/issues/197) - some cards (Sampler, Mirny, Zotino and others)
- do not work properly with some EEM ports. You might need to connect the card to the other ports until it gets working.~~
+* ~~[artiq-zynq#197](https://git.m-labs.hk/M-Labs/artiq-zynq/issues/197) - some cards
+ (Sampler, Mirny, Zotino and others) do not work properly with some EEM ports.
+ You might need to connect the card to the other ports until it gets working.~~
resolved (hopefully)
## Master-satellite setups
1. Change `base` in JSON to the respective `master` or `satellite`, remove `core_addr` in satellites
2. Build and flash firmware for each crate with JSONs (see instructions above)
-3. Create combined `device_db.py`: e.g. `artiq_ddb_template -o device_db.py -s 1 .json -s 2 .json .json`
+3. Create combined `device_db.py`:
+ e.g. `artiq_ddb_template -o device_db.py -s 1 .json -s 2 .json .json`
4. Connect satellite crates to the master respective to their numbers via the fiber (see example picture)
- 
+ 
5. Ethernet is needed only for master
6. Test hardware as it would be one crate
diff --git a/src/hw/bnc_sma_idc_adapter.md b/src/hw/bnc_sma_idc_adapter.md
index 4218973..209f542 100644
--- a/src/hw/bnc_sma_idc_adapter.md
+++ b/src/hw/bnc_sma_idc_adapter.md
@@ -7,8 +7,8 @@ connected to the Zotino/Fastino and not the Kasli. See [Zotino/Fastino page](./z
## Setup
-BNC/SMA-IDC adapters should be connected to the Zotino/Fastino with 26 pin cable only. Be aware of the order of the Zotino/Fastino's ports -
-see numbers of the channels at the board when connecting.
+BNC/SMA-IDC adapters should be connected to the Zotino/Fastino with 26 pin cable only. Be aware of the order of
+the Zotino/Fastino's ports - see numbers of the channels at the board when connecting.
## Testing
@@ -21,6 +21,6 @@ zotino0/fastino0 0.1 -0.1 0.2 -0.2 0.3 -0.3 0.4 -0.4 0.5 -0.5 0.6 -0.6 0.7 -0.7
Press ENTER when done.
```
-Similar to Zotino/Fastino, check output voltages on the BNC/SMA connectors with multimeter, alongside on the Zotino/Fastino itself.
-These voltages should be very close to the respective `artiq_sinara_test`'s suggested voltages.
-See [Zotino/Fastino page](./zotino_fastino.md) for details.
\ No newline at end of file
+Similar to Zotino/Fastino, check output voltages on the BNC/SMA connectors with multimeter, alongside on
+the Zotino/Fastino itself. These voltages should be very close to the respective `artiq_sinara_test`'s
+suggested voltages. See [Zotino/Fastino page](./zotino_fastino.md) for details.
diff --git a/src/hw/bnc_sma_ttl.md b/src/hw/bnc_sma_ttl.md
index 7751155..0400fb3 100644
--- a/src/hw/bnc_sma_ttl.md
+++ b/src/hw/bnc_sma_ttl.md
@@ -23,7 +23,7 @@
Switch the direction switches (shown on the picture below) according to customer requests.
Remember, that you can only switch directions in groups of four.
-
+
## Test
@@ -53,6 +53,7 @@ Connect ttl4 to ttl0. Press ENTER when done.
```
1. Mount a wire with respective connector to the chosen TTL output (any should work, choose most convenient one)
-2. Connect the end of the wire to the TTL input requested by the `artiq_sinara_test` (you may use fast connector for SMA)
+2. Connect the end of the wire to the TTL input requested by the `artiq_sinara_test`
+ (you may use fast connector for SMA)
3. Press ENTER and check that `artiq_sinara_test` prints `PASSED`
4. Repeat 2-3 for every connector
diff --git a/src/hw/booster.md b/src/hw/booster.md
index a599b5a..28e7322 100644
--- a/src/hw/booster.md
+++ b/src/hw/booster.md
@@ -11,6 +11,7 @@
#### Easier way
Download and unpack the [booster firmware](../extra/booster/booster0.5.0.tar.xz), and then:
+
```shell
nix-shell -p dfu-util
dfu-util -a 0 -s 0x08000000:leave --download booster0.5.0.bin
@@ -57,15 +58,18 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
1. `nix-shell -p cutecom mosquitto appimage-run`
2. Create mosquitto config `mosquitto.conf` with your bound address:
- ```
+
+ ```text
bind_address 192.168.1.123
allow_anonymous true
```
+
3. `mosquitto -c mosquitto.conf -d`
4. Run `cutecom`
5. Connect to the Booster via `/dev/ttyACMX` port, baud 9600, switch from LF to CR on newer version
6. Send `help` command to check if it works
7. Enter commands (change details if necessary):
+
```shell
write broker-address 192.168.1.123
# only if you need static IP address
@@ -75,13 +79,16 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
# apply changes and wait until it fully rebooted
reset
```
+
Newer version:
+
```shell
write broker "192.168.1.123"
write ip "192.168.1.75"
# apply changes and wait until it fully rebooted
reset
```
+
8. Check the Booster connects to your broker.
9. Download AppImage from [MQTT Explorer](https://mqtt-explorer.com/)
10. Run it with `appimage-run /path/to/MQTT-Explorer-XXX.AppImage`
@@ -92,20 +99,26 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
1. Assemble Kasli with one Urukul, build and flash firmware for it with [booster.json](../extra/booster/booster.json)
2. Run [dds_for_booster.py](../extra/booster/dds_for_booster.py) experiment once
-3. Attach parallel 50 Ohm load to the oscilloscope, as shown on the picture: ,
+3. Attach parallel 50 Ohm load to the oscilloscope, as shown on the picture:
+ ,
4. Configure oscilloscope for 1M Ohm impedance
5. Attach attenuator to the Urukul's RF2
6. `cd py/`
7. You may also need to download or install python's `gmqtt` and `miniconf`:
+
```shell
python -m venv env
source env/bin/activate.fish
pip install git+https://github.com/quartiq/miniconf.git@84cc9046bf504cc2d0d33b84d2f3133f2faf2248#subdirectory=py/miniconf-mqtt
```
-8. Enable channels: `python -m booster --broker 192.168.1.123 --prefix dt/sinara/booster/xx-xx-xx-xx-xx-xx --channel N tune=0.1`
-9. Using [booster_template](../extra/booster/booster_template.ods) fill in `y0`, `y1`, `m`, `c`, values using instructions below
+
+8. Enable channels:
+ `python -m booster --broker 192.168.1.123 --prefix dt/sinara/booster/xx-xx-xx-xx-xx-xx --channel N tune=0.1`
+9. Using [booster_template](../extra/booster/booster_template.ods) fill in `y0`, `y1`, `m`, `c`,
+ values using instructions below
10. Update settings with the adjusted values
-11. Save settings with `python -m booster --broker 192.168.1.123 --prefix dt/sinara/booster/xx-xx-xx-xx-xx-xx --channel N save`
+11. Save settings with
+ `python -m booster --broker 192.168.1.123 --prefix dt/sinara/booster/xx-xx-xx-xx-xx-xx --channel N save`
12. Reboot and check settings are applied
### Input power
@@ -121,7 +134,6 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
_Note: default setting and Urukul's measured values are usually the same across channels, so you can
extrapolate them for all channels._
-
### Output and reflected power
1. Connect Urukul's output (see booster template for exact ports) to the Booster's input
@@ -139,4 +151,3 @@ extrapolate them for all channels._
13. Do steps 1-10 for every channel
_Note: default setting values are usually the same across channels, so you can extrapolate them for all channels._
-
diff --git a/src/hw/clocker.md b/src/hw/clocker.md
index 57a58d0..1f6f114 100644
--- a/src/hw/clocker.md
+++ b/src/hw/clocker.md
@@ -15,28 +15,29 @@ You may also need to add `"refclk": ` field to the target card.
For tests, you may need an external RF generator, depending on customer needs.
Here is example setup for SynthNV RF signal generator:
-1. Connect SynthNV to the workstation via USB, and
+1. Connect SynthNV to the workstation via USB, and
2. Install and run `cutecom`: `nix-shell -p cutecom`
3. Set settings as on the picture below:
-
+ 
4. Open the device, usually it is `/dev/ttyACM0`
5. Put `?` into `Input` field and press `Enter` for current settings and help commands
6. For changing the frequency, enter `f`, e.g. `f125.0` for 125 MHz
7. Set RF power so that clocker would recognize the signal with `a` command, e.g. `a63`
8. Check for desired amplitude and frequency at the `RFOut` (see picture below for reference) pin via oscilloscope
-
+ 
9. If everything is ok, connect `RFOut` to the `CLK IN` on the Clocker (see instructions below for details)
### Setup the Clocker
1. Switch `CLK SEL` pin to `EXT`/`INT` according to customer needs
-2. Connect MMCx cables according to the customer needs and boards specifications (see image below for reference):
- if the `INT` source is chosen, connect MMCx cable to `INT CLK`, otherwise connect external clocker to SMA `EXT CLK`
+2. Connect MMCx cables according to the customer needs and boards specifications (see image below for reference):
+ if the `INT` source is chosen, connect MMCx cable to `INT CLK`, otherwise connect external clocker to SMA `EXT CLK`
3. Connect the Clocker to the Kasli via 30-pin ports, or via external power supply
- 
+ 
4. Connect the Clocker's SMA output to the Kasli's `CLK`/`CLK IN` SMA pin
5. After assembling the crates and flashing the firmware, start Kasli and set config if needed:
- `artiq_coremgmt config write -s rtio_clock ext0_bypass`. Please refer to the [official manual](https://m-labs.hk/artiq/manual/core_device.html#clocking)
+ `artiq_coremgmt config write -s rtio_clock ext0_bypass`.
+ Please refer to the [official manual](https://m-labs.hk/artiq/manual/core_device.html#clocking)
for the details and available options. In most cases you may skip this step.
6. Reboot either via `artiq_coremgmt reboot` or via power supply if the board's firmware doesn't have such command
@@ -45,10 +46,12 @@ Here is example setup for SynthNV RF signal generator:
Run `artiq_sinara_test` and check that it doesn't fail on the connected devices.
Alternatively, if it would be shipped standalone:
+
1. Switch to external source
2. Connect to the external `CLK IN` clock source (frequency generator) via SMA cable
3. Power up Clocker with power supply or EEM
-4. Check via oscilloscope all (internal and external) clocker outputs, that they output clock signal respective to the input frequency
+4. Check via oscilloscope all (internal and external) clocker outputs, that they output clock signal
+ respective to the input frequency
5. Shut down Clocker
6. Switch to internal source
7. Connect clock source to the internal `CLK IN` via MMCx cable
diff --git a/src/hw/grabber.md b/src/hw/grabber.md
index e5d50f1..c4366ff 100644
--- a/src/hw/grabber.md
+++ b/src/hw/grabber.md
@@ -17,4 +17,4 @@ Activate the camera's frame grabber output, type 'g', press ENTER, and trigger t
Just press ENTER to skip the test.
```
-**TODO**
\ No newline at end of file
+## TODO
diff --git a/src/hw/hardware.md b/src/hw/hardware.md
index 5094709..e8cc1bf 100644
--- a/src/hw/hardware.md
+++ b/src/hw/hardware.md
@@ -4,4 +4,5 @@ In this section you will find instructions on testing the hardware.
If you didn't find one for your hardware, feel free to compose and add your instruction.
Useful links:
-* [Sinara Wiki](https://github.com/sinara-hw/meta/wiki)
\ No newline at end of file
+
+* [Sinara Wiki](https://github.com/sinara-hw/meta/wiki)
diff --git a/src/hw/kasli.md b/src/hw/kasli.md
index b30fe9c..be0aba4 100644
--- a/src/hw/kasli.md
+++ b/src/hw/kasli.md
@@ -1,7 +1,9 @@
# Kasli
## Mounting fan onto heatsink
-
+
+
+
1. ⚠️ Verify the fan has the **correct polarity (powering on with wrong polarity will burn the MOSFET in series💥)**
2. Place the fan on a heatsink
3. Tap 3 threads on the heatsink using M2.5 pointy tapping screws (e.g. front panel screws)
diff --git a/src/hw/kasli_soc.md b/src/hw/kasli_soc.md
index 253cb35..a3df8b1 100644
--- a/src/hw/kasli_soc.md
+++ b/src/hw/kasli_soc.md
@@ -5,10 +5,12 @@
Check the BOOT mode switches - they both should be at SD if the Kasli-SoC going to be shipped to customer.
POR jumper needs only for JTAG mode.
-
+
## Mounting fan onto heatsink
-
+
+
+
1. ⚠️ Verify the fan has the **correct polarity (powering on with wrong polarity will burn the MOSFET in series💥)**
2. Place the fan on a heatsink
3. Tap 3 threads on the heatsink using M2.5 pointy tapping screws (e.g. front panel screws)
diff --git a/src/hw/lvds_dio.md b/src/hw/lvds_dio.md
index 35f2168..93db2ee 100644
--- a/src/hw/lvds_dio.md
+++ b/src/hw/lvds_dio.md
@@ -31,7 +31,7 @@ Be aware of the reversed EEM order on the card:
Switch DIPs in required position per each channel individually. Each RJ45 have 4 channels.
-
+
## Testing
@@ -70,10 +70,12 @@ Connect ttl1 to ttl7. Press ENTER when done.
FAILED
...
```
+
1. Connect a RJ45 output port to a input port
2. Run `artiq_sinara_tester`
3. One TTL will pass while other will fail
-4. Run `artiq_sinara_tester` again and increment the stimulus (e.g. `ttl0->ttl1->ttl2->ttl3`) until all channels on the input port passed at least once
+4. Run `artiq_sinara_tester` again and increment the stimulus (e.g. `ttl0->ttl1->ttl2->ttl3`)
+ until all channels on the input port passed at least once
5. Plug into to another input port and repeat 2-4 until all input ports are tested
-It is incompatible with other TTL cards, so you will need to use same or other LVDS card for proper testing.
\ No newline at end of file
+It is incompatible with other TTL cards, so you will need to use same or other LVDS card for proper testing.
diff --git a/src/hw/mcx_ttl.md b/src/hw/mcx_ttl.md
index b9e679c..cc3cf3f 100644
--- a/src/hw/mcx_ttl.md
+++ b/src/hw/mcx_ttl.md
@@ -3,7 +3,7 @@
* [Wiki](https://github.com/sinara-hw/DIO_MCX/wiki)
* [Datasheet](https://m-labs.hk/docs/sinara-datasheets/2238.pdf)
-# JSON
+## JSON
```json
[
@@ -33,9 +33,9 @@ and 2 entries in the JSON.
Switch the direction switches (shown on the picture below) according to customer requests.
Remember, that you can only switch directions in groups of four.
-
+
## Test
-Refer to the [BNC/SMA TTL instructions](bnc_sma_ttl.md) for testing, but chose appropriate connector,
-and respect increased number of channels.
\ No newline at end of file
+Refer to the [BNC/SMA TTL instructions](bnc_sma_ttl.md) for testing, but chose appropriate connector,
+and respect increased number of channels.
diff --git a/src/hw/mirny_almazny.md b/src/hw/mirny_almazny.md
index bb66dba..6c5e2d4 100644
--- a/src/hw/mirny_almazny.md
+++ b/src/hw/mirny_almazny.md
@@ -18,23 +18,29 @@
## Getting the firmware
-On Hydra you can find [Mirny 0.3.1 firmware](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-release). It contains a single `.jed` file that can be flashed following [flashing instructions](#flashing). This firmware supports Almazny v1.2+.
+On Hydra you can find [Mirny 0.3.1 firmware](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-release).
+It contains a single `.jed` file that can be flashed following [flashing instructions](#flashing).
+This firmware supports Almazny v1.2+.
-If you are using a legacy Almazny (v1.0-1.1), due to different signals routed, you need to flash the older [0.2.4 firmware with Almazny support](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-legacy-almazny).
+If you are using a legacy Almazny (v1.0-1.1), due to different signals routed, you need to flash the older
+[0.2.4 firmware with Almazny support](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-legacy-almazny).
### Building firmware (optional)
However, if you need to make chances or build from source, follow these instructions.
-Once you get your hands on the firmware source code, you will need to work around few shortcomings of Nix, mainly not being able to run dynamically linked executables.
+Once you get your hands on the firmware source code, you will need to work around few shortcomings of Nix, mainly
+not being able to run dynamically linked executables.
You will need:
-- Xilinx ISE 14.7 installed on your system (this guide is assuming `/opt/Xilinx` path),
-- an environment with Migen.
-One way to do it is to create an FHS environment, like ARTIQ does for Vivado, within ARTIQ's `flake.nix` (to leverage Migen already being there), by adding these lines:
+* Xilinx ISE 14.7 installed on your system (this guide is assuming `/opt/Xilinx` path),
+* an environment with Migen.
-```
+One way to do it is to create an FHS environment, like ARTIQ does for Vivado, within ARTIQ's `flake.nix`
+(to leverage Migen already being there), by adding these lines:
+
+```nix
iseEnv = pkgs.buildFHSEnv {
name = "ise-env";
targetPkgs = vivadoDeps;
@@ -62,7 +68,8 @@ python mirny_impl.py
### Flashing
-For flashing, you will need Xilinx ISE 14.7 installed on your system (here assuming `/opt/Xilinx` path), and `xc3sprog` with the appropriate HS2 JTAG adapter.
+For flashing, you will need Xilinx ISE 14.7 installed on your system (here assuming `/opt/Xilinx` path), and `xc3sprog`
+with the appropriate HS2 JTAG adapter.
```shell
nix-shell -p xc3sprog
@@ -80,13 +87,13 @@ mirny0_cpld...
...done
All mirny channels active.
Frequencies:
-mirny0_ch0 1000MHz
+mirny0_ch0 1000MHz
mirny0_ch0 info: {'f_outA': 1000000000.0, 'f_outB': 8000000000, 'output_divider': 4, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch1 1100MHz
+mirny0_ch1 1100MHz
mirny0_ch1 info: {'f_outA': 1100000000.0, 'f_outB': 8800000000, 'output_divider': 4, 'f_vco': 4400000000, 'pll_n': 44, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch2 1200MHz
+mirny0_ch2 1200MHz
mirny0_ch2 info: {'f_outA': 1200000000.0, 'f_outB': 9600000000, 'output_divider': 4, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch3 1300MHz
+mirny0_ch3 1300MHz
mirny0_ch3 info: {'f_outA': 1300000000.0, 'f_outB': 10400000000, 'output_divider': 4, 'f_vco': 5200000000, 'pll_n': 52, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
```
@@ -101,7 +108,7 @@ After running `artiq_sinara_test`:
7. You should see significant signal emission on choosen freq compared to nearby freqs (see image below)
8. Repeat 5-7 for every channel
-
+
### With Almazny (ARTIQ 7)
@@ -116,21 +123,21 @@ mirny0_cpld...
mirny1_cpld...
...done
Testing attenuators. Frequencies:
-mirny0_ch0 4000MHz
+mirny0_ch0 4000MHz
mirny0_ch0 info: {'f_outA': 2000000000.0, 'f_outB': 8000000000, 'output_divider': 2, 'f_vco': 4000000000, 'pll_n': 40, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch1 4100MHz
+mirny0_ch1 4100MHz
mirny0_ch1 info: {'f_outA': 2050000000.0, 'f_outB': 8200000000, 'output_divider': 2, 'f_vco': 4100000000, 'pll_n': 41, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch2 4200MHz
+mirny0_ch2 4200MHz
mirny0_ch2 info: {'f_outA': 2100000000.0, 'f_outB': 8400000000, 'output_divider': 2, 'f_vco': 4200000000, 'pll_n': 42, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny0_ch3 4300MHz
+mirny0_ch3 4300MHz
mirny0_ch3 info: {'f_outA': 2150000000.0, 'f_outB': 8600000000, 'output_divider': 2, 'f_vco': 4300000000, 'pll_n': 43, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny1_ch0 4500MHz
+mirny1_ch0 4500MHz
mirny1_ch0 info: {'f_outA': 2250000000.0, 'f_outB': 9000000000, 'output_divider': 2, 'f_vco': 4500000000, 'pll_n': 45, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny1_ch1 4600MHz
+mirny1_ch1 4600MHz
mirny1_ch1 info: {'f_outA': 2300000000.0, 'f_outB': 9200000000, 'output_divider': 2, 'f_vco': 4600000000, 'pll_n': 46, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny1_ch2 4700MHz
+mirny1_ch2 4700MHz
mirny1_ch2 info: {'f_outA': 2350000000.0, 'f_outB': 9400000000, 'output_divider': 2, 'f_vco': 4700000000, 'pll_n': 47, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
-mirny1_ch3 4800MHz
+mirny1_ch3 4800MHz
mirny1_ch3 info: {'f_outA': 2400000000.0, 'f_outB': 9600000000, 'output_divider': 2, 'f_vco': 4800000000, 'pll_n': 48, 'pll_frac1': 0, 'pll_frac2': 0, 'pll_mod2': 1, 'prescaler': '4/5', 'sysclk': 100000000.0, 'ref_doubler': False, 'ref_divider': False, 'ref_counter': 1, 'f_pfd': 100000000}
RF ON, all attenuators ON. Press ENTER when done.
@@ -148,11 +155,11 @@ RF OFF. Press ENTER when done.
Similar to _Without Almazny_, check mirnies' channels emissions on defined frequencies.
You should also see differences in various modes, but that may require disabling the gain.
-
### Tips
-~~Mirnies often fail `ValueError: MUXOUT not high`, in that case restart the tests or reboot the board(s).~~ - fixed in [9569cfb](https://github.com/m-labs/artiq/commit/9569cfb26329c0acdc1705d3256d2506b7bccce5)
+~~Mirnies often fail `ValueError: MUXOUT not high`, in that case restart the tests or reboot the board(s).~~ - fixed
+in [9569cfb](https://github.com/m-labs/artiq/commit/9569cfb26329c0acdc1705d3256d2506b7bccce5)
For Almazny v1.0 and 1.1 support, CPLD firmware 0.2.4 (linked above) must be flashed onto Mirny.
-For Almazny v1.2+ support, CPLD firmware 0.3.1+ (with fixes) must be flashed onto Mirny.
\ No newline at end of file
+For Almazny v1.2+ support, CPLD firmware 0.3.1+ (with fixes) must be flashed onto Mirny.
diff --git a/src/hw/phaser.md b/src/hw/phaser.md
index 6bd8605..c392643 100644
--- a/src/hw/phaser.md
+++ b/src/hw/phaser.md
@@ -33,9 +33,8 @@ phaser0 10+0 10+1 10+2 10+3 10+4 MHz
in `Receiver Options`
7. Connect the probe through attenuator to the Phaser's RF ports
8. You should see 5 tones on `artiq_sinara_test`'s frequencies, like on the pictures below for RF0 and RF1 respectively:
- 
- 
-
+ 
+ 
### Baseband
diff --git a/src/hw/sampler.md b/src/hw/sampler.md
index 31f8940..501d719 100644
--- a/src/hw/sampler.md
+++ b/src/hw/sampler.md
@@ -33,4 +33,4 @@ PASSED
1. Apply 1.5V (connect the AA-battery) to the `samplerX`'s requested channel
2. Press `Enter`, the `artiq_sinara_test` should output `PASSED`
3. Repeat steps 1-2 for every available channel.
-4. Disassemble AA-battery tool as it risks getting corrosion
\ No newline at end of file
+4. Disassemble AA-battery tool as it risks getting corrosion
diff --git a/src/hw/shuttler.md b/src/hw/shuttler.md
index 864c1cf..9d2fab8 100644
--- a/src/hw/shuttler.md
+++ b/src/hw/shuttler.md
@@ -1,8 +1,12 @@
# Sinara 5716 DAC Shuttler
-The Sinara 5716 DAC Shuttler consists of the [Shuttler](https://github.com/sinara-hw/Shuttler), [Remote AFE-Board](https://github.com/sinara-hw/Shuttler), and [EEM FMC Carrier](https://github.com/sinara-hw/EEM_FMC_Carrier) (EFC) Board.
+The Sinara 5716 DAC Shuttler consists of the [Shuttler](https://github.com/sinara-hw/Shuttler),
+[Remote AFE-Board](https://github.com/sinara-hw/Shuttler), and
+[EEM FMC Carrier](https://github.com/sinara-hw/EEM_FMC_Carrier) (EFC) Board.
-The EFC Board has an FPGA running Kasli Satellite. DRTIO communication is established through the EEM Cable. At first power up, EFC Board and connected Kasli/Kasli-soc calibrate the clock skews on their own EEM transceiver and then store the value into the flash memory/SD Card.
+The EFC Board has an FPGA running Kasli Satellite. DRTIO communication is established through the EEM Cable.
+At first power up, EFC Board and connected Kasli/Kasli-soc calibrate the clock skews on their own EEM transceiver
+and then store the value into the flash memory/SD Card.
## JSON
@@ -14,9 +18,11 @@ The EFC Board has an FPGA running Kasli Satellite. DRTIO communication is establ
```
## Hardware Configurations and Connections
-### EEM Cable Connection
-Only the EEM0 port on the EFC board is used. The EEM Cable provides power. You can ignore the barrel jack at the back of the board if it is placed.
+### EEM Cable Connection
+
+Only the EEM0 port on the EFC board is used. The EEM Cable provides power. You can ignore the barrel jack at
+the back of the board if it is placed.
### CLK Input
@@ -36,32 +42,40 @@ For the EFC Board v1.1 (or later), there is a DIP switch to select the clock sou
### VADJ Power
-The EFC Board has configurable Digital IO Voltage Level/PSU called VADJ. You should configure VADJ to 1.8V by fitting W1/W2 jumper accordingly.
+The EFC Board has configurable Digital IO Voltage Level/PSU called VADJ. You should configure VADJ to 1.8V by
+fitting W1/W2 jumper accordingly.
-
### Remote AFE Board Connections
-The Remote AFE Board is not installed in the crate and should be shipped separately. When you test the EFC Board, please connect the Mini SAS Cables in this orientation.
+The Remote AFE Board is not installed in the crate and should be shipped separately. When you test the EFC Board,
+please connect the Mini SAS Cables in this orientation.
-There is no PSU for the Remote AFE Board at this moment. For testing purposes, you should connect the Remote AFE Board to a lab PSU supplying +15V, -15V, and +5V. Please make sure all voltages share a common GND and check the pinouts carefully. Incorrect power connections can damage the Remote AFE Board.
+There is no PSU for the Remote AFE Board at this moment. For testing purposes, you should connect the Remote AFE
+Board to a lab PSU supplying +15V, -15V, and +5V. Please make sure all voltages share a common GND and check the
+pinouts carefully. Incorrect power connections can damage the Remote AFE Board.
## Building EFC Board Gateware and Firmware
The EFC Board gateware and firmware are on the [Artiq](https://github.com/m-labs/artiq) repo.
To build the gateware and firmware,
-```
+
+```shell
python -m artiq.gateware.targets.efc --hw-rev [v1.0, v1.1]
```
## Routing Table Configuration if Shuttler is Connected to Kasli Satellite
-When Kasli Satellite is compiled with Shuttler, Shuttler is connected to the Satellite Repeater instance. Therefore, you will need to specify the routing table on the Kasli/Kasli-soc master in order to access the Shuttler hardware. Shuttler locates at DEST 4 connecting to Repeater ID #3. The ID number goes up accordingly if more than one Shuttler is connected.
+When Kasli Satellite is compiled with Shuttler, Shuttler is connected to the Satellite Repeater instance. Therefore,
+you will need to specify the routing table on the Kasli/Kasli-soc master in order to access the Shuttler hardware.
+Shuttler locates at DEST 4 connecting to Repeater ID #3. The ID number goes up accordingly if more than one
+Shuttler is connected.
Here provides an example to configure the routing table.
-You have 1 Kasli Master and 1 Kasli Satellite. Kasli Master (SFP1)(DEST1) port is connected to Kasli Satellite(SFP0)(DEST0). Shuttler is connected to Kasli Satellite with DRTIO over EEM Cable(DEST4).
+You have 1 Kasli Master and 1 Kasli Satellite. Kasli Master (SFP1)(DEST1) port is connected to
+Kasli Satellite(SFP0)(DEST0). Shuttler is connected to Kasli Satellite with DRTIO over EEM Cable(DEST4).
1. Initialize the Routing Table: `artiq_route rt.bin init`
2. Add the routing table entry for Kasli Master's Peripherals: `artiq_route rt.bin set 0 0`
@@ -71,9 +85,12 @@ You have 1 Kasli Master and 1 Kasli Satellite. Kasli Master (SFP1)(DEST1) port i
## Flashing
-When you are building a crate with shuttler(s), you should erase the flash/sd card config on both the EFC and Kasli/Kasli-soc. Always flash the EFC Board first before flashing the Kasli/Kasli-soc.
+When you are building a crate with shuttler(s), you should erase the flash/sd card config on both the EFC and
+Kasli/Kasli-SoC. Always flash the EFC Board first before flashing the Kasli/Kasli-soc.
+
+If either of the following elements is changed, you will need to **ERASE** the stored calibrated values on both
+the EFC and Kasli Master, or the communication between the boards cannot be established:
-If either of the following elements is changed, you will need to **ERASE** the stored calibrated values on both the EFC and Kasli Master, or the communication between the boards cannot be established:
1. EEM Cable
2. Clock-Related Cable
3. EFC Board Gateware
@@ -81,12 +98,14 @@ If either of the following elements is changed, you will need to **ERASE** the s
5. EFC Board/Kasli/Kasli-Soc PCB
To erase the flash on the EFC board,
-```
+
+```shell
artiq_flash -t efc erase
```
To flash the gateware and firmware onto the EFC board,
-```
+
+```shell
artiq_flash --srcbuild -t [efc1v0, efc1v1] -d artiq_efc/shuttler
```
@@ -95,10 +114,9 @@ artiq_flash --srcbuild -t [efc1v0, efc1v1] -d artiq_efc/shuttler
1. Connect the Remote AFE Card to the Shuttler
2. Power up the Remote AFE Board and the Kasli/Kasli-Soc with the connected Shuttler.
3. Check all Remote AFE Board Power Indicator LEDs.
-4. Run the `artiq_sinara_test`.
+4. Run the `artiq_sinara_test`.
-
-```
+```text
*** Testing LEDs.
Check for blinking. Press ENTER when done.
...
diff --git a/src/hw/stabilizer.md b/src/hw/stabilizer.md
index 4c53fec..bd10dd6 100644
--- a/src/hw/stabilizer.md
+++ b/src/hw/stabilizer.md
@@ -22,19 +22,20 @@ These all include changes to the mainline code to include Pounder telemetry.
### Building (optional)
-Please keep in mind that the firmware from the official Quartiq repository does not include support for Pounder in MQTT,
+Please keep in mind that the firmware from the official Quartiq repository does not include support for Pounder in MQTT,
you may need to use a fork for that. But if the stabilizer is without a Pounder, it's also a valid option.
-There is no Nix Flake support to make things easier, so you need to set up rust and cargo manually.
-Start with cloning the stabilizer repository and opening a new shell with dfu-util (for flashing) and rustup (for building).
+There is no Nix Flake support to make things easier, so you need to set up rust and cargo manually.
+Start with cloning the stabilizer repository and opening a new shell with dfu-util (for flashing) and rustup
+(for building).
-```
+```shell
nix-shell -p dfu-util rustup
```
Set up the toolchain, this should be done only once:
-```
+```shell
rustup target add thumbv7em-none-eabihf
cargo install cargo-binutils
rustup component add llvm-tools-preview
@@ -44,7 +45,7 @@ rustup default stable
Building:
-```
+```shell
cargo build --release
cargo objcopy --release --bin dual-iir -- -O binary dual-iir.bin
```
@@ -53,7 +54,8 @@ cargo objcopy --release --bin dual-iir -- -O binary dual-iir.bin
Once you have the binary, you can now flash it.
-1. Without firmware on the device or with older firmware (without USB serial console), you need to use the jumper method:
+1. Without firmware on the device or with older firmware (without USB serial console),
+ you need to use the jumper method:
1. Have the Stabilizer disconnected from power.
2. Use a jumper of some sort to short BOOT pins on the board.
3. Turn on the power.
@@ -61,30 +63,34 @@ Once you have the binary, you can now flash it.
2. With newer firmware with USB serial console:
1. Connect the Stabilizer to power.
2. Connect USB cable to the Stabilizer.
- 3. Ensure you have `pyserial` module either with `nix-shell -p python312Packages.pyserial` for NixOS users
+ 3. Ensure you have `pyserial` module either with `nix-shell -p python312Packages.pyserial` for NixOS users
or using `pip install pyserial` if you are using venv.
4. Run `python -m serial /dev/ttyACM0` to connect the serial port using `pyserial`.
5. Input `platform dfu` in the console.
3. Once the device is now in DFU mode, flash the device with the following command (needs `nix-shell -p dfu-util`):
- ```
+
+ ```shell
dfu-util -a 0 -s 0x08000000:leave -R -D stabilizer-dual-iir.bin
```
+
4. Look for "File downloaded successfully".
-For normal usage, the stabilizer must be configured with USB console later (try `help` command first),
-to set its IP address and MQTT broker address. However, for general testing (like the one below), you don't need to
+For normal usage, the stabilizer must be configured with USB console later (try `help` command first),
+to set its IP address and MQTT broker address. However, for general testing (like the one below), you don't need to
configure it any further.
### Clearing settings
-In case someone sets some setting wrongly, or updates the firmware and suddenly there's an incompatibility,
+In case someone sets some setting wrongly, or updates the firmware and suddenly there's an incompatibility,
you may find (firmware, not yourself) in a state of panic, where it will not allow you to change the settings back.
1. Get into DFU mode (described above), probably with jumper method.
2. Use dfu-util to clear the flash completely:
- ```
+
+ ```shell
dfu-util -a 0 -s 0x08000000:mass-erase:force:leave
```
+
3. Reflash the target firmware.
## Testing
@@ -93,16 +99,17 @@ you may find (firmware, not yourself) in a state of panic, where it will not all
2. Turn on the crate/Stabilizer via EEM cable or power supply
3. Set up the signal generator for an amplitude of 1V, frequency of 10kHz, and a sine wave
4. Use the splitter to connect the generator's output to ADC0 and to the oscilloscope (refer to the picture below)
- 
+ 
5. Configure the oscilloscope so that the sine wave is clearly visible
6. Connect the second channel of the oscilloscope to the Stabilizer's DAC0
7. Ensure that there is the same wave on the second channel, with a small delay, as on the first channel
8. Repeat steps 4-7 for ADC/DAC1 (refer to the picture below for connection reference)
- 
+ 
## Setting up MQTT
-For testing the Stabilizer, it's usually enough to do the settings above, as signal is filtered by the firmware. However, if you need to test the network connectivity or Pounder telemetry, MQTT may come useful.
+For testing the Stabilizer, it's usually enough to do the settings above, as signal is filtered by the firmware.
+However, if you need to test the network connectivity or Pounder telemetry, MQTT may come useful.
On PC side:
@@ -121,4 +128,5 @@ Configure Stabilizer:
4. Change the broker setting with: ``set /net/broker ""``.
5. Reboot with ``platform reboot``.
-Now, disconnect the USB and connect the Ethernet cable to the Stabilizer, as both won't fit at the same time. Stabilizer should connect to moquitto automatically, and you should see the MQTT settings pop up in the MQTT Explorer.
\ No newline at end of file
+Now, disconnect the USB and connect the Ethernet cable to the Stabilizer, as both won't fit at the same time.
+Stabilizer should connect to moquitto automatically, and you should see the MQTT settings pop up in the MQTT Explorer.
diff --git a/src/hw/suservo.md b/src/hw/suservo.md
index 8320fab..b2f545f 100644
--- a/src/hw/suservo.md
+++ b/src/hw/suservo.md
@@ -17,17 +17,18 @@ With enabled SUServo mode, you only need to add `suservo` to JSON file, with its
## Setup
To enable, on bottoms of each Urukul, switch first switches 1 and 2 to `ON`, as on the picture:
-
+
### Easier access to the switches (for big racks)
When the crate is assembled, it may be difficult to pull out the cards to access the switches.
Hence for big racks it may be easier to remove the upper perforated panel. For this:
+
1. Unscrew from both sides:
2. Remove empty front panels
3. Gently push out the perforated panel, applying the force from rack's back and front
-4. With tweezers and following the [basic operating hints](../build_test_firmware.md#operating-hints-and-warnings)
+4. With tweezers and following the [basic operating hints](../build_test_firmware.md#operating-hints-and-warnings)
switch the switches in desired direction
5. Install the perforated and front panels back, screw the screws
@@ -61,10 +62,12 @@ Verify frequency and power behavior.
```
1. Connect oscilloscope to the `urukul0` port and configure with time and voltage scale and trigger threshold
- so that you'll see sine wave, like on the picture: 
+ so that you'll see sine wave, like on the picture:
+ 
2. Verify amplitude and frequency
3. Apply 1.5V (connect the AA-battery) to the `sampler0` port, as on the
- picture: 
-4. You should see significant amplitude decrease, as in the picture: 
+ picture: 
+4. You should see significant amplitude decrease, as in the picture:
+ 
5. Verify amplitude difference, and the frequency to be unchanged
6. Repeat steps 1-5 for every available channel.
diff --git a/src/hw/thermostat.md b/src/hw/thermostat.md
index 53d447c..dda035f 100644
--- a/src/hw/thermostat.md
+++ b/src/hw/thermostat.md
@@ -29,6 +29,7 @@ You may also check fan controls via `fan` commands (see the firmware documentati
2. General TEC: connect external connector to the TEC
3. Connect Ethernet and PSU
4. Run:
+
```shell
git clone gitea@git.m-labs.hk:esavkin/thermostat.git
cd thermostat
@@ -36,18 +37,22 @@ You may also check fan controls via `fan` commands (see the firmware documentati
nix develop
python pytec/tec_qt.py
```
-5. In `Output Config`, set limits:
+
+5. In `Output Config`, set limits:
* `Max Cooling Current` - 400 mA
* `Max Heating Current` - 400 mA
* `Max Voltage Difference` - 1 V
-6. `PID Config` -> `PID Auto Tune` set desired target temperature, which should be slightly above your room temperature (+10C)
-7. Set `Thermistor Config` -> `B` and other values, according to the datasheet of the TEC module, for example for Zotino `B` is `3455 K`
-8. Run `PID Config` -> `PID Auto Tune` -> `Run` and check graphs that the measured temperature goes to the target temperature,
- and eventually stabilizes at +- 0.01 of the target
+6. `PID Config` -> `PID Auto Tune` set desired target temperature,
+ which should be slightly above your room temperature (+10C)
+7. Set `Thermistor Config` -> `B` and other values, according to the datasheet of the TEC module,
+ for example for Zotino `B` is `3455 K`
+8. Run `PID Config` -> `PID Auto Tune` -> `Run` and check graphs that the measured temperature
+ goes to the target temperature, and eventually stabilizes at +- 0.01 of the target
## Common problems
### Thermostat doesn't connect or doesn't enter DFU mode
-Carefully take out Thermostat from its protective box, unscrewed all screws before. Apply jumper and power on the Thermostat.
-Now it should be in DFU mode.
\ No newline at end of file
+Carefully take out Thermostat from its protective box, unscrewed all screws before.
+Apply jumper and power on the Thermostat.
+Now it should be in DFU mode.
diff --git a/src/hw/urukul.md b/src/hw/urukul.md
index df25623..45880c2 100644
--- a/src/hw/urukul.md
+++ b/src/hw/urukul.md
@@ -20,32 +20,36 @@
## Setup
-Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clock source - either Clocker,
-Kasli or external via SMA.
+Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs.
+Connect to the clock source - either Clocker, Kasli or external via SMA.
### Synchronization
-Phase synchronization enables phase control from Kasli/Kasli-SoC with an absolute phase reference, i.e. you can use the phase control API in the coredevice driver.
-Without synchronization the phase between Urukuls will not drift, but it can change across reboots, and the phase control API cannot be used.
-Synchronization requires Kasli and Urukul to be clocked from the same oscillator with <<1ns noise, otherwise the synchronization may fail, and that's
-why this feature is disabled by default.
-There is no intrinsic impact on Urukul output phase noise and the synchronization process is quick and reliable when done correctly.
+Phase synchronization enables phase control from Kasli/Kasli-SoC with an absolute phase reference,
+i.e. you can use the phase control API in the coredevice driver. Without synchronization the phase between Urukuls
+will not drift, but it can change across reboots, and the phase control API cannot be used. Synchronization requires
+Kasli and Urukul to be clocked from the same oscillator with <<1ns noise, otherwise the synchronization may fail,
+and that's why this feature is disabled by default. There is no intrinsic impact on Urukul output phase noise and
+the synchronization process is quick and reliable when done correctly.
### One-EEM mode
Users may choose to use only one EEM port, if they want more cards to be in their crate. However following features
will become unavailable:
- * SU-Servo
- * Low-latency RF switch control
- * Synchronization
-RF switches are still available but the commands need to go over the SPI bus so it's higher-latency and lower-resolution.
+* SU-Servo
+* Low-latency RF switch control
+* Synchronization
+
+RF switches are still available but the commands need to go over the SPI bus so it's higher-latency
+and lower-resolution.
### Urukul 4412
Urukul 4412 has higher frequency resolution (47 bit against 32 at Urukul 4410), however lacks such features:
- * SU-Servo
- * Synchronization
+
+* SU-Servo
+* Synchronization
## Testing
@@ -57,18 +61,18 @@ urukul0_cpld: initializing CPLD...
urukul0_cpld: testing attenuator digital control...
urukul0_cpld: done
Calibrating inter-device synchronization...
-urukul0_ch0 no EEPROM synchronization
-urukul0_ch1 no EEPROM synchronization
-urukul0_ch2 no EEPROM synchronization
-urukul0_ch3 no EEPROM synchronization
+urukul0_ch0 no EEPROM synchronization
+urukul0_ch1 no EEPROM synchronization
+urukul0_ch2 no EEPROM synchronization
+urukul0_ch3 no EEPROM synchronization
...done
All urukul channels active.
Check each channel amplitude (~1.6Vpp/8dbm at 50ohm) and frequency.
Frequencies:
-urukul0_ch0 10MHz
-urukul0_ch1 11MHz
-urukul0_ch2 12MHz
-urukul0_ch3 13MHz
+urukul0_ch0 10MHz
+urukul0_ch1 11MHz
+urukul0_ch2 12MHz
+urukul0_ch3 13MHz
Press ENTER when done.
Testing RF switch control. Check LEDs at urukul RF ports.
@@ -80,7 +84,6 @@ Press ENTER when done.
3. Measure frequencies and amplitudes on each connector, check with `artiq_sinara_test`'s respective values
4. When done, proceed with `artiq_sinara_test` and check LEDs are lighting up one after another
-
## Common problems
### Urukul AD9912 product id mismatch or missing LEDs
@@ -89,22 +92,27 @@ Press ENTER when done.
ValueError: Urukul AD9912 product id mismatch
```
-Some Urukuls may fail with this error during testing, usually meaning that the Urukul has not been flashed with the
-firmware, especially if the ID is `65535` (you will need to edit the code to check this).
+Some Urukuls may fail with this error during testing, usually meaning that the Urukul has not been flashed with the
+firmware, especially if the ID is `65535` (you will need to edit the code to check this).
-Another common symptom of no firmware is that no LEDs are lit up, besides Power Good - whereas if the firmware has been flashed, the RF channels will be lit red.
+Another common symptom of no firmware is that no LEDs are lit up, besides Power Good - whereas if the firmware has been
+flashed, the RF channels will be lit red.
You can flash the firmware yourself with a JTAG adapter:
-1. Download the latest binary release from [quartiq/urukul](https://github.com/quartiq/urukul) and extract the `urukul.jed` file.
-2. Connect the Urukul with the JTAG adapter to the PC and connect its EEM0 to any available Kasli/Kasli-SoC (**do not hot-plug**), then power on the Kasli/Kasli-SoC.
+1. Download the latest binary release from [quartiq/urukul](https://github.com/quartiq/urukul) and extract the
+ `urukul.jed` file.
+2. Connect the Urukul with the JTAG adapter to the PC and connect its EEM0 to any available Kasli/Kasli-SoC
+ (**do not hot-plug**), then power on the Kasli/Kasli-SoC.
3. Run `nix-shell -p xc3sprog`.
4. Run `xc3sprog -c jtaghs2 urukul.jed -m /opt/Xilinx/Vivado//data/xicom/cable_data/digilent/lnx64/xbr/`.
-5. If the last command outputs Verify: Success, then your Urukul is ready. It can also output the message
+5. If the last command outputs Verify: Success, then your Urukul is ready. It can also output the message
+
```shell
*** buffer overflow detected ***: terminated
Aborted (core dumped)
```
+
, which is okay if `Verify: Success` was also emitted.
### no valid window/delay
@@ -113,7 +121,7 @@ You can flash the firmware yourself with a JTAG adapter:
ValueError: no valid window/delay
```
-Check with the customer to see if synchronization is necessary, and disable it if it is not.
+Check with the customer to see if synchronization is necessary, and disable it if it is not.
In any case, simply restart the test.
### Noise instead of signal
@@ -122,8 +130,8 @@ It may be due to misconfiguration of SUServo. Check that both firmware and pins
### Improper frequency
-This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the customer needs,
-and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly.
+This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the
+customer needs, and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly.
### Urukul proto_rev mismatch
@@ -139,9 +147,9 @@ Check the ports are connected respectively to the JSON description.
ValueError: PLL lock timeout
```
-This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the customer needs,
-and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly and `EXT`/`INT` pin
-matches real clocker source.
+This can happen due to lack/bad clock source connection. Check that clock source is connected respective
+to the customer needs, and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal
+properly and `EXT`/`INT` pin matches real clocker source.
### Urukul AD9910 AUX_DAC mismatch
@@ -170,4 +178,4 @@ device_db["urukulX_cpld"] = {
"clk_div" : 1 # <--- add this line
}
}
-```
\ No newline at end of file
+```
diff --git a/src/hw/zotino_fastino.md b/src/hw/zotino_fastino.md
index c486934..9b82362 100644
--- a/src/hw/zotino_fastino.md
+++ b/src/hw/zotino_fastino.md
@@ -12,6 +12,7 @@
"ports": []
}
```
+
```json
{
"type": "fastino",
@@ -25,8 +26,8 @@ Fastino uses one physical EEM channel, despite having two EEM ports.
## Setup
-Connect the BNC/SMA-IDC adapters to the Zotino/Fastino with 26-pin cable if needed by customer. Be aware of the ports order -
-see reference numbers on the board.
+Connect the BNC/SMA-IDC adapters to the Zotino/Fastino with 26-pin cable if needed by customer.
+Be aware of the ports order - see reference numbers on the board.
## Testing
@@ -49,7 +50,6 @@ Press ENTER when done.
3. If there are [BNC/SMA-IDC adapters](./bnc_sma_idc_adapter.md), also check their voltages - they should be the same
4. Check LEDs are on
-
## Common problems
### High-freq audible noise and output values all near -0.1 on Zotino v1.4.2
@@ -61,19 +61,24 @@ This may happen when power-cycle is too short. Power down the crate, wait at lea
Some Fastino may not output any meaningful voltage during testing, usually that means it has no gateware flashed.
-Another common symptom of no gateware is that no LEDs are lit up. Whereas if the gateware has been flashed, the PG and FD LEDs will be lit green.
+Another common symptom of no gateware is that no LEDs are lit up. Whereas if the gateware has been flashed,
+the PG and FD LEDs will be lit green.
-You can flash the gateware with a Kasli/Kasli-SoC, be it in the crate or standalone (no specific gateware needed for Kasli/SoC):
+You can flash the gateware with a Kasli/Kasli-SoC, be it in the crate or standalone
+(no specific gateware needed for Kasli/SoC):
1. Download the latest `fastino.bin` release from [quartiq/fastino](https://github.com/quartiq/fastino/releases).
2. Run `git clone https://github.com/quartiq/kasli-i2c.git` and place `fastino.bin` in the kasli-i2c directory.
-3. Connect the Fastino's EEM0 to any available Kasli/Kasli-SoC EEM port ([**do not hot-plug**](../build_test_firmware.md#operating-hints-and-warnings)).
+3. Connect the Fastino's EEM0 to any available Kasli/Kasli-SoC EEM port
+ ([**do not hot-plug**](../build_test_firmware.md#operating-hints-and-warnings)).
You may skip this step if Fastino is connected within a crate.
4. Power on the standalone Kasli/Kasli-SoC and connect it to the PC via data micro-USB.
5. Run `nix-shell -p python311Packages.pyftdi`.
-6. Run `cd kasli-i2c; python flash_fastino.py 0 EEM write fastino.bin` where `` is the EEM port number on the Kasli/Kasli-SoC side.
+6. Run `cd kasli-i2c; python flash_fastino.py 0 EEM write fastino.bin` where ``
+ is the EEM port number on the Kasli/Kasli-SoC side.
7. If PG and FD LEDs are lit green, the Fastino is ready.
### Fastino output is 10V
-Fastinos by default after power up output 10V on all channels if not driven by the test otherwise. Make sure the EEM ports are specified correctly in the JSON and the EEM cable is connected to EEM0 on the Fastino.
+Fastinos by default after power up output 10V on all channels if not driven by the test otherwise.
+Make sure the EEM ports are specified correctly in the JSON and the EEM cable is connected to EEM0 on the Fastino.
diff --git a/src/sw_sup/afws_client.md b/src/sw_sup/afws_client.md
index 6679927..f62cfb0 100644
--- a/src/sw_sup/afws_client.md
+++ b/src/sw_sup/afws_client.md
@@ -6,46 +6,49 @@ This article is intended to help with using the `afws_client` command properly.
### What is AFWS
-AFWS (ARTIQ FirmWare Service) - a service, that allows building customer tailored firmware and gateware (binaries) on M-Labs's servers,
-and receive these binaries in ready-to-flash format. Subscription to this service also includes helpdesk support,
-and thus is paid on yearly basis (contact sales for prices). It is also typically included when purchasing Carrier (Kasli/Kasli-SoC) for a year,
-or one-time when purchasing standalone cards for existing crate. Each variant/carrier requires its own subscription.
+AFWS (ARTIQ FirmWare Service) - a service, that allows building customer tailored firmware and gateware (binaries)
+on M-Labs's servers, and receive these binaries in ready-to-flash format. Subscription to this service also includes
+helpdesk support, and thus is paid on yearly basis (contact sales for prices). It is also typically included when
+purchasing Carrier (Kasli/Kasli-SoC) for a year, or one-time when purchasing standalone cards for existing crate.
+Each variant/carrier requires its own subscription.
### What do I need for obtaining binaries
-You'll need to have credentials - username and password, which you can obtain from helpdesk, if you haven't yet.
+You'll need to have credentials - username and password, which you can obtain from helpdesk, if you haven't yet.
Don't forget to specify variant (sticker on top of the crate) that you need to obtain binaries for.
### When do I need to update
-In most cases there is no need to update the firmware, unless you encountered a bug and the fix was backported to your version.
-However, if you: changed the layout of the cards - either moved EEM connections, added or deleted cards;
-changed modes/configurations of the cards (e.g. enable/disable SUServo, synchronization, edge counter, SED lanes etc.).
-In such cases, these changes need to be authorized through helpdesk.
+In most cases there is no need to update the firmware, unless you encountered a bug and the fix was backported
+to your version. However, if you: changed the layout of the cards - either moved EEM connections, added or
+deleted cards; changed modes/configurations of the cards (e.g. enable/disable SUServo, synchronization, edge counter,
+SED lanes etc.). In such cases, these changes need to be authorized through helpdesk.
### How to
The base command looks like this:
+
```shell
afws_client build
```
Where (remove `<` and `>`):
+
* `` - your username from credentials
* `` - the directory/folder, into which you wish to save the binaries
* `` - name of the crate/variant. It's optional if you have only one variant in the account
After running this command, it will ask you for the password (the line will remain blank for security reasons).
-If everything matches (username and password are correct, specified variant is in your account and not expired),
-AFWS will start building the firmware, which takes 10-15 minutes. Sometimes there might be some problems, in which
+If everything matches (username and password are correct, specified variant is in your account and not expired),
+AFWS will start building the firmware, which takes 10-15 minutes. Sometimes there might be some problems, in which
case don't hesitate to contact helpdesk.
-After the build done, the AFWS client will automatically download the binaries into ``, from which
+After the build done, the AFWS client will automatically download the binaries into ``, from which
you can flash them into your Carrier.
#### View build logs
-You may want to view the build logs (for example, in case of problems with configuration).
+You may want to view the build logs (for example, in case of problems with configuration).
For this, add `--log` option after build:
```shell
@@ -54,28 +57,31 @@ afws_client build --log
#### Specify version
-By default, AFWS client tries to figure out the installed ARTIQ version. However it works only for Kasli, and not Kasli-SoC.
-It also may fail to determine ARTIQ version if you are using AFWS client without ARTIQ installation.
+By default, AFWS client tries to figure out the installed ARTIQ version. However it works only for Kasli, and
+not Kasli-SoC. It also may fail to determine ARTIQ version if you are using AFWS client without ARTIQ installation.
Additionally, you may want to specify version regardless of installed version.
-In all these cases, you'll need to specify **both** `--major-ver` and `--rev` arguments, so your command will look like this:
+In all these cases, you'll need to specify **both** `--major-ver` and `--rev` arguments, so your command
+will look like this:
```shell
afws_client build --major-ver --rev
```
Where:
-* `MAJOR_VER` - ARTIQ major version, either `7` (legacy), `8` (current stable),
+
+* `MAJOR_VER` - ARTIQ major version, either `7` (legacy), `8` (current stable),
`9` (current beta) or `10` (experimental with `nac3` compiler)
* `REV` - revision from respective branch and repository - i.e. commit hash. You may obtain it either from:
- * [ARTIQ repository](https://github.com/m-labs/artiq) (for Kasli 2.0 and earlier) by
+ * [ARTIQ repository](https://github.com/m-labs/artiq) (for Kasli 2.0 and earlier) by
[selecting branch](https://docs.github.com/en/repositories/configuring-branches-and-merges-in-your-repository/managing-branches-in-your-repository/viewing-branches-in-your-repository)
- and selecting `XXX commits` above list of files. From here, the list of commits in specified branch will appear
- and you will be able to choose the commit and press ["Copy full SHA for YYY"](https://docs.github.com/en/pull-requests/committing-changes-to-your-project/creating-and-editing-commits/about-commits#using-the-file-tree)
+ and selecting `XXX commits` above list of files. From here, the list of commits in specified branch will appear
+ and you will be able to choose the commit and press ["Copy full SHA for YYY"](https://docs.github.com/en/pull-requests/committing-changes-to-your-project/creating-and-editing-commits/about-commits#using-the-file-tree)
button in the right side.
- * [ARTIQ on Zynq repository](https://git.m-labs.hk/M-Labs/artiq-zynq) (for Kasli-SoC). In similar way to GitHub,
+ * [ARTIQ on Zynq repository](https://git.m-labs.hk/M-Labs/artiq-zynq) (for Kasli-SoC). In similar way to GitHub,
you can choose branch, commit history and copy SHA1 of the commit.
The branches currently map as following:
+
* ARTIQ-7 - release-7
* ARTIQ-8 - release-8
* ARTIQ-9 - master
@@ -87,16 +93,17 @@ cache (i.e. not rebuilt).
#### Change password
-After you received credentials from us, we strongly recommend changing the password as soon as possible via
+After you received credentials from us, we strongly recommend changing the password as soon as possible via
`afws_client passwd` command. This command will ask you for existing password and new desired password.
-The passwords are stored in a hashed way (i.e. cannot be decrypted back), however it's your responsibility to choose good passwords.
-Just keep in mind, that password may contain only alpha-numeric symbols and underscore `[a-zA-Z0-9_]`.
-If you cannot login, we may reset your password if you email us at helpdesk.
+The passwords are stored in a hashed way (i.e. cannot be decrypted back), however it's your responsibility to
+choose good passwords. Just keep in mind, that password may contain only alpha-numeric symbols and underscore
+`[a-zA-Z0-9_]`. If you cannot login, we may reset your password if you email us at helpdesk.
#### Get variants
You may get variants, which are tied to your account by using `get_variants` command:
+
```shell
afws_client get_variants
```
@@ -115,18 +122,17 @@ It will ask for password and output the variants and their respective expiry dat
#### Get JSONs
Sometimes you may want to view the JSON description, from which AFWS is building the variant. With the JSON, you can
-later build the firmware by yourself and/or generate device_db file. The command looks like this (variant
+later build the firmware by yourself and/or generate device_db file. The command looks like this (variant
needs to be valid, i.e. not expired and authorized in your account):
```shell
afws_client get_json [-o ] [-f]
```
-Specify output file `-o `, if you want to save it directly to file ``, use `-f` if you want to force
+Specify output file `-o `, if you want to save it directly to file ``, use `-f` if you want to force
overwrite. If you do not specify any of these options, you'll get the JSON description directly in stdin (i.e. in your
console/terminal).
-
#### Miscellaneous
You may also specify custom AFWS provider with these options (put them before username):
@@ -134,4 +140,3 @@ You may also specify custom AFWS provider with these options (put them before us
* `--server SERVER` - server to connect to (default: afws.m-labs.hk)
* `--port PORT` - port to connect to (default: 80)
* `--cert CERT` - SSL certificate file used to authenticate server (default: use system certificates)
-
diff --git a/src/sw_sup/artiq_legacy.md b/src/sw_sup/artiq_legacy.md
index 2d21f73..a014973 100644
--- a/src/sw_sup/artiq_legacy.md
+++ b/src/sw_sup/artiq_legacy.md
@@ -14,13 +14,14 @@ If there are any `nixpkgs` present already, comment them out with `#`.
Then add the following line:
-```
+```text
https://nixos.org/channels/nixos-21.05 nixpkgs
```
Save and exit.
-Now, we need special `nix-scripts` to configure building environment, and a local copy of the artiq repository, in legacy release.
+Now, we need special `nix-scripts` to configure building environment, and a local copy of the artiq repository,
+in legacy release.
```shell
mkdir artiq-legacy
@@ -32,7 +33,8 @@ git checkout release-6 # or release-5...
cd ..
```
-Keep in mind that ARTIQ-6 scripts have been removed in `nix-scripts`, so you may need to checkout the last commit that still has them.
+Keep in mind that ARTIQ-6 scripts have been removed in `nix-scripts`, so you may need to checkout the last commit
+that still has them.
```shell
cd nix-scripts
@@ -55,14 +57,17 @@ python -m artiq.gateware.targets.kasli_generic .json
```
If you are building legacy ARTIQ for local use and you want to flash it, use:
+
```shell
artiq_flash -V -d artiq_kasli --srcbuild
```
-There's a slight discrepancy from usual command - ``-V `` option is not present in ARTIQ-7+, but it is necessary here.
+There's a slight discrepancy from usual command - ``-V `` option is not present in ARTIQ-7+,
+but it is necessary here.
-If you want to send the binaries to a customer, there's no need packing up the whole build directory - only `top.bit`, `bootloader.bin`
-and `runtime.elf/fbi` or `satman.elf/fbi` are necessary. You can use the `prep_pkg.py` script from extras to package them up neatly into a zip file for distributions:
+If you want to send the binaries to a customer, there's no need packing up the whole build directory - only `top.bit`,
+`bootloader.bin` and `runtime.elf/fbi` or `satman.elf/fbi` are necessary. You can use the `prep_pkg.py` script from
+extras to package them up neatly into a zip file for distributions:
```shell
python prep_pkg.py -v -d artiq_kasli/
@@ -76,8 +81,9 @@ artiq_flash -V -d .
## ARTIQ-7
-The process of building firmware for ARTIQ-7 is mostly similar to ARTIQ-8, except there are no named RTIO channels
-and no remote reboot functionality on Kasli-SoC. DRTIO set ups are also similar to ARTIQ-8. [See reference](../build_test_firmware.md).
+The process of building firmware for ARTIQ-7 is mostly similar to ARTIQ-8, except there are no named RTIO channels
+and no remote reboot functionality on Kasli-SoC. DRTIO set ups are also similar to ARTIQ-8.
+[See reference](../build_test_firmware.md).
### Kasli, Kasli 2.0
@@ -108,4 +114,3 @@ artiq_coremgmt -D 192.168.1.56 config write -s ip 192.168.1.75 # or just place e
artiq_coremgmt config write -f boot result/boot.bin
# reboot via power supply
```
-
diff --git a/src/sw_sup/artiq_start.md b/src/sw_sup/artiq_start.md
index 8cad18f..7d0a83b 100644
--- a/src/sw_sup/artiq_start.md
+++ b/src/sw_sup/artiq_start.md
@@ -4,26 +4,31 @@ This page describes how to start with ARTIQ system for novice users.
## Connecting wires
-In most cases the system is shipped with power bricks (PSU), DC splitters and SFPs enough to power and control the whole system.
-Connect them in following order:
+In most cases the system is shipped with power bricks (PSU), DC splitters and SFPs enough to power and control the
+whole system. Connect them in following order:
+
1. Insert Ethernet SFP into the SFP0 of the master or standalone Kasli/Kasli-SoC (Carrier)
2. Connect these SFPs to the router or PC via Ethernet cable (in some cases, optical cable)
-3. Insert optic/direct attach SFPs into the master and satellite Carriers, respective to the numeration, [more info in DRTIO page](drtio.md)
+3. Insert optic/direct attach SFPs into the master and satellite Carriers, respective to the numeration,
+ [more info in DRTIO page](drtio.md)
4. Power on PSU or EEM power module, by inserting C14 cable, attach DC splitters if available
5. Some cards may have "External power" setting (check the quotation), in this case, insert DC connector into the port
6. Insert remaining cables into the Carriers (not applicable in case of EEM Power Module).
## Set the network
-By default standalone/master Carriers arrive with 192.168.1.75/24 set as their static address. Carrier will try to acquire this address
-from your router, and in case of failure, they will be just unavailable from the network. Check the following articles for troubleshooting network issues:
+By default standalone/master Carriers arrive with 192.168.1.75/24 set as their static address.
+Carrier will try to acquire this address from your router, and in case of failure, they will be just unavailable
+from the network. Check the following articles for troubleshooting network issues:
+
* [Networking](networking.md)
* [Official docs](https://m-labs.hk/artiq/manual/configuring.html)
## Run first experiment via artiq_run
-Before diving in to the repository experiments management and scheduling, it is essential to try run your first experiment
-via most basic way - `artiq_run`. For this you need to enter your ARTIQ environment (console) and run:
+Before diving in to the repository experiments management and scheduling, it is essential to try run your first
+experiment via most basic way - `artiq_run`. For this you need to enter your ARTIQ environment (console) and run:
+
```shell
artiq_run --device-db path/to/device_db.py path/to/experiment.py
```
@@ -32,7 +37,8 @@ In case your directory contains relevant `device_db` file, you may omit the `--d
To check this, you may run `ls .` and check if it is in the list.
On pre-installed NUCs, the ARTIQ commands are available everywhere, and you just need to run them.
-If you have Nix package manager or NixOS, you will just need to enter the shell with `nix develop github:m-labs/artiq\?ref=release-8`.
-If you have installed ARTIQ with Conda, you will need to activate the environment with `conda activate `.
+If you have Nix package manager or NixOS, you will just need to enter the shell with
+`nix develop github:m-labs/artiq\?ref=release-8`. If you have installed ARTIQ with Conda, you will need to activate
+the environment with `conda activate `.
-You may check for experiments in the [official docs](https://m-labs.hk/artiq/manual/getting_started_core.html).
\ No newline at end of file
+You may check for experiments in the [official docs](https://m-labs.hk/artiq/manual/getting_started_core.html).
diff --git a/src/sw_sup/clocking.md b/src/sw_sup/clocking.md
index 5100cec..acf0b8c 100644
--- a/src/sw_sup/clocking.md
+++ b/src/sw_sup/clocking.md
@@ -81,4 +81,4 @@ Main page: [clocker.md](../hw/clocker.md)
Clocker card allows to distribute clock signal up to 1 GHz without additional software setup. Therefore, there is no way
to set it to generate signal, which would be different from input. The only setup allowed is to set to accept signal
from `EXT`/`INT` ports, front-panel SMA or card's MMCX ports respectively, by switching the `CLK SEL` switch on the
-card .
\ No newline at end of file
+card .
diff --git a/src/sw_sup/drtio.md b/src/sw_sup/drtio.md
index 1a2a3dd..1c21a44 100644
--- a/src/sw_sup/drtio.md
+++ b/src/sw_sup/drtio.md
@@ -4,19 +4,20 @@ This page intends to help users solve problems with their DRTIO systems.
## Description (from user experience)
-[Distributed Real Time Input/Output](https://m-labs.hk/artiq/manual/drtio.html) - allows almost seamlessly connecting several satellites to one master crate,
-so that all the crates can be controlled as one whole crate. The connection between the crates is done either by passive copper
-direct attach cables (suitable for one-crate setups) or optical fibers SFP+ adapters (suitable for multiple crates that
-can be distributed up to [several kilometers](https://github.com/m-labs/artiq/issues/2022)). The DRTIO protocol is not
-compatible with Ethernet, and moreover, satellites do not have any network access and can be controlled only by master.
-However, both star (2 levels) and tree topologies are supported as well,
-with default one being the star (one master and up to 3-4 directly connected satellites), and if any chaining is needed, the
-routing table setup is needed.
-To switch between satellite/master/standalone variants you just need to flash appropriate firmware, and set the respective `base`
+[Distributed Real Time Input/Output](https://m-labs.hk/artiq/manual/drtio.html) - allows almost seamlessly connecting
+several satellites to one master crate, so that all the crates can be controlled as one whole crate.
+The connection between the crates is done either by passive copper direct attach cables (suitable for one-crate setups)
+or optical fibers SFP+ adapters (suitable for multiple crates that can be distributed up to
+[several kilometers](https://github.com/m-labs/artiq/issues/2022)). The DRTIO protocol is not compatible with Ethernet,
+and moreover, satellites do not have any network access and can be controlled only by master. However,
+both star (2 levels) and tree topologies are supported as well, with default one being the star (one master and up to
+3-4 directly connected satellites), and if any chaining is needed, the routing table setup is needed. To switch between
+satellite/master/standalone variants you just need to flash appropriate firmware, and set the respective `base`
field in the JSON description.
The master will attempt to connect the satellite whenever it sees that there are SFPs plugged in. For this purpose,
it will _ping_ the satellite until it establishes the connection. This connection process can be observed from the logs:
+
```rust
// successful connection
[ 5385.011286s] INFO(runtime::rtio_mgt::drtio): [LINK#1] link RX became up, pinging
@@ -30,24 +31,24 @@ it will _ping_ the satellite until it establishes the connection. This connectio
[ 115.076772s] ERROR(runtime::rtio_mgt::drtio): [LINK#1] ping failed
```
-During the connection, the clock signal is being distributed, effectively making the clocks across crates to be synchronized.
-
+During the connection, the clock signal is being distributed, effectively making the clocks across
+crates to be synchronized.
## Common problems
### Master and satellite do not connect with each other
-* Shady cables and SFP adapters are often the cause, use the adapters from reputable sources, or better, use the one we ship.
- You may also contact our helpdesk to get help in choosing the right adapters if needed.
-* The adapter is not pushed until the end. You shouldn't be able to pull out the adapters without pulling the petals/handles.
-* The fiber is not properly connected - you shouldn't be able to pull it out without squeezing the handle. Also the optics
- may be dirty or damaged.
+* Shady cables and SFP adapters are often the cause, use the adapters from reputable sources, or better,
+ use the one we ship. You may also contact our helpdesk to get help in choosing the right adapters if needed.
+* The adapter is not pushed until the end. You shouldn't be able to pull out the adapters without
+ pulling the petals/handles.
+* The fiber is not properly connected - you shouldn't be able to pull it out without squeezing the handle.
+ Also the optics may be dirty or damaged.
* Wrong setups - master to master, standalone to standalone. Messing up with SFP ports generally makes it unusable,
but the connection should be established in most cases.
* The fiber adapters are not symmetrical - if one end has 1270/1330 label, another one should be 1330/1270.
-
### Master-satellite interrupted/unstable connection
This often happens due to overheating issues. Check if the Kasli/SoC fans are working properly and
-try installing rack fans to increase the air flow.
\ No newline at end of file
+try installing rack fans to increase the air flow.
diff --git a/src/sw_sup/flashing_firmware.md b/src/sw_sup/flashing_firmware.md
index bdca734..cf930cb 100644
--- a/src/sw_sup/flashing_firmware.md
+++ b/src/sw_sup/flashing_firmware.md
@@ -9,12 +9,15 @@ Here are some extra steps needed for flashing the firmware.
From the [official manual](https://m-labs.hk/artiq/manual/flashing.html#installing-and-configuring-openocd):
On Windows, a third-party tool, Zadig, is necessary. Use it as follows:
+
1. Make sure the FPGA board’s JTAG USB port is connected to your computer.
2. Activate Options → List All Devices.
-3. Select the “Digilent Adept USB Device (Interface 0)” or “FTDI Quad-RS232 HS” (or similar) device from the drop-down list.
+3. Select the “Digilent Adept USB Device (Interface 0)” or “FTDI Quad-RS232 HS” (or similar)
+ device from the drop-down list.
4. Select WinUSB from the spinner list.
5. Click “Install Driver” or “Replace Driver”.
6. After above steps done, you may see the devices in the Device Manager:
-You may need to repeat these steps every time you plug the FPGA board into a port where it has not been plugged into previously on the same system.
\ No newline at end of file
+You may need to repeat these steps every time you plug the FPGA board into a port where it has not been
+plugged into previously on the same system.
diff --git a/src/sw_sup/moninj.md b/src/sw_sup/moninj.md
index 982c687..a61ff80 100644
--- a/src/sw_sup/moninj.md
+++ b/src/sw_sup/moninj.md
@@ -8,4 +8,3 @@ That's why the dashboard may emit errors about not working moninj. To fix this,
```shell
aqctl_moninj_proxy CORE_ADDRESS
```
-
diff --git a/src/sw_sup/networking.md b/src/sw_sup/networking.md
index 68879f9..53473b8 100644
--- a/src/sw_sup/networking.md
+++ b/src/sw_sup/networking.md
@@ -6,43 +6,49 @@ a-la `I can't connect, please help`.
## Common problems
1. `device_db.py` has misleading `core_addr` address.
-2. PC and the crate are in different subnets. They should be in the same network. Also you may want to directly attach the Kasli to the PC.
+2. PC and the crate are in different subnets. They should be in the same network. Also you may want to directly
+ attach the Kasli to the PC.
3. Network restrictions/problems on your router, either by IP, MAC, protocols or anything else.
-4. Wrong configuration of the Kasli. Change IP or MAC address to correspond your network. For ARTIQ-8 and later, add
+4. Wrong configuration of the Kasli. Change IP or MAC address to correspond your network. For ARTIQ-8 and later, add
network mask to the `ip` setting on Kasli (not applicable for Kasli-SoC), like `192.168.1.75/24`.
-5. Incompatible Ethernet cables/SFP RJ45. Try different cables and SFP adapters.
+5. Incompatible Ethernet cables/SFP RJ45. Try different cables and SFP adapters.
We usually test them with CAT6 cables, but lower categories should be supported too.
6. SFP or Ethernet are not pushed til the end.
7. Some weird bugs in Vivado, leading to not working SFP on certain combinations of builds and Kaslis (very rare)
-8. Running configured for external reference Kasli without external reference clock signal
+8. Running configured for external reference Kasli without external reference clock signal
9. Using legacy firmware with newer hardware. ARTIQ-6 doesn't support Kasli v2.0.2
10. Some other device in your network already reserved the configured IP address.
## Ways to diagnose
1. `ping` the device. If destination is unreachable, than it is either didn't connect to the network
- or connected to different address. If the packets just do not respond then it is not as clear, we cannot know all the truth.
+ or connected to different address. If the packets just do not respond then it is not as clear,
+ we cannot know all the truth.
2. See the SFP0 LED
3. See the ERR LED
4. [UART logs](uart_logs.md)
5. `nmap` and `arp` to scan your network to help your Kasli get discovered. May be restricted in your network.
-6. Directly connect your Kasli to the PC via Ethernet and set up networking on the PC: `ip addr change 192.168.1.0/24 dev eth0`
+6. Directly connect your Kasli to the PC via Ethernet and set up networking on the PC:
+ `ip addr change 192.168.1.0/24 dev eth0`
7. Become a router and capture all the packets when your Kasli tries to connect to the network.
8. Turn off the Carrier/Kasli and `ping` the configured IP address. If it pings, then you'll need either set different
- IP address on your Carrier or somehow deal with that other device - remove, assign different address, move to other network etc.
-
+ IP address on your Carrier or somehow deal with that other device - remove,
+ assign different address, move to other network etc.
## Direct connection
Sometimes it is neccessary to connect your Kasli/Kasli-SoC (Carrier) directly to the PC/NUC. For example, your Kasli-SoC
may be configured for the wrong network. In order to do this, you will just need to:
+
1. Connect Carrier via Ethernet directly to the NUC/PC
2. Set the network settings (example for default 192.168.1.75 Carrier setting):
- ```
+
+ ```text
IPv4 method: Manual
Address: 192.168.1.0
Netmask: 255.255.255.0
Gateway: 192.168.1.0
DNS, Routes - Auto
```
- 
\ No newline at end of file
+
+ 
diff --git a/src/sw_sup/pycharm.md b/src/sw_sup/pycharm.md
index ee1fa86..cdedc55 100644
--- a/src/sw_sup/pycharm.md
+++ b/src/sw_sup/pycharm.md
@@ -7,11 +7,11 @@ It's fairly possible to integrate PyCharm with ARTIQ on Windows.
Below is an example configuration, change it according your installation.
1. Set System Interpreter to MSYS2 CLANG64 one (pip packages are not supported):
- 
+ 
2. Set Terminal to use MSYS2 CLANG64 one:
- 
+ 
After this you will be able to look up definitions from ARTIQ and use convenient integrated Terminal to run `artiq_run`.
-
-_PyCharm is a registered trademark of JetBrains s.r.o.. For license information, please refer to the JetBrains website or the product documentation._
+_PyCharm is a registered trademark of JetBrains s.r.o.. For license information, please refer to the
+JetBrains website or the product documentation._
diff --git a/src/sw_sup/setup_build_pc.md b/src/sw_sup/setup_build_pc.md
index 9ca0c7b..dd727f9 100644
--- a/src/sw_sup/setup_build_pc.md
+++ b/src/sw_sup/setup_build_pc.md
@@ -1,25 +1,29 @@
# Setup your PC for building ARTIQ firmware
-This page should guide you through building the firmware on your own PC.
-Unfortunately, the building process is not possible on Windows natively (nor MSYS2),
+This page should guide you through building the firmware on your own PC.
+Unfortunately, the building process is not possible on Windows natively (nor MSYS2),
but you can use [WSL](https://learn.microsoft.com/en-us/windows/wsl/install).
## Prerequisites
-You should have a Linux with `nix` and `git` installed. For this purpose you may want to consider NixOS, though it is hard way for everything else.
-You should have at least 70+ GB of free space (better 100+ GB) on your `/opt` or `/` - most of this space will be taken
-by Vivado.
+You should have a Linux with `nix` and `git` installed. For this purpose you may want to consider NixOS,
+though it is hard way for everything else. You should have at least 70+ GB of free space (better 100+ GB) on
+your `/opt` or `/` - most of this space will be taken by Vivado.
## Installation
-1. Install Vivado 2022.2 from [Vivado archive](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html) into `/opt`.
+1. Install Vivado 2022.2 from [Vivado archive](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html)
+ into `/opt`.
2. Check that `ls -al /opt/Xilinx/Vivado/2022.2/settings64.sh` exists and has read and execute permissions for all:
+
```shell
$ ls -al /opt/Xilinx/Vivado/2022.2/settings64.sh
-rwxr-xr-x 1 nobody nogroup 245 Dec 17 2022 /opt/Xilinx/Vivado/2022.2/settings64.sh
```
-3. Add following into the `~/.local/share/nix/trusted-settings.json`, by `mkdir -p ~/.local/share/nix/ && nano ~/.local/share/nix/trusted-settings.json`
+
+3. Add following into the `~/.local/share/nix/trusted-settings.json`, by `mkdir -p ~/.local/share/nix/ && nano ~/.local/share/nix/trusted-settings.json`
or with your favorite way (don't forget to save - Ctrl+O in `nano`):
+
```json
{
"extra-sandbox-paths":{
@@ -33,12 +37,16 @@ by Vivado.
}
}
```
-4. Enable flakes in Nix and add `/opt` to sandbox e.g. adding following to the `nix.conf` (for example `~/.config/nix/nix.conf` or `/etc/nix/nix.conf`):
- ```
+
+4. Enable flakes in Nix and add `/opt` to sandbox e.g. adding following to the `nix.conf`
+ (for example `~/.config/nix/nix.conf` or `/etc/nix/nix.conf`):
+
+ ```text
experimental-features = nix-command flakes
extra-sandbox-paths = /opt
```
-5. On Ubuntu, the Nix will conflict with Apparmor. You'll need to disable Apparmor for Nix,
+
+5. On Ubuntu, the Nix will conflict with Apparmor. You'll need to disable Apparmor for Nix,
or for the whole system (you can also delete Apparmor completely, but be careful with it).
From here, you should be able to enter ARTIQ development shell directly from URL, or by cloning the repository.
@@ -53,6 +61,7 @@ nix develop #boards
```
For Kasli-SoC:
+
```shell
git clone https://git.m-labs.hk/M-Labs/artiq-zynq.git
cd artiq-zynq
@@ -63,6 +72,7 @@ For building instructions for your JSON, please refer to the [build and test ins
The reference uses commands like `nix develop github:m-labs/artiq\?ref=release-8#boards` and `nix develop git+https://git.m-labs.hk/m-labs/artiq-zynq\?ref=release-8`.
You may safely skip such commands if you entered the development shell (`nix develop`) from cloned git repository.
-If you want to update the source files, you may use `git pull origin master --rebase`.
-Please refer to the [git documentation](https://www.git-scm.com/docs) or other resources of your choice if you are unfamiliar with `git`.
-You may also use GUI git tools, like the one integrated into JetBrains IDEs (PyCharm, Intellij and others), VS Code, Sublime Merge or others.
+If you want to update the source files, you may use `git pull origin master --rebase`.
+Please refer to the [git documentation](https://www.git-scm.com/docs) or other resources of your choice
+if you are unfamiliar with `git`. You may also use GUI git tools, like the one integrated into JetBrains IDEs
+(PyCharm, Intellij and others), VS Code, Sublime Merge or others.
diff --git a/src/sw_sup/software_support.md b/src/sw_sup/software_support.md
index f2d8976..26ba380 100644
--- a/src/sw_sup/software_support.md
+++ b/src/sw_sup/software_support.md
@@ -7,4 +7,4 @@ In the future, it may be revised and added to the official ARTIQ manual.
I hope that helps!
-
\ No newline at end of file
+
diff --git a/src/sw_sup/uart_logs.md b/src/sw_sup/uart_logs.md
index b4fdc00..a1c099f 100644
--- a/src/sw_sup/uart_logs.md
+++ b/src/sw_sup/uart_logs.md
@@ -4,8 +4,8 @@ Used for network, booting, and most other issues debugging.
## How to get them
-First, connect your Kasli/SoC to the PC with a data micro-USB cable. Once you turn on the device, wait at least 15 seconds
-until its fully loaded.
+First, connect your Kasli/SoC to the PC with a data micro-USB cable. Once you turn on the device,
+wait at least 15 seconds until its fully loaded.
### Development shell
@@ -30,7 +30,7 @@ manipulations, as shown below.
#### Drivers
Use following instructions to set correct drivers for the COM ports.
-At choosing FTDI drivers stage you may have longer list of drivers.
+At choosing FTDI drivers stage you may have longer list of drivers.
In that case, choose respective `USB Serial Converter X` (A for 0, B for 1, C for 2, D for 3) driver. In case you cannot
locate the devices, they may appear in the _Other devices_ section:
@@ -44,9 +44,9 @@ You may also need to reboot your PC after doing this.
6. 
7. 
-If you are here after [flashing firmware](flashing_firmware.md) stage, you may fail to see the devices in the described locations.
-If you see them in the `Universal Serial Bus devices` section, you may need just to uninstall the third _Quad_ device and reconnect the
-Kasli/Kasli-SoC to the PC.
+If you are here after [flashing firmware](flashing_firmware.md) stage, you may fail to see the devices in the described
+locations. If you see them in the `Universal Serial Bus devices` section, you may need just to uninstall
+the third _Quad_ device and reconnect the Kasli/Kasli-SoC to the PC.
#### Connecting with PuTTY
@@ -56,4 +56,4 @@ Kasli/Kasli-SoC to the PC.
3. Connect to every COM port you find on connecting the device (usually connecting the the third port is enough)
4. Restart the device with `artiq_flash start`, or by power-cycling it (wait 30 seconds before turning on)
-5. See which COM port produces meaningful output and close others :)
\ No newline at end of file
+5. See which COM port produces meaningful output and close others :)