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Add synchronisation description to urukul (#4) 

Signed-off-by: Egor Savkin <es@m-labs.hk>
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Egor Savkin 2023-07-13 11:59:33 +08:00
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src/hw/urukul.md
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@ -12,6 +12,7 @@
"dds": "<variant>", // ad9910/ad9912 "dds": "<variant>", // ad9910/ad9912
"ports": [<port num>, <port num>], // second port is optional "ports": [<port num>, <port num>], // second port is optional
"clk_sel": <clock num>, "clk_sel": <clock num>,
"synchronization": true/false, // for AD9910 only
"refclk": <freq>, // for external clock signal "refclk": <freq>, // for external clock signal
"pll_en": <0 or 1, default 1> // PLL bypass, to allow higher external clocker frequencies (1e9 for example) "pll_en": <0 or 1, default 1> // PLL bypass, to allow higher external clocker frequencies (1e9 for example)
} }
@ -21,6 +22,16 @@
Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clocker source. Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clocker source.
### Synchronization
Synchronization option in the JSON refers to the phase synchronization between the outputs, and can be used only on AD9910 variants and
only with 125 MHz clock source provided from Kasli/Kasli-SoC (may be relayed through the Clocker board).
The phase sync works only within one Urukul board, though the phase shift between Urukuls may be [predictable](https://github.com/m-labs/artiq/issues/1692#issuecomment-994439589).
Even though it is widely-desirable feature, there are drawbacks of this preventing from enabling by default:
1. The resulting signal is more noisy, which can be observed [previously](https://github.com/sinara-hw/Urukul/issues/64).
2. Phase sync process takes time and sometimes fails
3. ???
## Testing ## Testing
After running `artiq_sinara_test`: After running `artiq_sinara_test`: