diff --git a/src/hw/mirny_almazny.md b/src/hw/mirny_almazny.md
index ba86467..bb66dba 100644
--- a/src/hw/mirny_almazny.md
+++ b/src/hw/mirny_almazny.md
@@ -18,7 +18,7 @@
 
 ## Getting the firmware
 
-On Hydra you can find [Mirny 0.3.1 firmware](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-release). It contains a single ``.jed`` file that can be flashed following [flashing instructions](#flashing). This firmware supports Almazny v1.2+.
+On Hydra you can find [Mirny 0.3.1 firmware](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-release). It contains a single `.jed` file that can be flashed following [flashing instructions](#flashing). This firmware supports Almazny v1.2+.
 
 If you are using a legacy Almazny (v1.0-1.1), due to different signals routed, you need to flash the older [0.2.4 firmware with Almazny support](https://nixbld.m-labs.hk/job/artiq/gluelogic/mirny-cpld-legacy-almazny).
 
@@ -29,10 +29,10 @@ However, if you need to make chances or build from source, follow these instruct
 Once you get your hands on the firmware source code, you will need to work around few shortcomings of Nix, mainly not being able to run dynamically linked executables.
 
 You will need:
-- Xilinx ISE 14.7 installed on your system (this guide is assuming ``/opt/Xilinx`` path),
+- Xilinx ISE 14.7 installed on your system (this guide is assuming `/opt/Xilinx` path),
 - an environment with Migen.
 
-One way to do it is to create an FHS environment, like ARTIQ does for Vivado, within ARTIQ's ``flake.nix`` (to leverage Migen already being there), by adding these lines:
+One way to do it is to create an FHS environment, like ARTIQ does for Vivado, within ARTIQ's `flake.nix` (to leverage Migen already being there), by adding these lines:
 
 ```
 iseEnv = pkgs.buildFHSEnv {
@@ -48,7 +48,7 @@ ise = pkgs.buildFHSEnv {
 };
 ```
 
-Add them below ``vivadoEnv``. Then add ``iseEnv`` and ``ise`` to the dev shell's build inputs. Call ``nix develop`` on that.
+Add them below `vivadoEnv`. Then add `iseEnv` and `ise` to the dev shell's build inputs. Call `nix develop` on that.
 
 Then you can build Mirny:
 
@@ -62,7 +62,7 @@ python mirny_impl.py
 
 ### Flashing
 
-For flashing, you will need Xilinx ISE 14.7 installed on your system (here assuming ``/opt/Xilinx`` path), and ``xc3sprog`` with the appropriate HS2 JTAG adapter.
+For flashing, you will need Xilinx ISE 14.7 installed on your system (here assuming `/opt/Xilinx` path), and `xc3sprog` with the appropriate HS2 JTAG adapter.
 
 ```shell
 nix-shell -p xc3sprog
diff --git a/src/hw/shuttler.md b/src/hw/shuttler.md
index 9d377cc..864c1cf 100644
--- a/src/hw/shuttler.md
+++ b/src/hw/shuttler.md
@@ -63,11 +63,11 @@ When Kasli Satellite is compiled with Shuttler, Shuttler is connected to the Sat
 Here provides an example to configure the routing table.
 You have 1 Kasli Master and 1 Kasli Satellite. Kasli Master (SFP1)(DEST1) port is connected to Kasli Satellite(SFP0)(DEST0). Shuttler is connected to Kasli Satellite with DRTIO over EEM Cable(DEST4).
 
-1. Initialize the Routing Table: ``` artiq_route rt.bin init```
-2. Add the routing table entry for Kasli Master's Peripherals: ```artiq_route rt.bin set 0 0```
-3. Add the routing table entry for Kasli Satellite's Peripherals: ```artiq_route rt.bin set 1 1 0```
-4. Add the routing table entry for Shuttler: ```artiq_route rt.bin set 4 1 4 0```
-5. Flash the routing table on Kasli Master: ```artiq_coremgmt config write -f routing_table rt.bin```
+1. Initialize the Routing Table: `artiq_route rt.bin init`
+2. Add the routing table entry for Kasli Master's Peripherals: `artiq_route rt.bin set 0 0`
+3. Add the routing table entry for Kasli Satellite's Peripherals: `artiq_route rt.bin set 1 1 0`
+4. Add the routing table entry for Shuttler: `artiq_route rt.bin set 4 1 4 0`
+5. Flash the routing table on Kasli Master: `artiq_coremgmt config write -f routing_table rt.bin`
 
 ## Flashing
 
diff --git a/src/hw/urukul.md b/src/hw/urukul.md
index 8eae605..df25623 100644
--- a/src/hw/urukul.md
+++ b/src/hw/urukul.md
@@ -154,7 +154,7 @@ Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up r
 ### Jagged signal with 1GHz external clock on AD9910
 
 By default, on AD9910 external clock signal is divided by 4, while it should be not divided at all with PLL disabled.
-Change the ``clk_div`` parameter to the CPLD in the device_db file:
+Change the `clk_div` parameter to the CPLD in the device_db file:
 
 ```python
 device_db["urukulX_cpld"] = {