EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 8
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 7450 1050 600  1200
U 60FB17F2
F0 "HighSpeedADC" 50
F1 "HighSpeedADC.sch" 50
F2 "ADC_CLK" I L 7450 1300 50 
F3 "ADC_DATA1" I L 7450 1450 50 
F4 "ADC_DATA2" I L 7450 1550 50 
F5 "ADC_DATA3" I L 7450 1650 50 
F6 "ADC_DATA4" I L 7450 1750 50 
F7 "ADC_DATA5" I L 7450 1850 50 
F8 "ADC_DATA6" I L 7450 1950 50 
F9 "ADC_DATA7" I L 7450 2050 50 
F10 "ADC_DATA8" I L 7450 2150 50 
F11 "ADC_IN" I L 7450 1150 50 
$EndSheet
$Sheet
S 4650 900  1500 5450
U 60C0E996
F0 "FPGA" 50
F1 "FPGA.sch" 50
F2 "FPGA_VPP_FAST" I L 4650 4600 50 
F3 "FPGA_EEM0_0_P" I R 6150 950 50 
F4 "FPGA_EEM0_0_N" I R 6150 1050 50 
F5 "FPGA_EEM0_7_P" I R 6150 2350 50 
F6 "FPGA_EEM0_7_N" I R 6150 2450 50 
F7 "FPGA_EEM0_6_P" I R 6150 2150 50 
F8 "FPGA_EEM0_6_N" I R 6150 2250 50 
F9 "FPGA_EEM0_5_P" I R 6150 1950 50 
F10 "FPGA_EEM0_5_N" I R 6150 2050 50 
F11 "FPGA_EEM0_4_P" I R 6150 1750 50 
F12 "FPGA_EEM0_4_N" I R 6150 1850 50 
F13 "FPGA_EEM0_3_P" I R 6150 1550 50 
F14 "FPGA_EEM0_3_N" I R 6150 1650 50 
F15 "FPGA_EEM0_2_P" I R 6150 1350 50 
F16 "FPGA_EEM0_2_N" I R 6150 1450 50 
F17 "FPGA_EEM0_1_P" I R 6150 1150 50 
F18 "FPGA_EEM0_1_N" I R 6150 1250 50 
F19 "FPGA_EEM1_0_P" I R 6150 2750 50 
F20 "FPGA_EEM1_0_N" I R 6150 2850 50 
F21 "FPGA_EEM1_7_P" I R 6150 4150 50 
F22 "FPGA_EEM1_7_N" I R 6150 4250 50 
F23 "FPGA_EEM1_6_P" I R 6150 3950 50 
F24 "FPGA_EEM1_6_N" I R 6150 4050 50 
F25 "FPGA_EEM1_5_P" I R 6150 3750 50 
F26 "FPGA_EEM1_5_N" I R 6150 3850 50 
F27 "FPGA_EEM1_4_P" I R 6150 3550 50 
F28 "FPGA_EEM1_4_N" I R 6150 3650 50 
F29 "FPGA_EEM1_3_P" I R 6150 3350 50 
F30 "FPGA_EEM1_3_N" I R 6150 3450 50 
F31 "FPGA_EEM1_2_P" I R 6150 3150 50 
F32 "FPGA_EEM1_2_N" I R 6150 3250 50 
F33 "FPGA_EEM1_1_P" I R 6150 2950 50 
F34 "FPGA_EEM1_1_N" I R 6150 3050 50 
F35 "FPGA_EEM2_0_P" I R 6150 4550 50 
F36 "FPGA_EEM2_0_N" I R 6150 4650 50 
F37 "FPGA_EEM2_7_P" I R 6150 5950 50 
F38 "FPGA_EEM2_7_N" I R 6150 6050 50 
F39 "FPGA_EEM2_6_P" I R 6150 5750 50 
F40 "FPGA_EEM2_6_N" I R 6150 5850 50 
F41 "FPGA_EEM2_5_P" I R 6150 5550 50 
F42 "FPGA_EEM2_5_N" I R 6150 5650 50 
F43 "FPGA_EEM2_4_P" I R 6150 5350 50 
F44 "FPGA_EEM2_4_N" I R 6150 5450 50 
F45 "FPGA_EEM2_3_P" I R 6150 5150 50 
F46 "FPGA_EEM2_3_N" I R 6150 5250 50 
F47 "FPGA_EEM2_2_P" I R 6150 4950 50 
F48 "FPGA_EEM2_2_N" I R 6150 5050 50 
F49 "FPGA_EEM2_1_P" I R 6150 4750 50 
F50 "FPGA_EEM2_1_N" I R 6150 4850 50 
F51 "FPGA_IIC0_SDA" I R 6150 2650 50 
F52 "FPGA_IIC0_SCL" I R 6150 2550 50 
F53 "FPGA_IIC1_SDA" I R 6150 4450 50 
F54 "FPGA_IIC1_SCL" I R 6150 4350 50 
F55 "FPGA_IIC2_SDA" I R 6150 6250 50 
F56 "FPGA_IIC2_SCL" I R 6150 6150 50 
F57 "FPGA_FSMC_A0" I L 4650 950 50 
F58 "FPGA_FSMC_A1" I L 4650 1050 50 
F59 "FPGA_FSMC_A2" I L 4650 1150 50 
F60 "FPGA_FSMC_A3" I L 4650 1250 50 
F61 "FPGA_FSMC_A4" I L 4650 1350 50 
F62 "FPGA_FSMC_A5" I L 4650 1450 50 
F63 "FPGA_FSMC_A6" I L 4650 1550 50 
F64 "FPGA_FSMC_A7" I L 4650 1650 50 
F65 "FPGA_FSMC_D0" I L 4650 1750 50 
F66 "FPGA_FSMC_D1" I L 4650 1850 50 
F67 "FPGA_FSMC_D2" I L 4650 1950 50 
F68 "FPGA_FSMC_D3" I L 4650 2050 50 
F69 "FPGA_FSMC_D4" I L 4650 2150 50 
F70 "FPGA_FSMC_D5" I L 4650 2250 50 
F71 "FPGA_FSMC_D6" I L 4650 2350 50 
F72 "FPGA_FSMC_D7" I L 4650 2450 50 
F73 "FPGA_FSMC_D8" I L 4650 2550 50 
F74 "FPGA_FSMC_D9" I L 4650 2650 50 
F75 "FPGA_FSMC_D10" I L 4650 2750 50 
F76 "FPGA_FSMC_D11" I L 4650 2850 50 
F77 "FPGA_FSMC_D12" I L 4650 2950 50 
F78 "FPGA_FSMC_D13" I L 4650 3050 50 
F79 "FPGA_FSMC_D14" I L 4650 3150 50 
F80 "FPGA_FSMC_D15" I L 4650 3250 50 
F81 "FPGA_CSBSEL0" I L 4650 3600 50 
F82 "FPGA_CSBSEL1" I L 4650 3700 50 
F83 "FPGA_SPI_SDO" I L 4650 3800 50 
F84 "FPGA_SPI_SDI" I L 4650 3900 50 
F85 "FPGA_SPI_SS" I L 4650 4000 50 
F86 "FPGA_SPI_SCK" I L 4650 4100 50 
F87 "FPGA_CDONE" I L 4650 4200 50 
F88 "FPGA_CRESET" I L 4650 4300 50 
F89 "FPGA_IIC3_SDA" I L 4650 5050 50 
F90 "FPGA_IIC3_SCL" I L 4650 4950 50 
$EndSheet
$Sheet
S 2900 5300 650  1000
U 60E4702B
F0 "Ethernet" 50
F1 "Ethernet.sch" 50
F2 "POE_VC+" I L 2900 6200 50 
F3 "POE_VC-" I L 2900 6100 50 
F4 "ENC_SPI_SCK" I L 2900 5900 50 
F5 "ENC_SPI_MOSI" I L 2900 5800 50 
F6 "ENC_SPI_MISO" I L 2900 5700 50 
F7 "ENC_INT" I L 2900 5400 50 
F8 "ENC_SPI_CS" I L 2900 5600 50 
$EndSheet
$Sheet
S 1650 5350 750  800 
U 60C2FE2A
F0 "Power" 50
F1 "Power.sch" 50
F2 "POE_VC+" I R 2400 5600 50 
F3 "POE_VC-" I R 2400 5500 50 
F4 "POE_AT_EVENT" I L 1650 5800 50 
F5 "POE_SRC_Status" I L 1650 5900 50 
F6 "POE_CPU_RESET" I L 1650 6000 50 
$EndSheet
$Sheet
S 1650 6600 650  500 
U 60E3407A
F0 "CurrentSenser" 50
F1 "CurrentSenser.sch" 50
F2 "12V_OUT" I L 1650 6700 50 
F3 "12V_SW" I L 1650 6850 50 
F4 "12V_CURRENT" I L 1650 7000 50 
$EndSheet
$Sheet
S 7500 3050 750  1150
U 60CB9D41
F0 "Connectors" 50
F1 "Connectors.sch" 50
$EndSheet
Wire Wire Line
	2400 5500 2550 5500
Wire Wire Line
	2550 5500 2550 6100
Wire Wire Line
	2550 6100 2900 6100
Wire Wire Line
	2400 5600 2500 5600
Wire Wire Line
	2500 5600 2500 6200
Wire Wire Line
	2500 6200 2900 6200
NoConn ~ 1750 1000
NoConn ~ 1750 1100
NoConn ~ 1750 1300
NoConn ~ 1750 1400
NoConn ~ 1750 1500
NoConn ~ 1750 1600
NoConn ~ 1750 1700
NoConn ~ 1750 1800
NoConn ~ 1750 1900
NoConn ~ 1750 2000
NoConn ~ 1750 2450
NoConn ~ 1750 2550
NoConn ~ 1750 3250
NoConn ~ 1750 3350
NoConn ~ 1750 3450
NoConn ~ 1750 3550
NoConn ~ 1750 3800
NoConn ~ 1750 3900
NoConn ~ 1750 4050
NoConn ~ 1750 4150
NoConn ~ 1750 4400
NoConn ~ 1750 4500
NoConn ~ 1750 4600
NoConn ~ 1750 4700
$Sheet
S 1750 900  1500 3950
U 60C2FDBB
F0 "MCU" 50
F1 "MCU.sch" 50
F2 "CPU_DAC0" I L 1750 1000 50 
F3 "CPU_DAC1" I L 1750 1100 50 
F4 "CPU_ADC1" I L 1750 1400 50 
F5 "CPU_ADC2" I L 1750 1500 50 
F6 "CPU_ADC3" I L 1750 1600 50 
F7 "CPU_ADC4" I L 1750 1700 50 
F8 "CPU_ADC0" I L 1750 1300 50 
F9 "CPU_ADC5" I L 1750 1800 50 
F10 "CPU_ADC6" I L 1750 1900 50 
F11 "CPU_ADC7" I L 1750 2000 50 
F12 "CPU_IIC2_SCL" I L 1750 2450 50 
F13 "CPU_IIC2_SDA" I L 1750 2550 50 
F14 "CPU_SPI2_SCK" I L 1750 3250 50 
F15 "CPU_SPI2_MISO" I L 1750 3350 50 
F16 "CPU_SPI2_MOSI" I L 1750 3450 50 
F17 "CPU_SWDIO" I R 3250 4450 50 
F18 "CPU_SWCLK" I R 3250 4550 50 
F19 "CPU_UART1_TX" I L 1750 3800 50 
F20 "CPU_UART1_RX" I L 1750 3900 50 
F21 "CPU_UART4_TX" I L 1750 4050 50 
F22 "CPU_UART4_RX" I L 1750 4150 50 
F23 "CPU_IIC1_SCL" I L 1750 2200 50 
F24 "CPU_IIC1_SDA" I L 1750 2300 50 
F25 "CPU_SPI1_SCK" I L 1750 2750 50 
F26 "CPU_SPI1_MISO" I L 1750 2850 50 
F27 "CPU_SPI1_MOSI" I L 1750 2950 50 
F28 "CPU_SPI2_CS" I L 1750 3550 50 
F29 "CPU_SPI1_CS" I L 1750 3050 50 
F30 "CPU_FSMC_DA0" I R 3250 1000 50 
F31 "CPU_FSMC_DA1" I R 3250 1100 50 
F32 "CPU_FSMC_DA2" I R 3250 1200 50 
F33 "CPU_FSMC_DA3" I R 3250 1300 50 
F34 "CPU_FSMC_DA4" I R 3250 1400 50 
F35 "CPU_FSMC_DA5" I R 3250 1500 50 
F36 "CPU_FSMC_DA6" I R 3250 1600 50 
F37 "CPU_FSMC_DA7" I R 3250 1700 50 
F38 "CPU_FSMC_DA8" I R 3250 1800 50 
F39 "CPU_FSMC_DA9" I R 3250 1900 50 
F40 "CPU_FSMC_DA10" I R 3250 2000 50 
F41 "CPU_FSMC_DA11" I R 3250 2100 50 
F42 "CPU_FSMC_DA12" I R 3250 2200 50 
F43 "CPU_FSMC_D13" I R 3250 2300 50 
F44 "CPU_FSMC_D14" I R 3250 2400 50 
F45 "CPU_FSMC_D15" I R 3250 2500 50 
F46 "CPU_FSMC_A16" I R 3250 2600 50 
F47 "CPU_FSMC_A17" I R 3250 2700 50 
F48 "CPU_FSMC_A18" I R 3250 2800 50 
F49 "CPU_FSMC_A19" I R 3250 2900 50 
F50 "CPU_FSMC_A20" I R 3250 3000 50 
F51 "CPU_FSMC_A21" I R 3250 3100 50 
F52 "CPU_FSMC_A22" I R 3250 3200 50 
F53 "CPU_FSMC_A23" I R 3250 3300 50 
F54 "CPU_FSMC_NWE" I R 3250 3450 50 
F55 "CPU_FSMC_NOE" I R 3250 3550 50 
F56 "CPU_FSMC_NE1" I R 3250 3650 50 
F57 "CPU_PWM_CH1" I L 1750 4400 50 
F58 "CPU_PWM_CH2" I L 1750 4500 50 
F59 "CPU_PWM_CH3" I L 1750 4600 50 
F60 "CPU_PWM_CH4" I L 1750 4700 50 
F61 "CPU_FSMC_NBL0" I R 3250 3750 50 
F62 "CPU_FSMC_NBL1" I R 3250 3850 50 
F63 "CPU_FSMC_NL" I R 3250 3950 50 
F64 "CPU_FSMC_CLK" I R 3250 4050 50 
F65 "CPU_FSMC_NWAIT" I R 3250 4150 50 
F66 "CPU_ENC_CS" I L 1750 3150 50 
F67 "CPU_ADC8" I L 1750 1200 50 
$EndSheet
NoConn ~ 3250 4450
NoConn ~ 3250 4550
$EndSCHEMATC