EESchema Schematic File Version 4
EELAYER 30 0
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$Descr A4 11693 8268
encoding utf-8
Sheet 1 6
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 5550 1100 2050 2550
U 60C0E996
F0 "FPGA" 50
F1 "FPGA.sch" 50
F2 "FPGA_VCC" I R 7600 1300 50 
F3 "FPGA_GND" I R 7600 1600 50 
$EndSheet
$Sheet
S 2150 5000 2050 2150
U 60C2FE2A
F0 "Power" 50
F1 "Power.sch" 50
$EndSheet
$Sheet
S 5600 5000 2000 1450
U 60FB17F2
F0 "Analog_LVDS" 50
F1 "Analog_LVDS.sch" 50
$EndSheet
$Sheet
S 2150 1100 1950 2550
U 60C2FDBB
F0 "MCU" 50
F1 "MCU.sch" 50
F2 "CPU_DAC0" I L 2150 1250 50 
F3 "CPU_DAC1" I L 2150 1350 50 
F4 "CPU_ADC1" I L 2150 1600 50 
F5 "CPU_ADC2" I L 2150 1700 50 
F6 "CPU_ADC3" I L 2150 1800 50 
F7 "CPU_ADC4" I L 2150 1900 50 
F8 "CPU_ADC0" I L 2150 1500 50 
F9 "CPU_ADC5" I L 2150 2000 50 
F10 "CPU_ADC6" I L 2150 2100 50 
F11 "CPU_ADC7" I L 2150 2200 50 
$EndSheet
$Sheet
S 9150 2050 1200 1400
U 60E4702B
F0 "Ethernet" 50
F1 "Ethernet.sch" 50
$EndSheet
$EndSCHEMATC