EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 6
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 5550 1100 2050 2550
U 60C0E996
F0 "FPGA" 50
F1 "FPGA.sch" 50
F2 "FPGA_VCC" I R 7600 1300 50 
F3 "FPGA_GND" I R 7600 1600 50 
$EndSheet
$Sheet
S 2150 5000 2050 2150
U 60C2FE2A
F0 "Power" 50
F1 "Power.sch" 50
$EndSheet
$Sheet
S 5600 5000 2000 1450
U 60FB17F2
F0 "Analog_LVDS" 50
F1 "Analog_LVDS.sch" 50
F2 "ADC_DATA_BUS" I L 5600 5150 50 
F3 "ADC_IN" I L 5600 5550 50 
F4 "ADC_CLK" I L 5600 5250 50 
$EndSheet
$Sheet
S 2150 1100 1950 2550
U 60C2FDBB
F0 "MCU" 50
F1 "MCU.sch" 50
F2 "CPU_DAC0" I L 2150 1250 50 
F3 "CPU_DAC1" I L 2150 1350 50 
F4 "CPU_ADC1" I L 2150 1600 50 
F5 "CPU_ADC2" I L 2150 1700 50 
F6 "CPU_ADC3" I L 2150 1800 50 
F7 "CPU_ADC4" I L 2150 1900 50 
F8 "CPU_ADC0" I L 2150 1500 50 
F9 "CPU_ADC5" I L 2150 2000 50 
F10 "CPU_ADC6" I L 2150 2100 50 
F11 "CPU_ADC7" I L 2150 2200 50 
$EndSheet
$Sheet
S 9150 2050 1200 1400
U 60E4702B
F0 "Ethernet" 50
F1 "Ethernet.sch" 50
F2 "POE_VC+" I L 9150 3300 50 
F3 "POE_VC-" I L 9150 3150 50 
F4 "ENC_SPI_SCK" I L 9150 2750 50 
F5 "ENC_SPI_MOSI" I L 9150 2650 50 
F6 "ENC_SPI_MISO" I L 9150 2550 50 
F7 "ENC_INT" I L 9150 2350 50 
F8 "ENC_SPI_CS" I L 9150 2450 50 
$EndSheet
Wire Bus Line
	5600 5150 5450 5150
Entry Wire Line
	5350 4450 5450 4550
Entry Wire Line
	5350 4550 5450 4650
Entry Wire Line
	5350 4650 5450 4750
Entry Wire Line
	5350 4750 5450 4850
Entry Wire Line
	5350 4850 5450 4950
Entry Wire Line
	5350 4950 5450 5050
Entry Wire Line
	5350 5050 5450 5150
Entry Wire Line
	5350 4350 5450 4450
Wire Bus Line
	5450 4400 5450 5150
$EndSCHEMATC