From fc8c667020599bdd2e144a0f0e530dc1ea3749ad Mon Sep 17 00:00:00 2001 From: Jack-Zheng Date: Wed, 16 Jun 2021 17:20:32 +0800 Subject: [PATCH] Power: fix hierarchical and global label --- Power.sch | 26 ++--- Power.sch-bak | 26 ++--- TestAutomation.sch | 251 +++++++++++++++++++++-------------------- TestAutomation.sch-bak | 238 +++++++++++++++++++------------------- 4 files changed, 273 insertions(+), 268 deletions(-) diff --git a/Power.sch b/Power.sch index 174e3b5..f01cd3f 100644 --- a/Power.sch +++ b/Power.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 3 6 +Sheet 2 6 Title "" Date "" Rev "" @@ -537,14 +537,6 @@ Wire Wire Line 1700 1800 1700 1950 Wire Wire Line 1700 1950 1850 1950 -Text GLabel 2750 2950 0 50 Input ~ 0 -POE_VC- -Text GLabel 2800 1400 0 50 Input ~ 0 -POE_VC+ -Text Label 950 2700 0 50 ~ 0 -CPU_RESET -Wire Wire Line - 1400 2700 950 2700 Wire Wire Line 2750 2950 3000 2950 Connection ~ 3000 2950 @@ -619,8 +611,6 @@ Wire Wire Line 4000 3700 3500 3700 Wire Wire Line 3500 3700 3500 3800 -Text GLabel 2750 3300 0 50 Input ~ 0 -AT_EVENT Wire Wire Line 2750 3300 3100 3300 Wire Wire Line @@ -752,8 +742,6 @@ Wire Wire Line Wire Wire Line 7650 3850 8400 3850 Connection ~ 8400 3850 -Text GLabel 7450 3350 0 50 Input ~ 0 -POE_SRC_Status Wire Wire Line 7450 3350 7650 3350 Connection ~ 7650 3350 @@ -1657,4 +1645,16 @@ Wire Wire Line Wire Wire Line 5150 1200 5150 1100 Connection ~ 5150 1100 +Text HLabel 2800 1400 0 50 Input ~ 0 +POE_VC+ +Text HLabel 2750 2950 0 50 Input ~ 0 +POE_VC- +Text HLabel 2750 3300 0 50 Input ~ 0 +POE_AT_EVENT +Text HLabel 7450 3350 0 50 Input ~ 0 +POE_SRC_Status +Text HLabel 1300 2700 0 50 Input ~ 0 +POE_CPU_RESET +Wire Wire Line + 1400 2700 1300 2700 $EndSCHEMATC diff --git a/Power.sch-bak b/Power.sch-bak index 174e3b5..f01cd3f 100644 --- a/Power.sch-bak +++ b/Power.sch-bak @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 3 6 +Sheet 2 6 Title "" Date "" Rev "" @@ -537,14 +537,6 @@ Wire Wire Line 1700 1800 1700 1950 Wire Wire Line 1700 1950 1850 1950 -Text GLabel 2750 2950 0 50 Input ~ 0 -POE_VC- -Text GLabel 2800 1400 0 50 Input ~ 0 -POE_VC+ -Text Label 950 2700 0 50 ~ 0 -CPU_RESET -Wire Wire Line - 1400 2700 950 2700 Wire Wire Line 2750 2950 3000 2950 Connection ~ 3000 2950 @@ -619,8 +611,6 @@ Wire Wire Line 4000 3700 3500 3700 Wire Wire Line 3500 3700 3500 3800 -Text GLabel 2750 3300 0 50 Input ~ 0 -AT_EVENT Wire Wire Line 2750 3300 3100 3300 Wire Wire Line @@ -752,8 +742,6 @@ Wire Wire Line Wire Wire Line 7650 3850 8400 3850 Connection ~ 8400 3850 -Text GLabel 7450 3350 0 50 Input ~ 0 -POE_SRC_Status Wire Wire Line 7450 3350 7650 3350 Connection ~ 7650 3350 @@ -1657,4 +1645,16 @@ Wire Wire Line Wire Wire Line 5150 1200 5150 1100 Connection ~ 5150 1100 +Text HLabel 2800 1400 0 50 Input ~ 0 +POE_VC+ +Text HLabel 2750 2950 0 50 Input ~ 0 +POE_VC- +Text HLabel 2750 3300 0 50 Input ~ 0 +POE_AT_EVENT +Text HLabel 7450 3350 0 50 Input ~ 0 +POE_SRC_Status +Text HLabel 1300 2700 0 50 Input ~ 0 +POE_CPU_RESET +Wire Wire Line + 1400 2700 1300 2700 $EndSCHEMATC diff --git a/TestAutomation.sch b/TestAutomation.sch index 0ac7dd2..437c9cf 100644 --- a/TestAutomation.sch +++ b/TestAutomation.sch @@ -14,26 +14,113 @@ Comment3 "" Comment4 "" $EndDescr $Sheet -S 8300 3850 2050 2150 -U 60C2FE2A -F0 "Power" 50 -F1 "Power.sch" 50 +S 7500 950 600 1200 +U 60FB17F2 +F0 "High_Speed_ADC" 50 +F1 "High_Speed_ADC.sch" 50 +F2 "ADC_IN" I L 7500 1050 50 +F3 "ADC_CLK" I L 7500 1200 50 +F4 "ADC_DATA1" I L 7500 1350 50 +F5 "ADC_DATA2" I L 7500 1450 50 +F6 "ADC_DATA3" I L 7500 1550 50 +F7 "ADC_DATA4" I L 7500 1650 50 +F8 "ADC_DATA5" I L 7500 1750 50 +F9 "ADC_DATA6" I L 7500 1850 50 +F10 "ADC_DATA7" I L 7500 1950 50 +F11 "ADC_DATA8" I L 7500 2050 50 $EndSheet $Sheet -S 1000 1000 1950 2550 -U 60C2FDBB -F0 "MCU" 50 -F1 "MCU.sch" 50 -F2 "CPU_DAC0" I L 1000 1150 50 -F3 "CPU_DAC1" I L 1000 1250 50 -F4 "CPU_ADC1" I L 1000 1500 50 -F5 "CPU_ADC2" I L 1000 1600 50 -F6 "CPU_ADC3" I L 1000 1700 50 -F7 "CPU_ADC4" I L 1000 1800 50 -F8 "CPU_ADC0" I L 1000 1400 50 -F9 "CPU_ADC5" I L 1000 1900 50 -F10 "CPU_ADC6" I L 1000 2000 50 -F11 "CPU_ADC7" I L 1000 2100 50 +S 4650 900 1500 5450 +U 60C0E996 +F0 "FPGA" 50 +F1 "FPGA.sch" 50 +F2 "FPGA_VPP_FAST" I L 4650 4600 50 +F3 "FPGA_EEM0_0_P" I R 6150 950 50 +F4 "FPGA_EEM0_0_N" I R 6150 1050 50 +F5 "FPGA_EEM0_7_P" I R 6150 2350 50 +F6 "FPGA_EEM0_7_N" I R 6150 2450 50 +F7 "FPGA_EEM0_6_P" I R 6150 2150 50 +F8 "FPGA_EEM0_6_N" I R 6150 2250 50 +F9 "FPGA_EEM0_5_P" I R 6150 1950 50 +F10 "FPGA_EEM0_5_N" I R 6150 2050 50 +F11 "FPGA_EEM0_4_P" I R 6150 1750 50 +F12 "FPGA_EEM0_4_N" I R 6150 1850 50 +F13 "FPGA_EEM0_3_P" I R 6150 1550 50 +F14 "FPGA_EEM0_3_N" I R 6150 1650 50 +F15 "FPGA_EEM0_2_P" I R 6150 1350 50 +F16 "FPGA_EEM0_2_N" I R 6150 1450 50 +F17 "FPGA_EEM0_1_P" I R 6150 1150 50 +F18 "FPGA_EEM0_1_N" I R 6150 1250 50 +F19 "FPGA_EEM1_0_P" I R 6150 2750 50 +F20 "FPGA_EEM1_0_N" I R 6150 2850 50 +F21 "FPGA_EEM1_7_P" I R 6150 4150 50 +F22 "FPGA_EEM1_7_N" I R 6150 4250 50 +F23 "FPGA_EEM1_6_P" I R 6150 3950 50 +F24 "FPGA_EEM1_6_N" I R 6150 4050 50 +F25 "FPGA_EEM1_5_P" I R 6150 3750 50 +F26 "FPGA_EEM1_5_N" I R 6150 3850 50 +F27 "FPGA_EEM1_4_P" I R 6150 3550 50 +F28 "FPGA_EEM1_4_N" I R 6150 3650 50 +F29 "FPGA_EEM1_3_P" I R 6150 3350 50 +F30 "FPGA_EEM1_3_N" I R 6150 3450 50 +F31 "FPGA_EEM1_2_P" I R 6150 3150 50 +F32 "FPGA_EEM1_2_N" I R 6150 3250 50 +F33 "FPGA_EEM1_1_P" I R 6150 2950 50 +F34 "FPGA_EEM1_1_N" I R 6150 3050 50 +F35 "FPGA_EEM2_0_P" I R 6150 4550 50 +F36 "FPGA_EEM2_0_N" I R 6150 4650 50 +F37 "FPGA_EEM2_7_P" I R 6150 5950 50 +F38 "FPGA_EEM2_7_N" I R 6150 6050 50 +F39 "FPGA_EEM2_6_P" I R 6150 5750 50 +F40 "FPGA_EEM2_6_N" I R 6150 5850 50 +F41 "FPGA_EEM2_5_P" I R 6150 5550 50 +F42 "FPGA_EEM2_5_N" I R 6150 5650 50 +F43 "FPGA_EEM2_4_P" I R 6150 5350 50 +F44 "FPGA_EEM2_4_N" I R 6150 5450 50 +F45 "FPGA_EEM2_3_P" I R 6150 5150 50 +F46 "FPGA_EEM2_3_N" I R 6150 5250 50 +F47 "FPGA_EEM2_2_P" I R 6150 4950 50 +F48 "FPGA_EEM2_2_N" I R 6150 5050 50 +F49 "FPGA_EEM2_1_P" I R 6150 4750 50 +F50 "FPGA_EEM2_1_N" I R 6150 4850 50 +F51 "FPGA_IIC0_SDA" I R 6150 2650 50 +F52 "FPGA_IIC0_SCL" I R 6150 2550 50 +F53 "FPGA_IIC1_SDA" I R 6150 4450 50 +F54 "FPGA_IIC1_SCL" I R 6150 4350 50 +F55 "FPGA_IIC2_SDA" I R 6150 6250 50 +F56 "FPGA_IIC2_SCL" I R 6150 6150 50 +F57 "FPGA_FSMC_A0" I L 4650 950 50 +F58 "FPGA_FSMC_A1" I L 4650 1050 50 +F59 "FPGA_FSMC_A2" I L 4650 1150 50 +F60 "FPGA_FSMC_A3" I L 4650 1250 50 +F61 "FPGA_FSMC_A4" I L 4650 1350 50 +F62 "FPGA_FSMC_A5" I L 4650 1450 50 +F63 "FPGA_FSMC_A6" I L 4650 1550 50 +F64 "FPGA_FSMC_A7" I L 4650 1650 50 +F65 "FPGA_FSMC_D0" I L 4650 1750 50 +F66 "FPGA_FSMC_D1" I L 4650 1850 50 +F67 "FPGA_FSMC_D2" I L 4650 1950 50 +F68 "FPGA_FSMC_D3" I L 4650 2050 50 +F69 "FPGA_FSMC_D4" I L 4650 2150 50 +F70 "FPGA_FSMC_D5" I L 4650 2250 50 +F71 "FPGA_FSMC_D6" I L 4650 2350 50 +F72 "FPGA_FSMC_D7" I L 4650 2450 50 +F73 "FPGA_FSMC_D8" I L 4650 2550 50 +F74 "FPGA_FSMC_D9" I L 4650 2650 50 +F75 "FPGA_FSMC_D10" I L 4650 2750 50 +F76 "FPGA_FSMC_D11" I L 4650 2850 50 +F77 "FPGA_FSMC_D12" I L 4650 2950 50 +F78 "FPGA_FSMC_D13" I L 4650 3050 50 +F79 "FPGA_FSMC_D14" I L 4650 3150 50 +F80 "FPGA_FSMC_D15" I L 4650 3250 50 +F81 "FPGA_CSBSEL0" I L 4650 3600 50 +F82 "FPGA_CSBSEL1" I L 4650 3700 50 +F83 "FPGA_SPI_SDO" I L 4650 3800 50 +F84 "FPGA_SPI_SDI" I L 4650 3900 50 +F85 "FPGA_SPI_SS" I L 4650 4000 50 +F86 "FPGA_SPI_SCK" I L 4650 4100 50 +F87 "FPGA_CDONE" I L 4650 4200 50 +F88 "FPGA_CRESET" I L 4650 4300 50 $EndSheet $Sheet S 2250 4300 650 1000 @@ -49,112 +136,30 @@ F7 "ENC_INT" I L 2250 4400 50 F8 "ENC_SPI_CS" I L 2250 4600 50 $EndSheet $Sheet -S 8250 950 600 1200 -U 60FB17F2 -F0 "High_Speed_ADC" 50 -F1 "High_Speed_ADC.sch" 50 -F2 "ADC_IN" I L 8250 1050 50 -F3 "ADC_CLK" I L 8250 1200 50 -F4 "ADC_DATA1" I L 8250 1350 50 -F5 "ADC_DATA2" I L 8250 1450 50 -F6 "ADC_DATA3" I L 8250 1550 50 -F7 "ADC_DATA4" I L 8250 1650 50 -F8 "ADC_DATA5" I L 8250 1750 50 -F9 "ADC_DATA6" I L 8250 1850 50 -F10 "ADC_DATA7" I L 8250 1950 50 -F11 "ADC_DATA8" I L 8250 2050 50 +S 2250 5750 750 800 +U 60C2FE2A +F0 "Power" 50 +F1 "Power.sch" 50 +F2 "POE_VC+" I L 2250 5900 50 +F3 "POE_VC-" I L 2250 6000 50 +F4 "POE_AT_EVENT" I L 2250 6200 50 +F5 "POE_SRC_Status" I L 2250 6300 50 +F6 "POE_CPU_RESET" I L 2250 6400 50 $EndSheet $Sheet -S 4450 800 1500 5450 -U 60C0E996 -F0 "FPGA" 50 -F1 "FPGA.sch" 50 -F2 "FPGA_VPP_FAST" I L 4450 4500 50 -F3 "FPGA_EEM0_0_P" I R 5950 850 50 -F4 "FPGA_EEM0_0_N" I R 5950 950 50 -F5 "FPGA_EEM0_7_P" I R 5950 2250 50 -F6 "FPGA_EEM0_7_N" I R 5950 2350 50 -F7 "FPGA_EEM0_6_P" I R 5950 2050 50 -F8 "FPGA_EEM0_6_N" I R 5950 2150 50 -F9 "FPGA_EEM0_5_P" I R 5950 1850 50 -F10 "FPGA_EEM0_5_N" I R 5950 1950 50 -F11 "FPGA_EEM0_4_P" I R 5950 1650 50 -F12 "FPGA_EEM0_4_N" I R 5950 1750 50 -F13 "FPGA_EEM0_3_P" I R 5950 1450 50 -F14 "FPGA_EEM0_3_N" I R 5950 1550 50 -F15 "FPGA_EEM0_2_P" I R 5950 1250 50 -F16 "FPGA_EEM0_2_N" I R 5950 1350 50 -F17 "FPGA_EEM0_1_P" I R 5950 1050 50 -F18 "FPGA_EEM0_1_N" I R 5950 1150 50 -F19 "FPGA_EEM1_0_P" I R 5950 2650 50 -F20 "FPGA_EEM1_0_N" I R 5950 2750 50 -F21 "FPGA_EEM1_7_P" I R 5950 4050 50 -F22 "FPGA_EEM1_7_N" I R 5950 4150 50 -F23 "FPGA_EEM1_6_P" I R 5950 3850 50 -F24 "FPGA_EEM1_6_N" I R 5950 3950 50 -F25 "FPGA_EEM1_5_P" I R 5950 3650 50 -F26 "FPGA_EEM1_5_N" I R 5950 3750 50 -F27 "FPGA_EEM1_4_P" I R 5950 3450 50 -F28 "FPGA_EEM1_4_N" I R 5950 3550 50 -F29 "FPGA_EEM1_3_P" I R 5950 3250 50 -F30 "FPGA_EEM1_3_N" I R 5950 3350 50 -F31 "FPGA_EEM1_2_P" I R 5950 3050 50 -F32 "FPGA_EEM1_2_N" I R 5950 3150 50 -F33 "FPGA_EEM1_1_P" I R 5950 2850 50 -F34 "FPGA_EEM1_1_N" I R 5950 2950 50 -F35 "FPGA_EEM2_0_P" I R 5950 4450 50 -F36 "FPGA_EEM2_0_N" I R 5950 4550 50 -F37 "FPGA_EEM2_7_P" I R 5950 5850 50 -F38 "FPGA_EEM2_7_N" I R 5950 5950 50 -F39 "FPGA_EEM2_6_P" I R 5950 5650 50 -F40 "FPGA_EEM2_6_N" I R 5950 5750 50 -F41 "FPGA_EEM2_5_P" I R 5950 5450 50 -F42 "FPGA_EEM2_5_N" I R 5950 5550 50 -F43 "FPGA_EEM2_4_P" I R 5950 5250 50 -F44 "FPGA_EEM2_4_N" I R 5950 5350 50 -F45 "FPGA_EEM2_3_P" I R 5950 5050 50 -F46 "FPGA_EEM2_3_N" I R 5950 5150 50 -F47 "FPGA_EEM2_2_P" I R 5950 4850 50 -F48 "FPGA_EEM2_2_N" I R 5950 4950 50 -F49 "FPGA_EEM2_1_P" I R 5950 4650 50 -F50 "FPGA_EEM2_1_N" I R 5950 4750 50 -F51 "FPGA_IIC0_SDA" I R 5950 2550 50 -F52 "FPGA_IIC0_SCL" I R 5950 2450 50 -F53 "FPGA_IIC1_SDA" I R 5950 4350 50 -F54 "FPGA_IIC1_SCL" I R 5950 4250 50 -F55 "FPGA_IIC2_SDA" I R 5950 6150 50 -F56 "FPGA_IIC2_SCL" I R 5950 6050 50 -F57 "FPGA_FSMC_A0" I L 4450 850 50 -F58 "FPGA_FSMC_A1" I L 4450 950 50 -F59 "FPGA_FSMC_A2" I L 4450 1050 50 -F60 "FPGA_FSMC_A3" I L 4450 1150 50 -F61 "FPGA_FSMC_A4" I L 4450 1250 50 -F62 "FPGA_FSMC_A5" I L 4450 1350 50 -F63 "FPGA_FSMC_A6" I L 4450 1450 50 -F64 "FPGA_FSMC_A7" I L 4450 1550 50 -F65 "FPGA_FSMC_D0" I L 4450 1650 50 -F66 "FPGA_FSMC_D1" I L 4450 1750 50 -F67 "FPGA_FSMC_D2" I L 4450 1850 50 -F68 "FPGA_FSMC_D3" I L 4450 1950 50 -F69 "FPGA_FSMC_D4" I L 4450 2050 50 -F70 "FPGA_FSMC_D5" I L 4450 2150 50 -F71 "FPGA_FSMC_D6" I L 4450 2250 50 -F72 "FPGA_FSMC_D7" I L 4450 2350 50 -F73 "FPGA_FSMC_D8" I L 4450 2450 50 -F74 "FPGA_FSMC_D9" I L 4450 2550 50 -F75 "FPGA_FSMC_D10" I L 4450 2650 50 -F76 "FPGA_FSMC_D11" I L 4450 2750 50 -F77 "FPGA_FSMC_D12" I L 4450 2850 50 -F78 "FPGA_FSMC_D13" I L 4450 2950 50 -F79 "FPGA_FSMC_D14" I L 4450 3050 50 -F80 "FPGA_FSMC_D15" I L 4450 3150 50 -F81 "FPGA_CSBSEL0" I L 4450 3500 50 -F82 "FPGA_CSBSEL1" I L 4450 3600 50 -F83 "FPGA_SPI_SDO" I L 4450 3700 50 -F84 "FPGA_SPI_SDI" I L 4450 3800 50 -F85 "FPGA_SPI_SS" I L 4450 3900 50 -F86 "FPGA_SPI_SCK" I L 4450 4000 50 -F87 "FPGA_CDONE" I L 4450 4100 50 -F88 "FPGA_CRESET" I L 4450 4200 50 +S 1750 900 1950 2550 +U 60C2FDBB +F0 "MCU" 50 +F1 "MCU.sch" 50 +F2 "CPU_DAC0" I L 1750 1050 50 +F3 "CPU_DAC1" I L 1750 1150 50 +F4 "CPU_ADC1" I L 1750 1400 50 +F5 "CPU_ADC2" I L 1750 1500 50 +F6 "CPU_ADC3" I L 1750 1600 50 +F7 "CPU_ADC4" I L 1750 1700 50 +F8 "CPU_ADC0" I L 1750 1300 50 +F9 "CPU_ADC5" I L 1750 1800 50 +F10 "CPU_ADC6" I L 1750 1900 50 +F11 "CPU_ADC7" I L 1750 2000 50 $EndSheet $EndSCHEMATC diff --git a/TestAutomation.sch-bak b/TestAutomation.sch-bak index df25fde..0ac7dd2 100644 --- a/TestAutomation.sch-bak +++ b/TestAutomation.sch-bak @@ -14,147 +14,147 @@ Comment3 "" Comment4 "" $EndDescr $Sheet -S 2150 5000 2050 2150 +S 8300 3850 2050 2150 U 60C2FE2A F0 "Power" 50 F1 "Power.sch" 50 $EndSheet $Sheet -S 2150 1100 1950 2550 +S 1000 1000 1950 2550 U 60C2FDBB F0 "MCU" 50 F1 "MCU.sch" 50 -F2 "CPU_DAC0" I L 2150 1250 50 -F3 "CPU_DAC1" I L 2150 1350 50 -F4 "CPU_ADC1" I L 2150 1600 50 -F5 "CPU_ADC2" I L 2150 1700 50 -F6 "CPU_ADC3" I L 2150 1800 50 -F7 "CPU_ADC4" I L 2150 1900 50 -F8 "CPU_ADC0" I L 2150 1500 50 -F9 "CPU_ADC5" I L 2150 2000 50 -F10 "CPU_ADC6" I L 2150 2100 50 -F11 "CPU_ADC7" I L 2150 2200 50 +F2 "CPU_DAC0" I L 1000 1150 50 +F3 "CPU_DAC1" I L 1000 1250 50 +F4 "CPU_ADC1" I L 1000 1500 50 +F5 "CPU_ADC2" I L 1000 1600 50 +F6 "CPU_ADC3" I L 1000 1700 50 +F7 "CPU_ADC4" I L 1000 1800 50 +F8 "CPU_ADC0" I L 1000 1400 50 +F9 "CPU_ADC5" I L 1000 1900 50 +F10 "CPU_ADC6" I L 1000 2000 50 +F11 "CPU_ADC7" I L 1000 2100 50 $EndSheet $Sheet -S 9150 2050 1200 1400 +S 2250 4300 650 1000 U 60E4702B F0 "Ethernet" 50 F1 "Ethernet.sch" 50 -F2 "POE_VC+" I L 9150 3300 50 -F3 "POE_VC-" I L 9150 3150 50 -F4 "ENC_SPI_SCK" I L 9150 2750 50 -F5 "ENC_SPI_MOSI" I L 9150 2650 50 -F6 "ENC_SPI_MISO" I L 9150 2550 50 -F7 "ENC_INT" I L 9150 2350 50 -F8 "ENC_SPI_CS" I L 9150 2450 50 +F2 "POE_VC+" I L 2250 5200 50 +F3 "POE_VC-" I L 2250 5100 50 +F4 "ENC_SPI_SCK" I L 2250 4900 50 +F5 "ENC_SPI_MOSI" I L 2250 4800 50 +F6 "ENC_SPI_MISO" I L 2250 4700 50 +F7 "ENC_INT" I L 2250 4400 50 +F8 "ENC_SPI_CS" I L 2250 4600 50 $EndSheet $Sheet -S 9200 4250 600 1200 +S 8250 950 600 1200 U 60FB17F2 F0 "High_Speed_ADC" 50 F1 "High_Speed_ADC.sch" 50 -F2 "ADC_IN" I L 9200 4350 50 -F3 "ADC_CLK" I L 9200 4500 50 -F4 "ADC_DATA1" I L 9200 4650 50 -F5 "ADC_DATA2" I L 9200 4750 50 -F6 "ADC_DATA3" I L 9200 4850 50 -F7 "ADC_DATA4" I L 9200 4950 50 -F8 "ADC_DATA5" I L 9200 5050 50 -F9 "ADC_DATA6" I L 9200 5150 50 -F10 "ADC_DATA7" I L 9200 5250 50 -F11 "ADC_DATA8" I L 9200 5350 50 +F2 "ADC_IN" I L 8250 1050 50 +F3 "ADC_CLK" I L 8250 1200 50 +F4 "ADC_DATA1" I L 8250 1350 50 +F5 "ADC_DATA2" I L 8250 1450 50 +F6 "ADC_DATA3" I L 8250 1550 50 +F7 "ADC_DATA4" I L 8250 1650 50 +F8 "ADC_DATA5" I L 8250 1750 50 +F9 "ADC_DATA6" I L 8250 1850 50 +F10 "ADC_DATA7" I L 8250 1950 50 +F11 "ADC_DATA8" I L 8250 2050 50 $EndSheet $Sheet -S 5550 1100 1500 5450 +S 4450 800 1500 5450 U 60C0E996 F0 "FPGA" 50 F1 "FPGA.sch" 50 -F2 "FPGA_VPP_FAST" I L 5550 4800 50 -F3 "FPGA_EEM0_0_P" I R 7050 1150 50 -F4 "FPGA_EEM0_0_N" I R 7050 1250 50 -F5 "FPGA_EEM0_7_P" I R 7050 2550 50 -F6 "FPGA_EEM0_7_N" I R 7050 2650 50 -F7 "FPGA_EEM0_6_P" I R 7050 2350 50 -F8 "FPGA_EEM0_6_N" I R 7050 2450 50 -F9 "FPGA_EEM0_5_P" I R 7050 2150 50 -F10 "FPGA_EEM0_5_N" I R 7050 2250 50 -F11 "FPGA_EEM0_4_P" I R 7050 1950 50 -F12 "FPGA_EEM0_4_N" I R 7050 2050 50 -F13 "FPGA_EEM0_3_P" I R 7050 1750 50 -F14 "FPGA_EEM0_3_N" I R 7050 1850 50 -F15 "FPGA_EEM0_2_P" I R 7050 1550 50 -F16 "FPGA_EEM0_2_N" I R 7050 1650 50 -F17 "FPGA_EEM0_1_P" I R 7050 1350 50 -F18 "FPGA_EEM0_1_N" I R 7050 1450 50 -F19 "FPGA_EEM1_0_P" I R 7050 2950 50 -F20 "FPGA_EEM1_0_N" I R 7050 3050 50 -F21 "FPGA_EEM1_7_P" I R 7050 4350 50 -F22 "FPGA_EEM1_7_N" I R 7050 4450 50 -F23 "FPGA_EEM1_6_P" I R 7050 4150 50 -F24 "FPGA_EEM1_6_N" I R 7050 4250 50 -F25 "FPGA_EEM1_5_P" I R 7050 3950 50 -F26 "FPGA_EEM1_5_N" I R 7050 4050 50 -F27 "FPGA_EEM1_4_P" I R 7050 3750 50 -F28 "FPGA_EEM1_4_N" I R 7050 3850 50 -F29 "FPGA_EEM1_3_P" I R 7050 3550 50 -F30 "FPGA_EEM1_3_N" I R 7050 3650 50 -F31 "FPGA_EEM1_2_P" I R 7050 3350 50 -F32 "FPGA_EEM1_2_N" I R 7050 3450 50 -F33 "FPGA_EEM1_1_P" I R 7050 3150 50 -F34 "FPGA_EEM1_1_N" I R 7050 3250 50 -F35 "FPGA_EEM2_0_P" I R 7050 4750 50 -F36 "FPGA_EEM2_0_N" I R 7050 4850 50 -F37 "FPGA_EEM2_7_P" I R 7050 6150 50 -F38 "FPGA_EEM2_7_N" I R 7050 6250 50 -F39 "FPGA_EEM2_6_P" I R 7050 5950 50 -F40 "FPGA_EEM2_6_N" I R 7050 6050 50 -F41 "FPGA_EEM2_5_P" I R 7050 5750 50 -F42 "FPGA_EEM2_5_N" I R 7050 5850 50 -F43 "FPGA_EEM2_4_P" I R 7050 5550 50 -F44 "FPGA_EEM2_4_N" I R 7050 5650 50 -F45 "FPGA_EEM2_3_P" I R 7050 5350 50 -F46 "FPGA_EEM2_3_N" I R 7050 5450 50 -F47 "FPGA_EEM2_2_P" I R 7050 5150 50 -F48 "FPGA_EEM2_2_N" I R 7050 5250 50 -F49 "FPGA_EEM2_1_P" I R 7050 4950 50 -F50 "FPGA_EEM2_1_N" I R 7050 5050 50 -F51 "FPGA_IIC0_SDA" I R 7050 2850 50 -F52 "FPGA_IIC0_SCL" I R 7050 2750 50 -F53 "FPGA_IIC1_SDA" I R 7050 4650 50 -F54 "FPGA_IIC1_SCL" I R 7050 4550 50 -F55 "FPGA_IIC2_SDA" I R 7050 6450 50 -F56 "FPGA_IIC2_SCL" I R 7050 6350 50 -F57 "FPGA_FSMC_A0" I L 5550 1150 50 -F58 "FPGA_FSMC_A1" I L 5550 1250 50 -F59 "FPGA_FSMC_A2" I L 5550 1350 50 -F60 "FPGA_FSMC_A3" I L 5550 1450 50 -F61 "FPGA_FSMC_A4" I L 5550 1550 50 -F62 "FPGA_FSMC_A5" I L 5550 1650 50 -F63 "FPGA_FSMC_A6" I L 5550 1750 50 -F64 "FPGA_FSMC_A7" I L 5550 1850 50 -F65 "FPGA_FSMC_D0" I L 5550 1950 50 -F66 "FPGA_FSMC_D1" I L 5550 2050 50 -F67 "FPGA_FSMC_D2" I L 5550 2150 50 -F68 "FPGA_FSMC_D3" I L 5550 2250 50 -F69 "FPGA_FSMC_D4" I L 5550 2350 50 -F70 "FPGA_FSMC_D5" I L 5550 2450 50 -F71 "FPGA_FSMC_D6" I L 5550 2550 50 -F72 "FPGA_FSMC_D7" I L 5550 2650 50 -F73 "FPGA_FSMC_D8" I L 5550 2750 50 -F74 "FPGA_FSMC_D9" I L 5550 2850 50 -F75 "FPGA_FSMC_D10" I L 5550 2950 50 -F76 "FPGA_FSMC_D11" I L 5550 3050 50 -F77 "FPGA_FSMC_D12" I L 5550 3150 50 -F78 "FPGA_FSMC_D13" I L 5550 3250 50 -F79 "FPGA_FSMC_D14" I L 5550 3350 50 -F80 "FPGA_FSMC_D15" I L 5550 3450 50 -F81 "FPGA_CSBSEL0" I L 5550 3800 50 -F82 "FPGA_CSBSEL1" I L 5550 3900 50 -F83 "FPGA_SPI_SDO" I L 5550 4000 50 -F84 "FPGA_SPI_SDI" I L 5550 4100 50 -F85 "FPGA_SPI_SS" I L 5550 4200 50 -F86 "FPGA_SPI_SCK" I L 5550 4300 50 -F87 "FPGA_CDONE" I L 5550 4400 50 -F88 "FPGA_CRESET" I L 5550 4500 50 +F2 "FPGA_VPP_FAST" I L 4450 4500 50 +F3 "FPGA_EEM0_0_P" I R 5950 850 50 +F4 "FPGA_EEM0_0_N" I R 5950 950 50 +F5 "FPGA_EEM0_7_P" I R 5950 2250 50 +F6 "FPGA_EEM0_7_N" I R 5950 2350 50 +F7 "FPGA_EEM0_6_P" I R 5950 2050 50 +F8 "FPGA_EEM0_6_N" I R 5950 2150 50 +F9 "FPGA_EEM0_5_P" I R 5950 1850 50 +F10 "FPGA_EEM0_5_N" I R 5950 1950 50 +F11 "FPGA_EEM0_4_P" I R 5950 1650 50 +F12 "FPGA_EEM0_4_N" I R 5950 1750 50 +F13 "FPGA_EEM0_3_P" I R 5950 1450 50 +F14 "FPGA_EEM0_3_N" I R 5950 1550 50 +F15 "FPGA_EEM0_2_P" I R 5950 1250 50 +F16 "FPGA_EEM0_2_N" I R 5950 1350 50 +F17 "FPGA_EEM0_1_P" I R 5950 1050 50 +F18 "FPGA_EEM0_1_N" I R 5950 1150 50 +F19 "FPGA_EEM1_0_P" I R 5950 2650 50 +F20 "FPGA_EEM1_0_N" I R 5950 2750 50 +F21 "FPGA_EEM1_7_P" I R 5950 4050 50 +F22 "FPGA_EEM1_7_N" I R 5950 4150 50 +F23 "FPGA_EEM1_6_P" I R 5950 3850 50 +F24 "FPGA_EEM1_6_N" I R 5950 3950 50 +F25 "FPGA_EEM1_5_P" I R 5950 3650 50 +F26 "FPGA_EEM1_5_N" I R 5950 3750 50 +F27 "FPGA_EEM1_4_P" I R 5950 3450 50 +F28 "FPGA_EEM1_4_N" I R 5950 3550 50 +F29 "FPGA_EEM1_3_P" I R 5950 3250 50 +F30 "FPGA_EEM1_3_N" I R 5950 3350 50 +F31 "FPGA_EEM1_2_P" I R 5950 3050 50 +F32 "FPGA_EEM1_2_N" I R 5950 3150 50 +F33 "FPGA_EEM1_1_P" I R 5950 2850 50 +F34 "FPGA_EEM1_1_N" I R 5950 2950 50 +F35 "FPGA_EEM2_0_P" I R 5950 4450 50 +F36 "FPGA_EEM2_0_N" I R 5950 4550 50 +F37 "FPGA_EEM2_7_P" I R 5950 5850 50 +F38 "FPGA_EEM2_7_N" I R 5950 5950 50 +F39 "FPGA_EEM2_6_P" I R 5950 5650 50 +F40 "FPGA_EEM2_6_N" I R 5950 5750 50 +F41 "FPGA_EEM2_5_P" I R 5950 5450 50 +F42 "FPGA_EEM2_5_N" I R 5950 5550 50 +F43 "FPGA_EEM2_4_P" I R 5950 5250 50 +F44 "FPGA_EEM2_4_N" I R 5950 5350 50 +F45 "FPGA_EEM2_3_P" I R 5950 5050 50 +F46 "FPGA_EEM2_3_N" I R 5950 5150 50 +F47 "FPGA_EEM2_2_P" I R 5950 4850 50 +F48 "FPGA_EEM2_2_N" I R 5950 4950 50 +F49 "FPGA_EEM2_1_P" I R 5950 4650 50 +F50 "FPGA_EEM2_1_N" I R 5950 4750 50 +F51 "FPGA_IIC0_SDA" I R 5950 2550 50 +F52 "FPGA_IIC0_SCL" I R 5950 2450 50 +F53 "FPGA_IIC1_SDA" I R 5950 4350 50 +F54 "FPGA_IIC1_SCL" I R 5950 4250 50 +F55 "FPGA_IIC2_SDA" I R 5950 6150 50 +F56 "FPGA_IIC2_SCL" I R 5950 6050 50 +F57 "FPGA_FSMC_A0" I L 4450 850 50 +F58 "FPGA_FSMC_A1" I L 4450 950 50 +F59 "FPGA_FSMC_A2" I L 4450 1050 50 +F60 "FPGA_FSMC_A3" I L 4450 1150 50 +F61 "FPGA_FSMC_A4" I L 4450 1250 50 +F62 "FPGA_FSMC_A5" I L 4450 1350 50 +F63 "FPGA_FSMC_A6" I L 4450 1450 50 +F64 "FPGA_FSMC_A7" I L 4450 1550 50 +F65 "FPGA_FSMC_D0" I L 4450 1650 50 +F66 "FPGA_FSMC_D1" I L 4450 1750 50 +F67 "FPGA_FSMC_D2" I L 4450 1850 50 +F68 "FPGA_FSMC_D3" I L 4450 1950 50 +F69 "FPGA_FSMC_D4" I L 4450 2050 50 +F70 "FPGA_FSMC_D5" I L 4450 2150 50 +F71 "FPGA_FSMC_D6" I L 4450 2250 50 +F72 "FPGA_FSMC_D7" I L 4450 2350 50 +F73 "FPGA_FSMC_D8" I L 4450 2450 50 +F74 "FPGA_FSMC_D9" I L 4450 2550 50 +F75 "FPGA_FSMC_D10" I L 4450 2650 50 +F76 "FPGA_FSMC_D11" I L 4450 2750 50 +F77 "FPGA_FSMC_D12" I L 4450 2850 50 +F78 "FPGA_FSMC_D13" I L 4450 2950 50 +F79 "FPGA_FSMC_D14" I L 4450 3050 50 +F80 "FPGA_FSMC_D15" I L 4450 3150 50 +F81 "FPGA_CSBSEL0" I L 4450 3500 50 +F82 "FPGA_CSBSEL1" I L 4450 3600 50 +F83 "FPGA_SPI_SDO" I L 4450 3700 50 +F84 "FPGA_SPI_SDI" I L 4450 3800 50 +F85 "FPGA_SPI_SS" I L 4450 3900 50 +F86 "FPGA_SPI_SCK" I L 4450 4000 50 +F87 "FPGA_CDONE" I L 4450 4100 50 +F88 "FPGA_CRESET" I L 4450 4200 50 $EndSheet $EndSCHEMATC