From 74f4fc201a8cc4bdb6e7b1719441a66a6068a5a3 Mon Sep 17 00:00:00 2001 From: Jack-Zheng Date: Fri, 18 Jun 2021 10:27:05 +0800 Subject: [PATCH] FPGA: add GPIO and ADC parallel port --- Connectors.sch | 2 +- CurrentSenser.sch | 36 +++- FPGA.sch | 151 ++++++++++++++++- MCU.sch | 8 +- TestAutomation.sch | 415 ++++++++++++++++++++++++--------------------- 5 files changed, 405 insertions(+), 207 deletions(-) diff --git a/Connectors.sch b/Connectors.sch index 464fed7..2d9a8e0 100644 --- a/Connectors.sch +++ b/Connectors.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 8 8 +Sheet 6 8 Title "" Date "" Rev "" diff --git a/CurrentSenser.sch b/CurrentSenser.sch index b170ea4..2bff41f 100644 --- a/CurrentSenser.sch +++ b/CurrentSenser.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 7 8 +Sheet 5 8 Title "" Date "" Rev "" @@ -35,8 +35,6 @@ F 3 "" H 4600 5000 50 0001 C CNN 1 4600 5000 1 0 0 -1 $EndComp -Text HLabel 5900 4950 3 50 Input ~ 0 -12V_OUT $Comp L SI4425DDY:SI4425DDY-T1-GE3 Q? U 1 1 60F5F01A @@ -438,8 +436,36 @@ Wire Wire Line 6300 4750 5900 4750 Connection ~ 6300 4750 Connection ~ 5900 4750 -Wire Wire Line - 5900 4750 5900 4950 Text HLabel 8650 4100 2 50 Input ~ 0 12V_CURRENT +$Comp +L Connector_Generic:Conn_01x02 J8 +U 1 1 61786D79 +P 6200 5100 +F 0 "J8" H 6280 5092 50 0000 L CNN +F 1 "12V_OUT" H 6280 5001 50 0000 L CNN +F 2 "" H 6200 5100 50 0001 C CNN +F 3 "~" H 6200 5100 50 0001 C CNN + 1 6200 5100 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR086 +U 1 1 61787915 +P 5900 5400 +F 0 "#PWR086" H 5900 5150 50 0001 C CNN +F 1 "GND" H 5905 5227 50 0000 C CNN +F 2 "" H 5900 5400 50 0001 C CNN +F 3 "" H 5900 5400 50 0001 C CNN + 1 5900 5400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6000 5100 5900 5100 +Wire Wire Line + 5900 4750 5900 5100 +Wire Wire Line + 6000 5200 5900 5200 +Wire Wire Line + 5900 5200 5900 5400 $EndSCHEMATC diff --git a/FPGA.sch b/FPGA.sch index 9a0bb37..14c1eea 100644 --- a/FPGA.sch +++ b/FPGA.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 3 8 +Sheet 8 8 Title "" Date "" Rev "" @@ -293,8 +293,6 @@ F 3 "" H 10850 1900 50 0001 C CNN 1 10850 1900 0 1 1 0 $EndComp -Text HLabel 10850 1700 2 50 Input ~ 0 -FPGA_VPP_FAST $Comp L power:+2V5 #PWR061 U 1 1 6110673B @@ -366,8 +364,6 @@ Wire Wire Line Connection ~ 10550 1900 Wire Wire Line 10450 1600 10850 1600 -Wire Wire Line - 10450 1700 10850 1700 $Comp L Device:C C42 U 1 1 61137BFE @@ -2194,4 +2190,149 @@ Wire Wire Line 3750 1500 3850 1500 Wire Wire Line 3750 1600 3850 1600 +Text HLabel 3850 1900 2 50 Input ~ 0 +FPGA_ADC_D0 +Text HLabel 3850 2000 2 50 Input ~ 0 +FPGA_ADC_D1 +Text HLabel 3850 2100 2 50 Input ~ 0 +FPGA_ADC_D2 +Text HLabel 3850 2200 2 50 Input ~ 0 +FPGA_ADC_D3 +Text HLabel 3850 2300 2 50 Input ~ 0 +FPGA_ADC_D4 +Text HLabel 3850 2400 2 50 Input ~ 0 +FPGA_ADC_D5 +Text HLabel 3850 2500 2 50 Input ~ 0 +FPGA_ADC_D6 +Text HLabel 3850 2600 2 50 Input ~ 0 +FPGA_ADC_D7 +Text HLabel 3850 2700 2 50 Input ~ 0 +FPGA_ADC_CLK +Wire Wire Line + 3850 1900 3750 1900 +Wire Wire Line + 3850 2000 3750 2000 +Wire Wire Line + 3850 2100 3750 2100 +Wire Wire Line + 3850 2200 3750 2200 +Wire Wire Line + 3850 2300 3750 2300 +Wire Wire Line + 3850 2400 3750 2400 +Wire Wire Line + 3850 2500 3750 2500 +Wire Wire Line + 3850 2600 3750 2600 +Wire Wire Line + 3850 2700 3750 2700 +Text HLabel 1850 3300 2 50 Input ~ 0 +FPGA_FSMC_NWE +Text HLabel 1850 3400 2 50 Input ~ 0 +FPGA_FSMC_NOE +Text HLabel 1850 3500 2 50 Input ~ 0 +FPGA_FSMC_NE1 +Text HLabel 1850 3600 2 50 Input ~ 0 +FPGA_FSMC_NBL0 +Text HLabel 1850 3700 2 50 Input ~ 0 +FPGA_FSMC_NBL1 +Text HLabel 1850 3800 2 50 Input ~ 0 +FPGA_FSMC_NL +Text HLabel 1850 3900 2 50 Input ~ 0 +FPGA_FSMC_CLK +Text HLabel 1850 4000 2 50 Input ~ 0 +FPGA_FSMC_NWAIT +Wire Wire Line + 1850 3300 1800 3300 +Wire Wire Line + 1800 3400 1850 3400 +Wire Wire Line + 1800 3500 1850 3500 +Wire Wire Line + 1850 3600 1800 3600 +Wire Wire Line + 1800 3700 1850 3700 +Wire Wire Line + 1850 3800 1800 3800 +Wire Wire Line + 1800 3900 1850 3900 +Wire Wire Line + 1850 4000 1800 4000 +Text HLabel 3850 3000 2 50 Input ~ 0 +FPGA_IO0 +Text HLabel 3850 3100 2 50 Input ~ 0 +FPGA_IO1 +Text HLabel 3850 3200 2 50 Input ~ 0 +FPGA_IO2 +Text HLabel 3850 3300 2 50 Input ~ 0 +FPGA_IO3 +Text HLabel 3850 3400 2 50 Input ~ 0 +FPGA_IO4 +Text HLabel 3850 3500 2 50 Input ~ 0 +FPGA_IO5 +Text HLabel 3850 3600 2 50 Input ~ 0 +FPGA_IO6 +Text HLabel 3850 3700 2 50 Input ~ 0 +FPGA_IO7 +Text HLabel 3850 3800 2 50 Input ~ 0 +FPGA_IO8 +Text HLabel 3850 3900 2 50 Input ~ 0 +FPGA_IO9 +Text HLabel 3850 4000 2 50 Input ~ 0 +FPGA_IO10 +Text HLabel 3850 4100 2 50 Input ~ 0 +FPGA_IO11 +Text HLabel 3850 4200 2 50 Input ~ 0 +FPGA_IO12 +Text HLabel 3850 4300 2 50 Input ~ 0 +FPGA_IO13 +Text HLabel 3850 4400 2 50 Input ~ 0 +FPGA_IO14 +Text HLabel 3850 4500 2 50 Input ~ 0 +FPGA_IO15 +Wire Wire Line + 3850 3000 3750 3000 +Wire Wire Line + 3750 3100 3850 3100 +Wire Wire Line + 3850 3200 3750 3200 +Wire Wire Line + 3750 3300 3850 3300 +Wire Wire Line + 3850 3400 3750 3400 +Wire Wire Line + 3850 3500 3750 3500 +Wire Wire Line + 3850 3600 3750 3600 +Wire Wire Line + 3850 3700 3750 3700 +Wire Wire Line + 3850 3800 3750 3800 +Wire Wire Line + 3850 3900 3750 3900 +Wire Wire Line + 3850 4000 3750 4000 +Wire Wire Line + 3850 4100 3750 4100 +Wire Wire Line + 3850 4200 3750 4200 +Wire Wire Line + 3850 4300 3750 4300 +Wire Wire Line + 3750 4400 3850 4400 +Wire Wire Line + 3750 4500 3850 4500 +$Comp +L Connector:TestPoint TP? +U 1 1 617CC5CE +P 10500 1700 +F 0 "TP?" V 10454 1888 50 0000 L CNN +F 1 "FPGA_VPP_FAST" V 10545 1888 50 0000 L CNN +F 2 "" H 10700 1700 50 0001 C CNN +F 3 "~" H 10700 1700 50 0001 C CNN + 1 10500 1700 + 0 1 1 0 +$EndComp +Wire Wire Line + 10450 1700 10500 1700 $EndSCHEMATC diff --git a/MCU.sch b/MCU.sch index d18bc5f..b24ae77 100644 --- a/MCU.sch +++ b/MCU.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 8 8 +Sheet 7 8 Title "" Date "" Rev "" @@ -450,11 +450,11 @@ Wire Wire Line Wire Wire Line 2600 5250 3000 5250 Text HLabel 2600 5950 0 50 Input ~ 0 -CPU_FSMC_D13 +CPU_FSMC_DA13 Text HLabel 2600 6050 0 50 Input ~ 0 -CPU_FSMC_D14 +CPU_FSMC_DA14 Text HLabel 2600 6150 0 50 Input ~ 0 -CPU_FSMC_D15 +CPU_FSMC_DA15 Wire Wire Line 2600 5950 3000 5950 Wire Wire Line diff --git a/TestAutomation.sch b/TestAutomation.sch index f060678..e220c7c 100644 --- a/TestAutomation.sch +++ b/TestAutomation.sch @@ -30,101 +30,6 @@ F10 "ADC_DATA8" I L 7450 2150 50 F11 "ADC_IN" I L 7450 1150 50 $EndSheet $Sheet -S 4650 900 1500 5450 -U 60C0E996 -F0 "FPGA" 50 -F1 "FPGA.sch" 50 -F2 "FPGA_VPP_FAST" I L 4650 4600 50 -F3 "FPGA_EEM0_0_P" I R 6150 950 50 -F4 "FPGA_EEM0_0_N" I R 6150 1050 50 -F5 "FPGA_EEM0_7_P" I R 6150 2350 50 -F6 "FPGA_EEM0_7_N" I R 6150 2450 50 -F7 "FPGA_EEM0_6_P" I R 6150 2150 50 -F8 "FPGA_EEM0_6_N" I R 6150 2250 50 -F9 "FPGA_EEM0_5_P" I R 6150 1950 50 -F10 "FPGA_EEM0_5_N" I R 6150 2050 50 -F11 "FPGA_EEM0_4_P" I R 6150 1750 50 -F12 "FPGA_EEM0_4_N" I R 6150 1850 50 -F13 "FPGA_EEM0_3_P" I R 6150 1550 50 -F14 "FPGA_EEM0_3_N" I R 6150 1650 50 -F15 "FPGA_EEM0_2_P" I R 6150 1350 50 -F16 "FPGA_EEM0_2_N" I R 6150 1450 50 -F17 "FPGA_EEM0_1_P" I R 6150 1150 50 -F18 "FPGA_EEM0_1_N" I R 6150 1250 50 -F19 "FPGA_EEM1_0_P" I R 6150 2750 50 -F20 "FPGA_EEM1_0_N" I R 6150 2850 50 -F21 "FPGA_EEM1_7_P" I R 6150 4150 50 -F22 "FPGA_EEM1_7_N" I R 6150 4250 50 -F23 "FPGA_EEM1_6_P" I R 6150 3950 50 -F24 "FPGA_EEM1_6_N" I R 6150 4050 50 -F25 "FPGA_EEM1_5_P" I R 6150 3750 50 -F26 "FPGA_EEM1_5_N" I R 6150 3850 50 -F27 "FPGA_EEM1_4_P" I R 6150 3550 50 -F28 "FPGA_EEM1_4_N" I R 6150 3650 50 -F29 "FPGA_EEM1_3_P" I R 6150 3350 50 -F30 "FPGA_EEM1_3_N" I R 6150 3450 50 -F31 "FPGA_EEM1_2_P" I R 6150 3150 50 -F32 "FPGA_EEM1_2_N" I R 6150 3250 50 -F33 "FPGA_EEM1_1_P" I R 6150 2950 50 -F34 "FPGA_EEM1_1_N" I R 6150 3050 50 -F35 "FPGA_EEM2_0_P" I R 6150 4550 50 -F36 "FPGA_EEM2_0_N" I R 6150 4650 50 -F37 "FPGA_EEM2_7_P" I R 6150 5950 50 -F38 "FPGA_EEM2_7_N" I R 6150 6050 50 -F39 "FPGA_EEM2_6_P" I R 6150 5750 50 -F40 "FPGA_EEM2_6_N" I R 6150 5850 50 -F41 "FPGA_EEM2_5_P" I R 6150 5550 50 -F42 "FPGA_EEM2_5_N" I R 6150 5650 50 -F43 "FPGA_EEM2_4_P" I R 6150 5350 50 -F44 "FPGA_EEM2_4_N" I R 6150 5450 50 -F45 "FPGA_EEM2_3_P" I R 6150 5150 50 -F46 "FPGA_EEM2_3_N" I R 6150 5250 50 -F47 "FPGA_EEM2_2_P" I R 6150 4950 50 -F48 "FPGA_EEM2_2_N" I R 6150 5050 50 -F49 "FPGA_EEM2_1_P" I R 6150 4750 50 -F50 "FPGA_EEM2_1_N" I R 6150 4850 50 -F51 "FPGA_IIC0_SDA" I R 6150 2650 50 -F52 "FPGA_IIC0_SCL" I R 6150 2550 50 -F53 "FPGA_IIC1_SDA" I R 6150 4450 50 -F54 "FPGA_IIC1_SCL" I R 6150 4350 50 -F55 "FPGA_IIC2_SDA" I R 6150 6250 50 -F56 "FPGA_IIC2_SCL" I R 6150 6150 50 -F57 "FPGA_FSMC_A0" I L 4650 950 50 -F58 "FPGA_FSMC_A1" I L 4650 1050 50 -F59 "FPGA_FSMC_A2" I L 4650 1150 50 -F60 "FPGA_FSMC_A3" I L 4650 1250 50 -F61 "FPGA_FSMC_A4" I L 4650 1350 50 -F62 "FPGA_FSMC_A5" I L 4650 1450 50 -F63 "FPGA_FSMC_A6" I L 4650 1550 50 -F64 "FPGA_FSMC_A7" I L 4650 1650 50 -F65 "FPGA_FSMC_D0" I L 4650 1750 50 -F66 "FPGA_FSMC_D1" I L 4650 1850 50 -F67 "FPGA_FSMC_D2" I L 4650 1950 50 -F68 "FPGA_FSMC_D3" I L 4650 2050 50 -F69 "FPGA_FSMC_D4" I L 4650 2150 50 -F70 "FPGA_FSMC_D5" I L 4650 2250 50 -F71 "FPGA_FSMC_D6" I L 4650 2350 50 -F72 "FPGA_FSMC_D7" I L 4650 2450 50 -F73 "FPGA_FSMC_D8" I L 4650 2550 50 -F74 "FPGA_FSMC_D9" I L 4650 2650 50 -F75 "FPGA_FSMC_D10" I L 4650 2750 50 -F76 "FPGA_FSMC_D11" I L 4650 2850 50 -F77 "FPGA_FSMC_D12" I L 4650 2950 50 -F78 "FPGA_FSMC_D13" I L 4650 3050 50 -F79 "FPGA_FSMC_D14" I L 4650 3150 50 -F80 "FPGA_FSMC_D15" I L 4650 3250 50 -F81 "FPGA_CSBSEL0" I L 4650 3600 50 -F82 "FPGA_CSBSEL1" I L 4650 3700 50 -F83 "FPGA_SPI_SDO" I L 4650 3800 50 -F84 "FPGA_SPI_SDI" I L 4650 3900 50 -F85 "FPGA_SPI_SS" I L 4650 4000 50 -F86 "FPGA_SPI_SCK" I L 4650 4100 50 -F87 "FPGA_CDONE" I L 4650 4200 50 -F88 "FPGA_CRESET" I L 4650 4300 50 -F89 "FPGA_IIC3_SDA" I L 4650 5050 50 -F90 "FPGA_IIC3_SCL" I L 4650 4950 50 -$EndSheet -$Sheet S 2900 5300 650 1000 U 60E4702B F0 "Ethernet" 50 @@ -149,13 +54,12 @@ F5 "POE_SRC_Status" I L 1650 5900 50 F6 "POE_CPU_RESET" I L 1650 6000 50 $EndSheet $Sheet -S 1650 6600 650 500 +S 1650 6600 650 300 U 60E3407A F0 "CurrentSenser" 50 F1 "CurrentSenser.sch" 50 -F2 "12V_OUT" I L 1650 6700 50 -F3 "12V_SW" I L 1650 6850 50 -F4 "12V_CURRENT" I L 1650 7000 50 +F3 "12V_SW" I L 1650 6700 50 +F4 "12V_CURRENT" I L 1650 6800 50 $EndSheet $Sheet S 7500 3050 750 1150 @@ -175,102 +79,229 @@ Wire Wire Line 2500 5600 2500 6200 Wire Wire Line 2500 6200 2900 6200 -NoConn ~ 1750 1000 -NoConn ~ 1750 1100 -NoConn ~ 1750 1300 -NoConn ~ 1750 1400 -NoConn ~ 1750 1500 -NoConn ~ 1750 1600 -NoConn ~ 1750 1700 -NoConn ~ 1750 1800 -NoConn ~ 1750 1900 -NoConn ~ 1750 2000 -NoConn ~ 1750 2450 -NoConn ~ 1750 2550 -NoConn ~ 1750 3250 -NoConn ~ 1750 3350 -NoConn ~ 1750 3450 -NoConn ~ 1750 3550 -NoConn ~ 1750 3800 -NoConn ~ 1750 3900 -NoConn ~ 1750 4050 -NoConn ~ 1750 4150 -NoConn ~ 1750 4400 -NoConn ~ 1750 4500 -NoConn ~ 1750 4600 -NoConn ~ 1750 4700 +NoConn ~ 1800 950 +NoConn ~ 1800 1050 +NoConn ~ 1800 1250 +NoConn ~ 1800 1350 +NoConn ~ 1800 1450 +NoConn ~ 1800 1550 +NoConn ~ 1800 1650 +NoConn ~ 1800 1750 +NoConn ~ 1800 1850 +NoConn ~ 1800 1950 +NoConn ~ 1800 2400 +NoConn ~ 1800 2500 +NoConn ~ 1800 3200 +NoConn ~ 1800 3300 +NoConn ~ 1800 3400 +NoConn ~ 1800 3500 +NoConn ~ 1800 3750 +NoConn ~ 1800 3850 +NoConn ~ 1800 4000 +NoConn ~ 1800 4100 +NoConn ~ 1800 4350 +NoConn ~ 1800 4450 +NoConn ~ 1800 4550 +NoConn ~ 1800 4650 $Sheet -S 1750 900 1500 3950 +S 1800 850 1500 3950 U 60C2FDBB F0 "MCU" 50 F1 "MCU.sch" 50 -F2 "CPU_DAC0" I L 1750 1000 50 -F3 "CPU_DAC1" I L 1750 1100 50 -F4 "CPU_ADC1" I L 1750 1400 50 -F5 "CPU_ADC2" I L 1750 1500 50 -F6 "CPU_ADC3" I L 1750 1600 50 -F7 "CPU_ADC4" I L 1750 1700 50 -F8 "CPU_ADC0" I L 1750 1300 50 -F9 "CPU_ADC5" I L 1750 1800 50 -F10 "CPU_ADC6" I L 1750 1900 50 -F11 "CPU_ADC7" I L 1750 2000 50 -F12 "CPU_IIC2_SCL" I L 1750 2450 50 -F13 "CPU_IIC2_SDA" I L 1750 2550 50 -F14 "CPU_SPI2_SCK" I L 1750 3250 50 -F15 "CPU_SPI2_MISO" I L 1750 3350 50 -F16 "CPU_SPI2_MOSI" I L 1750 3450 50 -F17 "CPU_SWDIO" I R 3250 4450 50 -F18 "CPU_SWCLK" I R 3250 4550 50 -F19 "CPU_UART1_TX" I L 1750 3800 50 -F20 "CPU_UART1_RX" I L 1750 3900 50 -F21 "CPU_UART4_TX" I L 1750 4050 50 -F22 "CPU_UART4_RX" I L 1750 4150 50 -F23 "CPU_IIC1_SCL" I L 1750 2200 50 -F24 "CPU_IIC1_SDA" I L 1750 2300 50 -F25 "CPU_SPI1_SCK" I L 1750 2750 50 -F26 "CPU_SPI1_MISO" I L 1750 2850 50 -F27 "CPU_SPI1_MOSI" I L 1750 2950 50 -F28 "CPU_SPI2_CS" I L 1750 3550 50 -F29 "CPU_SPI1_CS" I L 1750 3050 50 -F30 "CPU_FSMC_DA0" I R 3250 1000 50 -F31 "CPU_FSMC_DA1" I R 3250 1100 50 -F32 "CPU_FSMC_DA2" I R 3250 1200 50 -F33 "CPU_FSMC_DA3" I R 3250 1300 50 -F34 "CPU_FSMC_DA4" I R 3250 1400 50 -F35 "CPU_FSMC_DA5" I R 3250 1500 50 -F36 "CPU_FSMC_DA6" I R 3250 1600 50 -F37 "CPU_FSMC_DA7" I R 3250 1700 50 -F38 "CPU_FSMC_DA8" I R 3250 1800 50 -F39 "CPU_FSMC_DA9" I R 3250 1900 50 -F40 "CPU_FSMC_DA10" I R 3250 2000 50 -F41 "CPU_FSMC_DA11" I R 3250 2100 50 -F42 "CPU_FSMC_DA12" I R 3250 2200 50 -F43 "CPU_FSMC_D13" I R 3250 2300 50 -F44 "CPU_FSMC_D14" I R 3250 2400 50 -F45 "CPU_FSMC_D15" I R 3250 2500 50 -F46 "CPU_FSMC_A16" I R 3250 2600 50 -F47 "CPU_FSMC_A17" I R 3250 2700 50 -F48 "CPU_FSMC_A18" I R 3250 2800 50 -F49 "CPU_FSMC_A19" I R 3250 2900 50 -F50 "CPU_FSMC_A20" I R 3250 3000 50 -F51 "CPU_FSMC_A21" I R 3250 3100 50 -F52 "CPU_FSMC_A22" I R 3250 3200 50 -F53 "CPU_FSMC_A23" I R 3250 3300 50 -F54 "CPU_FSMC_NWE" I R 3250 3450 50 -F55 "CPU_FSMC_NOE" I R 3250 3550 50 -F56 "CPU_FSMC_NE1" I R 3250 3650 50 -F57 "CPU_PWM_CH1" I L 1750 4400 50 -F58 "CPU_PWM_CH2" I L 1750 4500 50 -F59 "CPU_PWM_CH3" I L 1750 4600 50 -F60 "CPU_PWM_CH4" I L 1750 4700 50 -F61 "CPU_FSMC_NBL0" I R 3250 3750 50 -F62 "CPU_FSMC_NBL1" I R 3250 3850 50 -F63 "CPU_FSMC_NL" I R 3250 3950 50 -F64 "CPU_FSMC_CLK" I R 3250 4050 50 -F65 "CPU_FSMC_NWAIT" I R 3250 4150 50 -F66 "CPU_ENC_CS" I L 1750 3150 50 -F67 "CPU_ADC8" I L 1750 1200 50 +F2 "CPU_DAC0" I L 1800 950 50 +F3 "CPU_DAC1" I L 1800 1050 50 +F4 "CPU_ADC1" I L 1800 1350 50 +F5 "CPU_ADC2" I L 1800 1450 50 +F6 "CPU_ADC3" I L 1800 1550 50 +F7 "CPU_ADC4" I L 1800 1650 50 +F8 "CPU_ADC0" I L 1800 1250 50 +F9 "CPU_ADC5" I L 1800 1750 50 +F10 "CPU_ADC6" I L 1800 1850 50 +F11 "CPU_ADC7" I L 1800 1950 50 +F12 "CPU_IIC2_SCL" I L 1800 2400 50 +F13 "CPU_IIC2_SDA" I L 1800 2500 50 +F14 "CPU_SPI2_SCK" I L 1800 3200 50 +F15 "CPU_SPI2_MISO" I L 1800 3300 50 +F16 "CPU_SPI2_MOSI" I L 1800 3400 50 +F17 "CPU_SWDIO" I R 3300 4400 50 +F18 "CPU_SWCLK" I R 3300 4500 50 +F19 "CPU_UART1_TX" I L 1800 3750 50 +F20 "CPU_UART1_RX" I L 1800 3850 50 +F21 "CPU_UART4_TX" I L 1800 4000 50 +F22 "CPU_UART4_RX" I L 1800 4100 50 +F23 "CPU_IIC1_SCL" I L 1800 2150 50 +F24 "CPU_IIC1_SDA" I L 1800 2250 50 +F25 "CPU_SPI1_SCK" I L 1800 2700 50 +F26 "CPU_SPI1_MISO" I L 1800 2800 50 +F27 "CPU_SPI1_MOSI" I L 1800 2900 50 +F28 "CPU_SPI2_CS" I L 1800 3500 50 +F29 "CPU_SPI1_CS" I L 1800 3000 50 +F30 "CPU_FSMC_DA0" I R 3300 950 50 +F31 "CPU_FSMC_DA1" I R 3300 1050 50 +F32 "CPU_FSMC_DA2" I R 3300 1150 50 +F33 "CPU_FSMC_DA3" I R 3300 1250 50 +F34 "CPU_FSMC_DA4" I R 3300 1350 50 +F35 "CPU_FSMC_DA5" I R 3300 1450 50 +F36 "CPU_FSMC_DA6" I R 3300 1550 50 +F37 "CPU_FSMC_DA7" I R 3300 1650 50 +F38 "CPU_FSMC_DA8" I R 3300 1750 50 +F39 "CPU_FSMC_DA9" I R 3300 1850 50 +F40 "CPU_FSMC_DA10" I R 3300 1950 50 +F41 "CPU_FSMC_DA11" I R 3300 2050 50 +F42 "CPU_FSMC_DA12" I R 3300 2150 50 +F43 "CPU_FSMC_A16" I R 3300 2550 50 +F44 "CPU_FSMC_A17" I R 3300 2650 50 +F45 "CPU_FSMC_A18" I R 3300 2750 50 +F46 "CPU_FSMC_A19" I R 3300 2850 50 +F47 "CPU_FSMC_A20" I R 3300 2950 50 +F48 "CPU_FSMC_A21" I R 3300 3050 50 +F49 "CPU_FSMC_A22" I R 3300 3150 50 +F50 "CPU_FSMC_A23" I R 3300 3250 50 +F51 "CPU_FSMC_NWE" I R 3300 3400 50 +F52 "CPU_FSMC_NOE" I R 3300 3500 50 +F53 "CPU_FSMC_NE1" I R 3300 3600 50 +F54 "CPU_PWM_CH1" I L 1800 4350 50 +F55 "CPU_PWM_CH2" I L 1800 4450 50 +F56 "CPU_PWM_CH3" I L 1800 4550 50 +F57 "CPU_PWM_CH4" I L 1800 4650 50 +F58 "CPU_FSMC_NBL0" I R 3300 3700 50 +F59 "CPU_FSMC_NBL1" I R 3300 3800 50 +F60 "CPU_FSMC_NL" I R 3300 3900 50 +F61 "CPU_FSMC_CLK" I R 3300 4000 50 +F62 "CPU_FSMC_NWAIT" I R 3300 4100 50 +F63 "CPU_ENC_CS" I L 1800 3100 50 +F64 "CPU_ADC8" I L 1800 1150 50 +F65 "CPU_FSMC_DA13" I R 3300 2250 50 +F66 "CPU_FSMC_DA14" I R 3300 2350 50 +F67 "CPU_FSMC_DA15" I R 3300 2450 50 +$EndSheet +NoConn ~ 3300 4400 +NoConn ~ 3300 4500 +$Sheet +S 4650 850 1500 6450 +U 60C0E996 +F0 "FPGA" 50 +F1 "FPGA.sch" 50 +F2 "FPGA_EEM0_0_P" I R 6150 950 50 +F3 "FPGA_EEM0_0_N" I R 6150 1050 50 +F4 "FPGA_EEM0_7_P" I R 6150 2350 50 +F5 "FPGA_EEM0_7_N" I R 6150 2450 50 +F6 "FPGA_EEM0_6_P" I R 6150 2150 50 +F7 "FPGA_EEM0_6_N" I R 6150 2250 50 +F8 "FPGA_EEM0_5_P" I R 6150 1950 50 +F9 "FPGA_EEM0_5_N" I R 6150 2050 50 +F10 "FPGA_EEM0_4_P" I R 6150 1750 50 +F11 "FPGA_EEM0_4_N" I R 6150 1850 50 +F12 "FPGA_EEM0_3_P" I R 6150 1550 50 +F13 "FPGA_EEM0_3_N" I R 6150 1650 50 +F14 "FPGA_EEM0_2_P" I R 6150 1350 50 +F15 "FPGA_EEM0_2_N" I R 6150 1450 50 +F16 "FPGA_EEM0_1_P" I R 6150 1150 50 +F17 "FPGA_EEM0_1_N" I R 6150 1250 50 +F18 "FPGA_EEM1_0_P" I R 6150 2750 50 +F19 "FPGA_EEM1_0_N" I R 6150 2850 50 +F20 "FPGA_EEM1_7_P" I R 6150 4150 50 +F21 "FPGA_EEM1_7_N" I R 6150 4250 50 +F22 "FPGA_EEM1_6_P" I R 6150 3950 50 +F23 "FPGA_EEM1_6_N" I R 6150 4050 50 +F24 "FPGA_EEM1_5_P" I R 6150 3750 50 +F25 "FPGA_EEM1_5_N" I R 6150 3850 50 +F26 "FPGA_EEM1_4_P" I R 6150 3550 50 +F27 "FPGA_EEM1_4_N" I R 6150 3650 50 +F28 "FPGA_EEM1_3_P" I R 6150 3350 50 +F29 "FPGA_EEM1_3_N" I R 6150 3450 50 +F30 "FPGA_EEM1_2_P" I R 6150 3150 50 +F31 "FPGA_EEM1_2_N" I R 6150 3250 50 +F32 "FPGA_EEM1_1_P" I R 6150 2950 50 +F33 "FPGA_EEM1_1_N" I R 6150 3050 50 +F34 "FPGA_EEM2_0_P" I R 6150 4550 50 +F35 "FPGA_EEM2_0_N" I R 6150 4650 50 +F36 "FPGA_EEM2_7_P" I R 6150 5950 50 +F37 "FPGA_EEM2_7_N" I R 6150 6050 50 +F38 "FPGA_EEM2_6_P" I R 6150 5750 50 +F39 "FPGA_EEM2_6_N" I R 6150 5850 50 +F40 "FPGA_EEM2_5_P" I R 6150 5550 50 +F41 "FPGA_EEM2_5_N" I R 6150 5650 50 +F42 "FPGA_EEM2_4_P" I R 6150 5350 50 +F43 "FPGA_EEM2_4_N" I R 6150 5450 50 +F44 "FPGA_EEM2_3_P" I R 6150 5150 50 +F45 "FPGA_EEM2_3_N" I R 6150 5250 50 +F46 "FPGA_EEM2_2_P" I R 6150 4950 50 +F47 "FPGA_EEM2_2_N" I R 6150 5050 50 +F48 "FPGA_EEM2_1_P" I R 6150 4750 50 +F49 "FPGA_EEM2_1_N" I R 6150 4850 50 +F50 "FPGA_IIC0_SDA" I R 6150 2650 50 +F51 "FPGA_IIC0_SCL" I R 6150 2550 50 +F52 "FPGA_IIC1_SDA" I R 6150 4450 50 +F53 "FPGA_IIC1_SCL" I R 6150 4350 50 +F54 "FPGA_IIC2_SDA" I R 6150 6250 50 +F55 "FPGA_IIC2_SCL" I R 6150 6150 50 +F56 "FPGA_FSMC_A0" I L 4650 950 50 +F57 "FPGA_FSMC_A1" I L 4650 1050 50 +F58 "FPGA_FSMC_A2" I L 4650 1150 50 +F59 "FPGA_FSMC_A3" I L 4650 1250 50 +F60 "FPGA_FSMC_A4" I L 4650 1350 50 +F61 "FPGA_FSMC_A5" I L 4650 1450 50 +F62 "FPGA_FSMC_A6" I L 4650 1550 50 +F63 "FPGA_FSMC_A7" I L 4650 1650 50 +F64 "FPGA_FSMC_D0" I L 4650 1750 50 +F65 "FPGA_FSMC_D1" I L 4650 1850 50 +F66 "FPGA_FSMC_D2" I L 4650 1950 50 +F67 "FPGA_FSMC_D3" I L 4650 2050 50 +F68 "FPGA_FSMC_D4" I L 4650 2150 50 +F69 "FPGA_FSMC_D5" I L 4650 2250 50 +F70 "FPGA_FSMC_D6" I L 4650 2350 50 +F71 "FPGA_FSMC_D7" I L 4650 2450 50 +F72 "FPGA_FSMC_D8" I L 4650 2550 50 +F73 "FPGA_FSMC_D9" I L 4650 2650 50 +F74 "FPGA_FSMC_D10" I L 4650 2750 50 +F75 "FPGA_FSMC_D11" I L 4650 2850 50 +F76 "FPGA_FSMC_D12" I L 4650 2950 50 +F77 "FPGA_FSMC_D13" I L 4650 3050 50 +F78 "FPGA_FSMC_D14" I L 4650 3150 50 +F79 "FPGA_FSMC_D15" I L 4650 3250 50 +F80 "FPGA_CSBSEL0" I L 4650 4250 50 +F81 "FPGA_CSBSEL1" I L 4650 4350 50 +F82 "FPGA_SPI_SDO" I L 4650 4450 50 +F83 "FPGA_SPI_SDI" I L 4650 4550 50 +F84 "FPGA_SPI_SS" I L 4650 4650 50 +F85 "FPGA_SPI_SCK" I L 4650 4750 50 +F86 "FPGA_CDONE" I L 4650 4850 50 +F87 "FPGA_CRESET" I L 4650 4950 50 +F88 "FPGA_IIC3_SDA" I L 4650 5200 50 +F89 "FPGA_IIC3_SCL" I L 4650 5100 50 +F90 "FPGA_ADC_D0" I R 6150 6400 50 +F91 "FPGA_ADC_D1" I R 6150 6500 50 +F92 "FPGA_ADC_D2" I R 6150 6600 50 +F93 "FPGA_ADC_D3" I R 6150 6700 50 +F94 "FPGA_ADC_D4" I R 6150 6800 50 +F95 "FPGA_ADC_D5" I R 6150 6900 50 +F96 "FPGA_ADC_D6" I R 6150 7000 50 +F97 "FPGA_ADC_D7" I R 6150 7100 50 +F98 "FPGA_ADC_CLK" I R 6150 7200 50 +F99 "FPGA_FSMC_NWE" I L 4650 3400 50 +F100 "FPGA_FSMC_NOE" I L 4650 3500 50 +F101 "FPGA_FSMC_NE1" I L 4650 3600 50 +F102 "FPGA_FSMC_NBL0" I L 4650 3700 50 +F103 "FPGA_FSMC_NBL1" I L 4650 3800 50 +F104 "FPGA_FSMC_NL" I L 4650 3900 50 +F105 "FPGA_FSMC_CLK" I L 4650 4000 50 +F106 "FPGA_FSMC_NWAIT" I L 4650 4100 50 +F107 "FPGA_IO0" I L 4650 5350 50 +F108 "FPGA_IO1" I L 4650 5450 50 +F109 "FPGA_IO2" I L 4650 5550 50 +F110 "FPGA_IO3" I L 4650 5650 50 +F111 "FPGA_IO4" I L 4650 5750 50 +F112 "FPGA_IO5" I L 4650 5850 50 +F113 "FPGA_IO6" I L 4650 5950 50 +F114 "FPGA_IO7" I L 4650 6050 50 +F115 "FPGA_IO8" I L 4650 6150 50 +F116 "FPGA_IO9" I L 4650 6250 50 +F117 "FPGA_IO10" I L 4650 6350 50 +F118 "FPGA_IO11" I L 4650 6450 50 +F119 "FPGA_IO12" I L 4650 6550 50 +F120 "FPGA_IO13" I L 4650 6650 50 +F121 "FPGA_IO14" I L 4650 6750 50 +F122 "FPGA_IO15" I L 4650 6850 50 $EndSheet -NoConn ~ 3250 4450 -NoConn ~ 3250 4550 $EndSCHEMATC