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Ethernet: finish ethernet controller and PoE input

This commit is contained in:
Jack-Zheng 2021-06-15 16:49:17 +08:00
parent e28d01d115
commit 66188cd3ad
4 changed files with 2259 additions and 14 deletions
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Ethernet.sch Normal file
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Ethernet.sch-bak Normal file
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37
TestAutomation.sch
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@ -3,7 +3,7 @@ EELAYER 30 0
EELAYER END EELAYER END
$Descr A4 11693 8268 $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 1 5 Sheet 1 6
Title "" Title ""
Date "" Date ""
Rev "" Rev ""
@ -22,12 +22,6 @@ F2 "FPGA_VCC" I R 7600 1300 50
F3 "FPGA_GND" I R 7600 1600 50 F3 "FPGA_GND" I R 7600 1600 50
$EndSheet $EndSheet
$Sheet $Sheet
S 2150 1100 1950 2550
U 60C2FDBB
F0 "MCU" 50
F1 "MCU.sch" 50
$EndSheet
$Sheet
S 2150 5000 2050 2150 S 2150 5000 2050 2150
U 60C2FE2A U 60C2FE2A
F0 "Power" 50 F0 "Power" 50
@ -39,4 +33,33 @@ U 60FB17F2
F0 "Analog_LVDS" 50 F0 "Analog_LVDS" 50
F1 "Analog_LVDS.sch" 50 F1 "Analog_LVDS.sch" 50
$EndSheet $EndSheet
$Sheet
S 2150 1100 1950 2550
U 60C2FDBB
F0 "MCU" 50
F1 "MCU.sch" 50
F2 "CPU_DAC0" I L 2150 1250 50
F3 "CPU_DAC1" I L 2150 1350 50
F4 "CPU_ADC1" I L 2150 1600 50
F5 "CPU_ADC2" I L 2150 1700 50
F6 "CPU_ADC3" I L 2150 1800 50
F7 "CPU_ADC4" I L 2150 1900 50
F8 "CPU_ADC0" I L 2150 1500 50
F9 "CPU_ADC5" I L 2150 2000 50
F10 "CPU_ADC6" I L 2150 2100 50
F11 "CPU_ADC7" I L 2150 2200 50
$EndSheet
$Sheet
S 9150 2050 1200 1400
U 60E4702B
F0 "Ethernet" 50
F1 "Ethernet.sch" 50
F2 "POE_VC+" I L 9150 3300 50
F3 "POE_VC-" I L 9150 3150 50
F4 "ENC_SPI_SCK" I L 9150 2750 50
F5 "ENC_SPI_MOSI" I L 9150 2650 50
F6 "ENC_SPI_MISO" I L 9150 2550 50
F7 "ENC_INT" I L 9150 2350 50
F8 "ENC_SPI_CS" I L 9150 2450 50
$EndSheet
$EndSCHEMATC $EndSCHEMATC

30
TestAutomation.sch-bak
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@ -3,7 +3,7 @@ EELAYER 30 0
EELAYER END EELAYER END
$Descr A4 11693 8268 $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 1 5 Sheet 1 6
Title "" Title ""
Date "" Date ""
Rev "" Rev ""
@ -22,12 +22,6 @@ F2 "FPGA_VCC" I R 7600 1300 50
F3 "FPGA_GND" I R 7600 1600 50 F3 "FPGA_GND" I R 7600 1600 50
$EndSheet $EndSheet
$Sheet $Sheet
S 2150 1100 1950 2550
U 60C2FDBB
F0 "MCU" 50
F1 "MCU.sch" 50
$EndSheet
$Sheet
S 2150 5000 2050 2150 S 2150 5000 2050 2150
U 60C2FE2A U 60C2FE2A
F0 "Power" 50 F0 "Power" 50
@ -39,4 +33,26 @@ U 60FB17F2
F0 "Analog_LVDS" 50 F0 "Analog_LVDS" 50
F1 "Analog_LVDS.sch" 50 F1 "Analog_LVDS.sch" 50
$EndSheet $EndSheet
$Sheet
S 2150 1100 1950 2550
U 60C2FDBB
F0 "MCU" 50
F1 "MCU.sch" 50
F2 "CPU_DAC0" I L 2150 1250 50
F3 "CPU_DAC1" I L 2150 1350 50
F4 "CPU_ADC1" I L 2150 1600 50
F5 "CPU_ADC2" I L 2150 1700 50
F6 "CPU_ADC3" I L 2150 1800 50
F7 "CPU_ADC4" I L 2150 1900 50
F8 "CPU_ADC0" I L 2150 1500 50
F9 "CPU_ADC5" I L 2150 2000 50
F10 "CPU_ADC6" I L 2150 2100 50
F11 "CPU_ADC7" I L 2150 2200 50
$EndSheet
$Sheet
S 9150 2050 1200 1400
U 60E4702B
F0 "Ethernet" 50
F1 "Ethernet.sch" 50
$EndSheet
$EndSCHEMATC $EndSCHEMATC