PCB: finish SWD, IIC
This commit is contained in:
parent
0e1120d266
commit
4b15f466a0
349
FPGA.sch
349
FPGA.sch
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@ -158,17 +158,17 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 1160 695
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Text Label 3850 -400 0 50 ~ 0
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Text Label 3800 3700 0 50 ~ 0
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I2C_0_SDA
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@ -200,30 +200,30 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 3360 695
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Text HLabel 3900 -400 2 50 Input ~ 0
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Text HLabel 3850 3700 2 50 Input ~ 0
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FPGA_EEM0_IIC_SDA
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Text HLabel 3900 -300 2 50 Input ~ 0
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Text HLabel 3850 4900 2 50 Input ~ 0
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FPGA_EEM2_IIC_SDA
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Text HLabel 3900 100 2 50 Input ~ 0
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Text HLabel 3850 4700 2 50 Input ~ 0
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FPGA_EEM2_IIC_SCL
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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3750 3900 3850 3900
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@ -549,14 +549,14 @@ F 3 "~" H 8700 6800 50 0001 C CNN
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Text HLabel 3900 200 2 50 Input ~ 0
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Text HLabel 3850 5600 2 50 Input ~ 0
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FPGA_IIC_SDA
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Text HLabel 3900 300 2 50 Input ~ 0
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Text HLabel 3850 5300 2 50 Input ~ 0
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FPGA_IIC_SCL
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Wire Wire Line
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3800 200 3900 200
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FPGA_ADC_D1
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@ -738,132 +738,132 @@ $EndComp
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1 4350 5000
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F 3 "~" H 4350 5300 50 0001 C CNN
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1 4350 5300
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F 3 "~" H 10400 7050 50 0001 C CNN
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1 10400 7050
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F 2 "" H 4350 4750 50 0001 C CNN
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F 3 "" H 4350 4750 50 0001 C CNN
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1 4350 4750
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P 10950 7050
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F 0 "#PWR011" H 10950 6900 50 0001 C CNN
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F 1 "+3V3" H 10965 7223 50 0000 C CNN
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F 2 "" H 10950 7050 50 0001 C CNN
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F 3 "" H 10950 7050 50 0001 C CNN
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1 10950 7050
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0 1 1 0
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L power:GND #PWR012
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U 1 1 61C1A434
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F 0 "#PWR012" H 4350 5800 50 0001 C CNN
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F 1 "GND" H 4355 5877 50 0000 C CNN
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F 2 "" H 4350 6050 50 0001 C CNN
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F 3 "" H 4350 6050 50 0001 C CNN
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1 4350 6050
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1 0 0 -1
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P 9650 7050
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F 0 "#PWR012" H 9650 6800 50 0001 C CNN
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F 1 "GND" H 9655 6877 50 0000 C CNN
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F 2 "" H 9650 7050 50 0001 C CNN
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F 3 "" H 9650 7050 50 0001 C CNN
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1 9650 7050
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0 1 1 0
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$EndComp
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Wire Wire Line
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4350 4900 4350 4850
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10800 7050 10850 7050
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Wire Wire Line
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4350 5100 4350 5150
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10600 7050 10550 7050
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Wire Wire Line
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4350 5450 4350 5500
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10250 7050 10200 7050
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Wire Wire Line
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4350 5900 4350 6000
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9800 7050 9700 7050
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Wire Wire Line
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4350 6000 4350 6050
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Connection ~ 4350 6000
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9700 7050 9650 7050
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Connection ~ 9700 7050
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Wire Wire Line
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3900 6000 4350 6000
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9700 6600 9700 7050
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Wire Wire Line
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2200 7500 2200 7550
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L Switch:SW_Push SW?
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U 1 1 6100CA18
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P 10300 6600
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AR Path="/60C2FDBB/6100CA18" Ref="SW?" Part="1"
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AR Path="/60C0E996/6100CA18" Ref="SW1" Part="1"
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F 0 "SW1" H 3900 5685 50 0000 C CNN
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F 1 "SW_FPGA" H 3900 5594 50 0000 C CNN
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F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 3900 5600 50 0001 C CNN
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F 3 "~" H 3900 5600 50 0001 C CNN
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1 3900 5400
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0 -1 -1 0
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F 0 "SW1" H 10300 6885 50 0000 C CNN
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F 1 "SW_FPGA" H 10300 6794 50 0000 C CNN
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F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 10300 6800 50 0001 C CNN
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F 3 "~" H 10300 6800 50 0001 C CNN
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1 10300 6600
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1 0 0 -1
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$EndComp
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$Comp
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||||
L Device:R_Small R8
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U 1 1 61AE7ED5
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P 4250 5000
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F 0 "R8" H 4309 5046 50 0000 L CNN
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F 1 "10k" H 4309 4955 50 0000 L CNN
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F 2 "Resistor_SMD:R_0402_1005Metric" H 4250 5000 50 0001 C CNN
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F 3 "~" H 4250 5000 50 0001 C CNN
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1 4250 5000
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-1 0 0 1
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P 10700 6950
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||||
F 0 "R8" H 10759 6996 50 0000 L CNN
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F 1 "10k" H 10759 6905 50 0000 L CNN
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F 2 "Resistor_SMD:R_0402_1005Metric" H 10700 6950 50 0001 C CNN
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||||
F 3 "~" H 10700 6950 50 0001 C CNN
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1 10700 6950
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0 -1 -1 0
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||||
$EndComp
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||||
Wire Wire Line
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3900 4700 3900 5150
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11000 6600 10550 6600
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Wire Wire Line
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4250 4900 4250 4850
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10800 6950 10850 6950
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Wire Wire Line
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4250 4850 4350 4850
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10850 6950 10850 7050
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Wire Wire Line
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4350 4850 4350 4750
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Connection ~ 4350 4850
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10850 7050 10950 7050
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Connection ~ 10850 7050
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Wire Wire Line
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4250 5100 4250 5150
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10600 6950 10550 6950
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Wire Wire Line
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4250 5150 3900 5150
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Connection ~ 3900 5150
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10550 6950 10550 6600
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Connection ~ 10550 6600
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Wire Wire Line
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3900 5150 3900 5200
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10550 6600 10500 6600
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Wire Wire Line
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3900 5600 3900 6000
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10100 6600 9700 6600
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$Comp
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||||
L TestAutomation:ICE40HX8K-CT256 U3
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U 5 1 6256A27C
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@ -2508,119 +2508,12 @@ Wire Wire Line
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8150 3900 8300 3900
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Wire Wire Line
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8150 4000 8300 4000
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Text Label 12050 1050 0 50 ~ 0
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LVDS0_0_P
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Text Label 12050 1150 0 50 ~ 0
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LVDS0_0_N
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Text Label 12050 1250 0 50 ~ 0
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LVDS0_1_P
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Text Label 12050 1350 0 50 ~ 0
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LVDS0_1_N
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Text Label 12050 1450 0 50 ~ 0
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LVDS0_2_P
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Text Label 12050 1550 0 50 ~ 0
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LVDS0_2_N
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Text Label 12050 1650 0 50 ~ 0
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LVDS0_3_P
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Text Label 12050 1750 0 50 ~ 0
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LVDS0_3_N
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Text Label 12050 1850 0 50 ~ 0
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||||
LVDS0_4_P
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Text Label 12050 1950 0 50 ~ 0
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LVDS0_4_N
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Text Label 12050 2050 0 50 ~ 0
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LVDS0_5_P
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Text Label 12050 2150 0 50 ~ 0
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LVDS0_5_N
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Text Label 12050 2250 0 50 ~ 0
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LVDS0_6_P
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Text Label 12050 2350 0 50 ~ 0
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LVDS0_6_N
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Text Label 12050 2450 0 50 ~ 0
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LVDS0_7_P
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Text Label 12050 2550 0 50 ~ 0
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LVDS0_7_N
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Text Label 12050 2650 0 50 ~ 0
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LVDS1_0_P
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Text Label 12050 2750 0 50 ~ 0
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LVDS1_0_N
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Text Label 12050 2850 0 50 ~ 0
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LVDS1_1_P
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Text Label 12050 2950 0 50 ~ 0
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LVDS1_1_N
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Text Label 12050 3050 0 50 ~ 0
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LVDS1_2_P
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Text Label 12050 3150 0 50 ~ 0
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LVDS1_2_N
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Text Label 12050 3250 0 50 ~ 0
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LVDS1_3_P
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Text Label 12050 3350 0 50 ~ 0
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LVDS1_3_N
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Text Label 12050 3450 0 50 ~ 0
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LVDS1_4_P
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Text Label 12050 3550 0 50 ~ 0
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LVDS1_4_N
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Text Label 12050 3650 0 50 ~ 0
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LVDS1_5_P
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Text Label 12050 3750 0 50 ~ 0
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LVDS1_5_N
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Text Label 12050 3850 0 50 ~ 0
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LVDS1_6_P
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Text Label 12050 3950 0 50 ~ 0
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LVDS1_6_N
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Text Label 12050 4050 0 50 ~ 0
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LVDS1_7_P
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Text Label 12050 4150 0 50 ~ 0
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LVDS1_7_N
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Text Label 12050 4250 0 50 ~ 0
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LVDS2_0_P
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Text Label 12050 4350 0 50 ~ 0
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LVDS2_0_N
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Text Label 12050 4450 0 50 ~ 0
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LVDS2_1_P
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Text Label 12050 4550 0 50 ~ 0
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LVDS2_1_N
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Text Label 12050 4650 0 50 ~ 0
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LVDS2_2_P
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Text Label 12050 4750 0 50 ~ 0
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LVDS2_2_N
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Text Label 12050 4850 0 50 ~ 0
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LVDS2_3_P
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Text Label 12050 4950 0 50 ~ 0
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LVDS2_3_N
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Text Label 12050 5050 0 50 ~ 0
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LVDS2_4_P
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Text Label 12050 5150 0 50 ~ 0
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LVDS2_4_N
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Text Label 12050 5250 0 50 ~ 0
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LVDS2_5_P
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Text Label 12050 5350 0 50 ~ 0
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LVDS2_5_N
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Text Label 12050 5450 0 50 ~ 0
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LVDS2_6_P
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Text Label 12050 5550 0 50 ~ 0
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LVDS2_6_N
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Text Label 12050 5650 0 50 ~ 0
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LVDS2_7_P
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Text Label 12050 5750 0 50 ~ 0
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LVDS2_7_N
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Text Label 12050 5850 0 50 ~ 0
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LVDS3_1_P
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Text Label 12050 5950 0 50 ~ 0
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LVDS3_1_N
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Text Label 12050 6050 0 50 ~ 0
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LVDS3_2_P
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Text Label 12050 6150 0 50 ~ 0
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LVDS3_2_N
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NoConn ~ 3750 4800
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NoConn ~ 3750 4900
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NoConn ~ 3750 5000
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NoConn ~ 3750 5100
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NoConn ~ 3750 5200
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NoConn ~ 3750 5300
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NoConn ~ 3750 5400
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NoConn ~ 3750 5500
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NoConn ~ 3750 5600
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NoConn ~ 3750 5700
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NoConn ~ 3750 5800
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NoConn ~ 3750 5900
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@ -2746,9 +2639,9 @@ Wire Wire Line
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5850 4400 5750 4400
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Wire Wire Line
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5750 5000 5850 5000
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Text Label 3900 4700 1 50 ~ 0
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Text Label 11000 6600 0 50 ~ 0
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FPGA_KEY
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Text Label 11100 6750 0 50 ~ 0
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FPGA_LED
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Text HLabel 1850 2600 2 50 Input ~ 0
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FPGA_FSMC_A2
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@ -2766,4 +2659,48 @@ Wire Wire Line
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1850 2000 1800 2000
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Text HLabel 1850 2000 2 50 Input ~ 0
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FPGA_FSMC_A7
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NoConn ~ 1800 1100
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NoConn ~ 1800 1400
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NoConn ~ 1800 1900
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NoConn ~ 1800 2100
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NoConn ~ 1800 2800
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NoConn ~ 1800 3000
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NoConn ~ 1800 3100
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NoConn ~ 1800 3300
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NoConn ~ 1800 3500
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NoConn ~ 1800 3700
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NoConn ~ 1800 4300
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NoConn ~ 1800 4400
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NoConn ~ 1800 4600
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NoConn ~ 1800 4900
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NoConn ~ 1800 5200
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NoConn ~ 1800 5400
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NoConn ~ 1800 5500
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NoConn ~ 1800 5700
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NoConn ~ 1800 5800
|
||||
NoConn ~ 1800 5900
|
||||
NoConn ~ 3750 4600
|
||||
NoConn ~ 3750 4500
|
||||
NoConn ~ 3750 4400
|
||||
NoConn ~ 3750 4200
|
||||
NoConn ~ 3750 4100
|
||||
NoConn ~ 3750 4000
|
||||
NoConn ~ 3750 3800
|
||||
NoConn ~ 3750 3600
|
||||
NoConn ~ 3750 3500
|
||||
NoConn ~ 3750 3300
|
||||
NoConn ~ 3750 3200
|
||||
NoConn ~ 3750 3100
|
||||
NoConn ~ 3750 2700
|
||||
NoConn ~ 3750 2600
|
||||
NoConn ~ 3750 2400
|
||||
NoConn ~ 3750 2200
|
||||
NoConn ~ 3750 2000
|
||||
NoConn ~ 3750 1900
|
||||
NoConn ~ 3750 1600
|
||||
NoConn ~ 3750 1500
|
||||
NoConn ~ 3750 1400
|
||||
NoConn ~ 3750 1100
|
||||
NoConn ~ 3750 1000
|
||||
NoConn ~ 3750 900
|
||||
$EndSCHEMATC
|
||||
|
|
|
|||
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Reference in New Issue