From 45940c1ac85977841fb4dcda36e3a7046c5d99b8 Mon Sep 17 00:00:00 2001 From: Jack-Zheng Date: Fri, 18 Jun 2021 16:13:42 +0800 Subject: [PATCH] all: finish routing --- CurrentSenser.sch | 12 +- Ethernet.sch | 2 +- FPGA.sch | 2 +- HighSpeedADC.sch | 6 +- LVDS.sch => LVDS&IO.sch | 303 +++++++++- MCU.sch | 127 +++- Power.sch | 2 +- TestAutomation.sch | 1246 ++++++++++++++++++++++++++++----------- 8 files changed, 1334 insertions(+), 366 deletions(-) rename LVDS.sch => LVDS&IO.sch (69%) diff --git a/CurrentSenser.sch b/CurrentSenser.sch index 3ab3cc3..516538e 100644 --- a/CurrentSenser.sch +++ b/CurrentSenser.sch @@ -425,16 +425,11 @@ U 1 1 61786D79 P 5750 5400 F 0 "J8" H 5830 5392 50 0000 L CNN F 1 "12V_OUT" H 5830 5301 50 0000 L CNN -F 2 "" H 5750 5400 50 0001 C CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" H 5750 5400 50 0001 C CNN F 3 "~" H 5750 5400 50 0001 C CNN 1 5750 5400 1 0 0 -1 $EndComp -Text HLabel 5350 5400 0 50 Input ~ 0 -12V_OUT -Wire Wire Line - 5350 5400 5450 5400 -Connection ~ 5450 5400 $Comp L Device:R R131 U 1 1 628EB7FE @@ -679,4 +674,9 @@ F 3 "" H 8550 5100 50 0001 C CNN $EndComp Wire Wire Line 8550 4950 8550 5100 +Wire Wire Line + 5350 5400 5450 5400 +Connection ~ 5450 5400 +Text GLabel 5350 5400 0 50 Input ~ 0 ++12V_OUT $EndSCHEMATC diff --git a/Ethernet.sch b/Ethernet.sch index 2b381c7..dbb3993 100644 --- a/Ethernet.sch +++ b/Ethernet.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 3 8 +Sheet 7 8 Title "" Date "" Rev "" diff --git a/FPGA.sch b/FPGA.sch index 32b5b79..37a1c88 100644 --- a/FPGA.sch +++ b/FPGA.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 7 8 +Sheet 3 8 Title "" Date "" Rev "" diff --git a/HighSpeedADC.sch b/HighSpeedADC.sch index ecfa8ac..9f622a9 100644 --- a/HighSpeedADC.sch +++ b/HighSpeedADC.sch @@ -432,7 +432,7 @@ AR Path="/60CB9D41/60D1901A" Ref="J?" Part="1" AR Path="/60FB17F2/60D1901A" Ref="J3" Part="1" F 0 "J3" H 2700 3725 50 0000 L CNN F 1 "Conn_Coaxial" H 2700 3634 50 0000 L CNN -F 2 "" H 2600 3750 50 0001 C CNN +F 2 "Connector_Coaxial:SMA_Molex_73251-2200_Horizontal" H 2600 3750 50 0001 C CNN F 3 " ~" H 2600 3750 50 0001 C CNN 1 2600 3750 -1 0 0 -1 @@ -442,8 +442,8 @@ L Connector_Generic:Conn_01x02 J4 U 1 1 60D22419 P 2600 4250 F 0 "J4" H 2518 3925 50 0000 C CNN -F 1 "Conn_01x02" H 2518 4016 50 0000 C CNN -F 2 "" H 2600 4250 50 0001 C CNN +F 1 "HSADC" H 2518 4016 50 0000 C CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" H 2600 4250 50 0001 C CNN F 3 "~" H 2600 4250 50 0001 C CNN 1 2600 4250 -1 0 0 1 diff --git a/LVDS.sch b/LVDS&IO.sch similarity index 69% rename from LVDS.sch rename to LVDS&IO.sch index d89376a..e3d6c04 100644 --- a/LVDS.sch +++ b/LVDS&IO.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 8 8 +Sheet 4 8 Title "" Date "" Rev "" @@ -19,7 +19,7 @@ U 1 1 6182545F P 3500 3400 F 0 "J9" H 3580 3392 50 0000 L CNN F 1 "EEM0" H 3580 3301 50 0000 L CNN -F 2 "" H 3500 3400 50 0001 C CNN +F 2 "Connector_IDC:IDC-Header_2x15_P2.54mm_Vertical" H 3500 3400 50 0001 C CNN F 3 "~" H 3500 3400 50 0001 C CNN 1 3500 3400 1 0 0 -1 @@ -159,8 +159,6 @@ Text HLabel 3150 4500 0 50 Input ~ 0 EEM0_IIC_SDA Text HLabel 3150 4600 0 50 Input ~ 0 EEM0_IIC_SCL -Text Label 3050 4750 2 50 ~ 0 -EEM_12V Wire Wire Line 2650 2000 3300 2000 Wire Wire Line @@ -236,7 +234,7 @@ U 1 1 61B237C0 P 5500 3400 F 0 "J10" H 5580 3392 50 0000 L CNN F 1 "EEM1" H 5580 3301 50 0000 L CNN -F 2 "" H 5500 3400 50 0001 C CNN +F 2 "Connector_IDC:IDC-Header_2x15_P2.54mm_Vertical" H 5500 3400 50 0001 C CNN F 3 "~" H 5500 3400 50 0001 C CNN 1 5500 3400 1 0 0 -1 @@ -376,8 +374,6 @@ Text HLabel 5150 4500 0 50 Input ~ 0 EEM1_IIC_SDA Text HLabel 5150 4600 0 50 Input ~ 0 EEM1_IIC_SCL -Text Label 5050 4750 2 50 ~ 0 -EEM_12V Wire Wire Line 4650 2000 5300 2000 Wire Wire Line @@ -455,7 +451,7 @@ AR Path="/60CB9D41/61B2D756" Ref="J11" Part="1" AR Path="/60FB17F2/61B2D756" Ref="J?" Part="1" F 0 "J11" H 7480 3392 50 0000 L CNN F 1 "EEM2" H 7480 3301 50 0000 L CNN -F 2 "" H 7400 3400 50 0001 C CNN +F 2 "Connector_IDC:IDC-Header_2x15_P2.54mm_Vertical" H 7400 3400 50 0001 C CNN F 3 "~" H 7400 3400 50 0001 C CNN 1 7400 3400 1 0 0 -1 @@ -611,8 +607,6 @@ Text HLabel 7050 4300 0 50 Input ~ 0 EEM2_7_N Text HLabel 7050 4500 0 50 Input ~ 0 EEM2_IIC_SDA -Text Label 6950 4750 2 50 ~ 0 -EEM_12V Wire Wire Line 6550 2000 7200 2000 Wire Wire Line @@ -684,4 +678,293 @@ Wire Wire Line 7200 4900 7050 4900 Text HLabel 7050 4600 0 50 Input ~ 0 EEM2_IIC_SCL +$Comp +L Connector_Generic:Conn_02x16_Counter_Clockwise J12 +U 1 1 62B89A4D +P 9350 2750 +F 0 "J12" H 9400 3667 50 0000 C CNN +F 1 "FPGA_IO" H 9400 3576 50 0000 C CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_2x16_P2.54mm_Vertical" H 9350 2750 50 0001 C CNN +F 3 "~" H 9350 2750 50 0001 C CNN + 1 9350 2750 + 1 0 0 -1 +$EndComp +Text GLabel 3050 4750 0 50 Input ~ 0 ++12V_OUT +Text GLabel 5050 4750 0 50 Input ~ 0 ++12V_OUT +Text GLabel 6950 4750 0 50 Input ~ 0 ++12V_OUT +Text HLabel 8950 2050 0 50 Input ~ 0 +FPGA_IO0 +Text HLabel 9850 2150 2 50 Input ~ 0 +FPGA_IO1 +Text HLabel 8950 2250 0 50 Input ~ 0 +FPGA_IO2 +Text HLabel 9850 2350 2 50 Input ~ 0 +FPGA_IO3 +Text HLabel 8950 2450 0 50 Input ~ 0 +FPGA_IO4 +Text HLabel 9850 2550 2 50 Input ~ 0 +FPGA_IO5 +Text HLabel 8950 2650 0 50 Input ~ 0 +FPGA_IO6 +Text HLabel 9850 2750 2 50 Input ~ 0 +FPGA_IO7 +Text HLabel 8950 2850 0 50 Input ~ 0 +FPGA_IO8 +Text HLabel 9850 2950 2 50 Input ~ 0 +FPGA_IO9 +Text HLabel 8950 3050 0 50 Input ~ 0 +FPGA_IO10 +Text HLabel 9850 3150 2 50 Input ~ 0 +FPGA_IO11 +Text HLabel 8950 3250 0 50 Input ~ 0 +FPGA_IO12 +Text HLabel 9850 3350 2 50 Input ~ 0 +FPGA_IO13 +Text HLabel 8950 3450 0 50 Input ~ 0 +FPGA_IO14 +Text HLabel 9850 3550 2 50 Input ~ 0 +FPGA_IO15 +$Comp +L power:GND #PWR0129 +U 1 1 62C1F019 +P 8800 2150 +F 0 "#PWR0129" H 8800 1900 50 0001 C CNN +F 1 "GND" V 8805 2022 50 0000 R CNN +F 2 "" H 8800 2150 50 0001 C CNN +F 3 "" H 8800 2150 50 0001 C CNN + 1 8800 2150 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0130 +U 1 1 62C1FF0B +P 8800 2350 +F 0 "#PWR0130" H 8800 2100 50 0001 C CNN +F 1 "GND" V 8805 2222 50 0000 R CNN +F 2 "" H 8800 2350 50 0001 C CNN +F 3 "" H 8800 2350 50 0001 C CNN + 1 8800 2350 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0131 +U 1 1 62C2399D +P 8800 2550 +F 0 "#PWR0131" H 8800 2300 50 0001 C CNN +F 1 "GND" V 8805 2422 50 0000 R CNN +F 2 "" H 8800 2550 50 0001 C CNN +F 3 "" H 8800 2550 50 0001 C CNN + 1 8800 2550 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0132 +U 1 1 62C273A8 +P 8800 2750 +F 0 "#PWR0132" H 8800 2500 50 0001 C CNN +F 1 "GND" V 8805 2622 50 0000 R CNN +F 2 "" H 8800 2750 50 0001 C CNN +F 3 "" H 8800 2750 50 0001 C CNN + 1 8800 2750 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0133 +U 1 1 62C2AE1D +P 8800 2950 +F 0 "#PWR0133" H 8800 2700 50 0001 C CNN +F 1 "GND" V 8805 2822 50 0000 R CNN +F 2 "" H 8800 2950 50 0001 C CNN +F 3 "" H 8800 2950 50 0001 C CNN + 1 8800 2950 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0134 +U 1 1 62C2E883 +P 8800 3150 +F 0 "#PWR0134" H 8800 2900 50 0001 C CNN +F 1 "GND" V 8805 3022 50 0000 R CNN +F 2 "" H 8800 3150 50 0001 C CNN +F 3 "" H 8800 3150 50 0001 C CNN + 1 8800 3150 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0135 +U 1 1 62C3231D +P 8800 3350 +F 0 "#PWR0135" H 8800 3100 50 0001 C CNN +F 1 "GND" V 8805 3222 50 0000 R CNN +F 2 "" H 8800 3350 50 0001 C CNN +F 3 "" H 8800 3350 50 0001 C CNN + 1 8800 3350 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0136 +U 1 1 62C35DE2 +P 8800 3550 +F 0 "#PWR0136" H 8800 3300 50 0001 C CNN +F 1 "GND" V 8805 3422 50 0000 R CNN +F 2 "" H 8800 3550 50 0001 C CNN +F 3 "" H 8800 3550 50 0001 C CNN + 1 8800 3550 + 0 1 1 0 +$EndComp +$Comp +L power:+3V3 #PWR0137 +U 1 1 62C41A06 +P 9900 2050 +F 0 "#PWR0137" H 9900 1900 50 0001 C CNN +F 1 "+3V3" V 9915 2178 50 0000 L CNN +F 2 "" H 9900 2050 50 0001 C CNN +F 3 "" H 9900 2050 50 0001 C CNN + 1 9900 2050 + 0 1 1 0 +$EndComp +$Comp +L power:+3V3 #PWR0138 +U 1 1 62C42942 +P 9900 2250 +F 0 "#PWR0138" H 9900 2100 50 0001 C CNN +F 1 "+3V3" V 9915 2378 50 0000 L CNN +F 2 "" H 9900 2250 50 0001 C CNN +F 3 "" H 9900 2250 50 0001 C CNN + 1 9900 2250 + 0 1 1 0 +$EndComp +$Comp +L power:+3V3 #PWR0139 +U 1 1 62C464FC +P 9900 2450 +F 0 "#PWR0139" H 9900 2300 50 0001 C CNN +F 1 "+3V3" V 9915 2578 50 0000 L CNN +F 2 "" H 9900 2450 50 0001 C CNN +F 3 "" H 9900 2450 50 0001 C CNN + 1 9900 2450 + 0 1 1 0 +$EndComp +$Comp +L power:+3V3 #PWR0140 +U 1 1 62C4A0DB +P 9900 2650 +F 0 "#PWR0140" H 9900 2500 50 0001 C CNN +F 1 "+3V3" V 9915 2778 50 0000 L CNN +F 2 "" H 9900 2650 50 0001 C CNN +F 3 "" H 9900 2650 50 0001 C CNN + 1 9900 2650 + 0 1 1 0 +$EndComp +$Comp +L power:+3V3 #PWR0141 +U 1 1 62C4DBD5 +P 9900 2850 +F 0 "#PWR0141" H 9900 2700 50 0001 C CNN +F 1 "+3V3" V 9915 2978 50 0000 L CNN +F 2 "" H 9900 2850 50 0001 C CNN +F 3 "" H 9900 2850 50 0001 C CNN + 1 9900 2850 + 0 1 1 0 +$EndComp +$Comp +L power:+3V3 #PWR0142 +U 1 1 62C516A9 +P 9900 3050 +F 0 "#PWR0142" H 9900 2900 50 0001 C CNN +F 1 "+3V3" V 9915 3178 50 0000 L CNN +F 2 "" H 9900 3050 50 0001 C CNN +F 3 "" H 9900 3050 50 0001 C CNN + 1 9900 3050 + 0 1 1 0 +$EndComp +$Comp +L power:+3V3 #PWR0143 +U 1 1 62C552AF +P 9900 3250 +F 0 "#PWR0143" H 9900 3100 50 0001 C CNN +F 1 "+3V3" V 9915 3378 50 0000 L CNN +F 2 "" H 9900 3250 50 0001 C CNN +F 3 "" H 9900 3250 50 0001 C CNN + 1 9900 3250 + 0 1 1 0 +$EndComp +$Comp +L power:+3V3 #PWR0144 +U 1 1 62C58DBB +P 9900 3450 +F 0 "#PWR0144" H 9900 3300 50 0001 C CNN +F 1 "+3V3" V 9915 3578 50 0000 L CNN +F 2 "" H 9900 3450 50 0001 C CNN +F 3 "" H 9900 3450 50 0001 C CNN + 1 9900 3450 + 0 1 1 0 +$EndComp +Wire Wire Line + 9900 2050 9650 2050 +Wire Wire Line + 9650 2150 9850 2150 +Wire Wire Line + 9900 2250 9650 2250 +Wire Wire Line + 9650 2350 9850 2350 +Wire Wire Line + 9900 2450 9650 2450 +Wire Wire Line + 9650 2550 9850 2550 +Wire Wire Line + 9900 2650 9650 2650 +Wire Wire Line + 9650 2750 9850 2750 +Wire Wire Line + 9900 2850 9650 2850 +Wire Wire Line + 9650 2950 9850 2950 +Wire Wire Line + 9900 3050 9650 3050 +Wire Wire Line + 9650 3150 9850 3150 +Wire Wire Line + 9900 3250 9650 3250 +Wire Wire Line + 9650 3350 9850 3350 +Wire Wire Line + 9900 3450 9650 3450 +Wire Wire Line + 9650 3550 9850 3550 +Wire Wire Line + 8950 2050 9150 2050 +Wire Wire Line + 8800 2150 9150 2150 +Wire Wire Line + 8950 2250 9150 2250 +Wire Wire Line + 8800 2350 9150 2350 +Wire Wire Line + 8950 2450 9150 2450 +Wire Wire Line + 8800 2550 9150 2550 +Wire Wire Line + 8950 2650 9150 2650 +Wire Wire Line + 8800 2750 9150 2750 +Wire Wire Line + 8950 2850 9150 2850 +Wire Wire Line + 8800 2950 9150 2950 +Wire Wire Line + 8950 3050 9150 3050 +Wire Wire Line + 8800 3150 9150 3150 +Wire Wire Line + 8950 3250 9150 3250 +Wire Wire Line + 8800 3350 9150 3350 +Wire Wire Line + 8950 3450 9150 3450 +Wire Wire Line + 8800 3550 9150 3550 $EndSCHEMATC diff --git a/MCU.sch b/MCU.sch index dabb23b..3a3c2e3 100644 --- a/MCU.sch +++ b/MCU.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 6 8 +Sheet 8 8 Title "" Date "" Rev "" @@ -160,8 +160,6 @@ F 3 "" H 2000 1750 50 0001 C CNN 1 2000 1750 0 -1 -1 0 $EndComp -Text GLabel 2100 1400 0 50 Input ~ 0 -CPU_RESET $Comp L Device:R R16 U 1 1 618E4ED2 @@ -740,7 +738,7 @@ U 1 1 6103F22E P 8200 5050 F 0 "J6" H 8250 5667 50 0000 C CNN F 1 "Analog" H 8250 5576 50 0000 C CNN -F 2 "" H 8200 5050 50 0001 C CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_2x10_P2.54mm_Vertical" H 8200 5050 50 0001 C CNN F 3 "~" H 8200 5050 50 0001 C CNN 1 8200 5050 1 0 0 -1 @@ -1027,7 +1025,7 @@ U 1 1 6142A963 P 8200 3500 F 0 "J5" H 8250 4217 50 0000 C CNN F 1 "IO" H 8250 4126 50 0000 C CNN -F 2 "" H 8200 3500 50 0001 C CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_2x12_P2.54mm_Vertical" H 8200 3500 50 0001 C CNN F 3 "~" H 8200 3500 50 0001 C CNN 1 8200 3500 1 0 0 -1 @@ -1057,12 +1055,12 @@ $EndComp $Comp L power:GND #PWR0126 U 1 1 6210B2EE -P 7100 5250 -F 0 "#PWR0126" H 7100 5000 50 0001 C CNN -F 1 "GND" H 7105 5077 50 0000 C CNN -F 2 "" H 7100 5250 50 0001 C CNN -F 3 "" H 7100 5250 50 0001 C CNN - 1 7100 5250 +P 7100 5400 +F 0 "#PWR0126" H 7100 5150 50 0001 C CNN +F 1 "GND" H 7105 5227 50 0000 C CNN +F 2 "" H 7100 5400 50 0001 C CNN +F 3 "" H 7100 5400 50 0001 C CNN + 1 7100 5400 1 0 0 -1 $EndComp Wire Wire Line @@ -1073,4 +1071,111 @@ Wire Wire Line 6700 5150 6600 5150 Wire Wire Line 6300 5150 5000 5150 +$Comp +L Switch:SW_Push SW1 +U 1 1 62CA6A93 +P 3100 1100 +F 0 "SW1" H 3100 1385 50 0000 C CNN +F 1 "SW_RESET" H 3100 1294 50 0000 C CNN +F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 3100 1300 50 0001 C CNN +F 3 "~" H 3100 1300 50 0001 C CNN + 1 3100 1100 + 1 0 0 -1 +$EndComp +$Comp +L Switch:SW_Push SW2 +U 1 1 62CCB907 +P 6100 5250 +F 0 "SW2" H 6100 5535 50 0000 C CNN +F 1 "SW_USER" H 6100 5444 50 0000 C CNN +F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 6100 5450 50 0001 C CNN +F 3 "~" H 6100 5450 50 0001 C CNN + 1 6100 5250 + -1 0 0 1 +$EndComp +Text HLabel 2100 1400 0 50 Input ~ 0 +CPU_RESET +$Comp +L power:GND #PWR0145 +U 1 1 62D1B098 +P 3450 1250 +F 0 "#PWR0145" H 3450 1000 50 0001 C CNN +F 1 "GND" H 3455 1077 50 0000 C CNN +F 2 "" H 3450 1250 50 0001 C CNN +F 3 "" H 3450 1250 50 0001 C CNN + 1 3450 1250 + 0 -1 -1 0 +$EndComp +$Comp +L Device:C C52 +U 1 1 62D1BE27 +P 3100 1400 +F 0 "C52" V 2848 1400 50 0000 C CNN +F 1 "0.1uF" V 2939 1400 50 0000 C CNN +F 2 "Capacitor_SMD:C_0402_1005Metric" H 3138 1250 50 0001 C CNN +F 3 "~" H 3100 1400 50 0001 C CNN + 1 3100 1400 + 0 1 1 0 +$EndComp +Wire Wire Line + 2950 1400 2850 1400 +Connection ~ 2850 1400 +Wire Wire Line + 2900 1100 2850 1100 +Wire Wire Line + 2850 1100 2850 1400 +Wire Wire Line + 3250 1400 3350 1400 +Wire Wire Line + 3350 1400 3350 1250 +Wire Wire Line + 3350 1100 3300 1100 +Wire Wire Line + 3450 1250 3350 1250 +Connection ~ 3350 1250 +Wire Wire Line + 3350 1250 3350 1100 +Wire Wire Line + 5900 5250 5000 5250 +Wire Wire Line + 6300 5250 7100 5250 +Wire Wire Line + 7100 5400 7100 5250 +Connection ~ 7100 5250 +Text HLabel 5400 2850 2 50 Input ~ 0 +CPU_ENC_INT +Text HLabel 5400 2550 2 50 Input ~ 0 +CPU_12V_SW +Text HLabel 5400 3650 2 50 Input ~ 0 +CPU_POE_AT_EVENT +Text HLabel 5400 3550 2 50 Input ~ 0 +CPU_POE_SRC_STATUS +Wire Wire Line + 5400 6450 5000 6450 +Wire Wire Line + 5000 6550 5400 6550 +Wire Wire Line + 5400 6650 5000 6650 +Wire Wire Line + 5400 3550 5000 3550 +Wire Wire Line + 5400 2550 5000 2550 +Wire Wire Line + 5000 2850 5400 2850 +Wire Wire Line + 5000 3650 5400 3650 +Text HLabel 5400 6350 2 50 Input ~ 0 +CPU_FPGA_CSBSEL0 +Text HLabel 5400 6450 2 50 Input ~ 0 +CPU_FPGA_CSBSEL1 +Text HLabel 5400 6550 2 50 Input ~ 0 +CPU_FPGA_CDONE +Text HLabel 5400 6650 2 50 Input ~ 0 +CPU_FPGA_CRESET +Wire Wire Line + 5000 6350 5400 6350 +NoConn ~ 5000 5350 +NoConn ~ 5000 5450 +NoConn ~ 3000 5350 +NoConn ~ 5000 4050 $EndSCHEMATC diff --git a/Power.sch b/Power.sch index 7e8e31e..645f21c 100644 --- a/Power.sch +++ b/Power.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 4 8 +Sheet 6 8 Title "" Date "" Rev "" diff --git a/TestAutomation.sch b/TestAutomation.sch index 77cfb22..2a39c56 100644 --- a/TestAutomation.sch +++ b/TestAutomation.sch @@ -14,349 +14,929 @@ Comment3 "" Comment4 "" $EndDescr $Sheet -S 9150 5100 600 1200 +S 9650 4650 600 1050 U 60FB17F2 F0 "HighSpeedADC" 50 F1 "HighSpeedADC.sch" 50 -F2 "ADC_CLK" I L 9150 5350 50 -F3 "ADC_DATA1" I L 9150 5500 50 -F4 "ADC_DATA2" I L 9150 5600 50 -F5 "ADC_DATA3" I L 9150 5700 50 -F6 "ADC_DATA4" I L 9150 5800 50 -F7 "ADC_DATA5" I L 9150 5900 50 -F8 "ADC_DATA6" I L 9150 6000 50 -F9 "ADC_DATA7" I L 9150 6100 50 -F10 "ADC_DATA8" I L 9150 6200 50 -F11 "ADC_IN" I L 9150 5200 50 +F2 "ADC_CLK" I L 9650 5600 50 +F3 "ADC_DATA1" I L 9650 4750 50 +F4 "ADC_DATA2" I L 9650 4850 50 +F5 "ADC_DATA3" I L 9650 4950 50 +F6 "ADC_DATA4" I L 9650 5050 50 +F7 "ADC_DATA5" I L 9650 5150 50 +F8 "ADC_DATA6" I L 9650 5250 50 +F9 "ADC_DATA7" I L 9650 5350 50 +F10 "ADC_DATA8" I L 9650 5450 50 $EndSheet +NoConn ~ 1650 750 +NoConn ~ 1650 850 +NoConn ~ 1650 1050 +NoConn ~ 1650 1150 +NoConn ~ 1650 1250 +NoConn ~ 1650 1350 +NoConn ~ 1650 1450 +NoConn ~ 1650 1550 +NoConn ~ 1650 1650 +NoConn ~ 1650 1750 +NoConn ~ 1650 2200 +NoConn ~ 1650 2300 +NoConn ~ 1650 4450 $Sheet -S 2900 5300 650 1000 -U 60E4702B -F0 "Ethernet" 50 -F1 "Ethernet.sch" 50 -F2 "POE_VC+" I L 2900 6200 50 -F3 "POE_VC-" I L 2900 6100 50 -F4 "ENC_SPI_SCK" I L 2900 5900 50 -F5 "ENC_SPI_MOSI" I L 2900 5800 50 -F6 "ENC_SPI_MISO" I L 2900 5700 50 -F7 "ENC_INT" I L 2900 5400 50 -F8 "ENC_SPI_CS" I L 2900 5600 50 -$EndSheet -$Sheet -S 1650 5350 750 800 -U 60C2FE2A -F0 "Power" 50 -F1 "Power.sch" 50 -F2 "POE_VC+" I R 2400 5600 50 -F3 "POE_VC-" I R 2400 5500 50 -F4 "POE_AT_EVENT" I L 1650 5800 50 -F5 "POE_SRC_Status" I L 1650 5900 50 -F6 "POE_CPU_RESET" I L 1650 6000 50 -$EndSheet -$Sheet -S 1650 6600 650 450 -U 60E3407A -F0 "CurrentSenser" 50 -F1 "CurrentSenser.sch" 50 -F2 "12V_SW" I L 1650 6700 50 -F3 "12V_CURRENT" I L 1650 6800 50 -F4 "12V_OUT" I L 1650 6950 50 -$EndSheet -Wire Wire Line - 2400 5500 2550 5500 -Wire Wire Line - 2550 5500 2550 6100 -Wire Wire Line - 2550 6100 2900 6100 -Wire Wire Line - 2400 5600 2500 5600 -Wire Wire Line - 2500 5600 2500 6200 -Wire Wire Line - 2500 6200 2900 6200 -NoConn ~ 1800 950 -NoConn ~ 1800 1050 -NoConn ~ 1800 1250 -NoConn ~ 1800 1350 -NoConn ~ 1800 1450 -NoConn ~ 1800 1550 -NoConn ~ 1800 1650 -NoConn ~ 1800 1750 -NoConn ~ 1800 1850 -NoConn ~ 1800 1950 -NoConn ~ 1800 2400 -NoConn ~ 1800 2500 -NoConn ~ 1800 3200 -NoConn ~ 1800 3300 -NoConn ~ 1800 3400 -NoConn ~ 1800 3500 -NoConn ~ 1800 3750 -NoConn ~ 1800 3850 -NoConn ~ 1800 4000 -NoConn ~ 1800 4100 -NoConn ~ 1800 4350 -NoConn ~ 1800 4450 -NoConn ~ 1800 4550 -NoConn ~ 1800 4650 -$Sheet -S 1800 850 1500 3950 -U 60C2FDBB -F0 "MCU" 50 -F1 "MCU.sch" 50 -F2 "CPU_DAC0" I L 1800 950 50 -F3 "CPU_DAC1" I L 1800 1050 50 -F4 "CPU_ADC1" I L 1800 1350 50 -F5 "CPU_ADC2" I L 1800 1450 50 -F6 "CPU_ADC3" I L 1800 1550 50 -F7 "CPU_ADC4" I L 1800 1650 50 -F8 "CPU_ADC0" I L 1800 1250 50 -F9 "CPU_ADC5" I L 1800 1750 50 -F10 "CPU_ADC6" I L 1800 1850 50 -F11 "CPU_ADC7" I L 1800 1950 50 -F12 "CPU_IIC2_SCL" I L 1800 2400 50 -F13 "CPU_IIC2_SDA" I L 1800 2500 50 -F14 "CPU_SPI2_SCK" I L 1800 3200 50 -F15 "CPU_SPI2_MISO" I L 1800 3300 50 -F16 "CPU_SPI2_MOSI" I L 1800 3400 50 -F17 "CPU_SWDIO" I R 3300 4400 50 -F18 "CPU_SWCLK" I R 3300 4500 50 -F19 "CPU_UART1_TX" I L 1800 3750 50 -F20 "CPU_UART1_RX" I L 1800 3850 50 -F21 "CPU_UART4_TX" I L 1800 4000 50 -F22 "CPU_UART4_RX" I L 1800 4100 50 -F23 "CPU_IIC1_SCL" I L 1800 2150 50 -F24 "CPU_IIC1_SDA" I L 1800 2250 50 -F25 "CPU_SPI1_SCK" I L 1800 2700 50 -F26 "CPU_SPI1_MISO" I L 1800 2800 50 -F27 "CPU_SPI1_MOSI" I L 1800 2900 50 -F28 "CPU_SPI2_CS" I L 1800 3500 50 -F29 "CPU_SPI1_CS" I L 1800 3000 50 -F30 "CPU_FSMC_DA0" I R 3300 950 50 -F31 "CPU_FSMC_DA1" I R 3300 1050 50 -F32 "CPU_FSMC_DA2" I R 3300 1150 50 -F33 "CPU_FSMC_DA3" I R 3300 1250 50 -F34 "CPU_FSMC_DA4" I R 3300 1350 50 -F35 "CPU_FSMC_DA5" I R 3300 1450 50 -F36 "CPU_FSMC_DA6" I R 3300 1550 50 -F37 "CPU_FSMC_DA7" I R 3300 1650 50 -F38 "CPU_FSMC_DA8" I R 3300 1750 50 -F39 "CPU_FSMC_DA9" I R 3300 1850 50 -F40 "CPU_FSMC_DA10" I R 3300 1950 50 -F41 "CPU_FSMC_DA11" I R 3300 2050 50 -F42 "CPU_FSMC_DA12" I R 3300 2150 50 -F43 "CPU_FSMC_A16" I R 3300 2550 50 -F44 "CPU_FSMC_A17" I R 3300 2650 50 -F45 "CPU_FSMC_A18" I R 3300 2750 50 -F46 "CPU_FSMC_A19" I R 3300 2850 50 -F47 "CPU_FSMC_A20" I R 3300 2950 50 -F48 "CPU_FSMC_A21" I R 3300 3050 50 -F49 "CPU_FSMC_A22" I R 3300 3150 50 -F50 "CPU_FSMC_A23" I R 3300 3250 50 -F51 "CPU_FSMC_NWE" I R 3300 3400 50 -F52 "CPU_FSMC_NOE" I R 3300 3500 50 -F53 "CPU_FSMC_NE1" I R 3300 3600 50 -F54 "CPU_PWM_CH1" I L 1800 4350 50 -F55 "CPU_PWM_CH2" I L 1800 4450 50 -F56 "CPU_PWM_CH3" I L 1800 4550 50 -F57 "CPU_PWM_CH4" I L 1800 4650 50 -F58 "CPU_FSMC_NBL0" I R 3300 3700 50 -F59 "CPU_FSMC_NBL1" I R 3300 3800 50 -F60 "CPU_FSMC_NL" I R 3300 3900 50 -F61 "CPU_FSMC_CLK" I R 3300 4000 50 -F62 "CPU_FSMC_NWAIT" I R 3300 4100 50 -F63 "CPU_ENC_CS" I L 1800 3100 50 -F64 "CPU_ADC8" I L 1800 1150 50 -F65 "CPU_FSMC_DA13" I R 3300 2250 50 -F66 "CPU_FSMC_DA14" I R 3300 2350 50 -F67 "CPU_FSMC_DA15" I R 3300 2450 50 -$EndSheet -NoConn ~ 3300 4400 -NoConn ~ 3300 4500 -$Sheet -S 4650 850 1500 6450 +S 4450 650 1500 6450 U 60C0E996 F0 "FPGA" 50 F1 "FPGA.sch" 50 -F2 "FPGA_EEM0_0_P" I R 6150 950 50 -F3 "FPGA_EEM0_0_N" I R 6150 1050 50 -F4 "FPGA_EEM0_7_P" I R 6150 2350 50 -F5 "FPGA_EEM0_7_N" I R 6150 2450 50 -F6 "FPGA_EEM0_6_P" I R 6150 2150 50 -F7 "FPGA_EEM0_6_N" I R 6150 2250 50 -F8 "FPGA_EEM0_5_P" I R 6150 1950 50 -F9 "FPGA_EEM0_5_N" I R 6150 2050 50 -F10 "FPGA_EEM0_4_P" I R 6150 1750 50 -F11 "FPGA_EEM0_4_N" I R 6150 1850 50 -F12 "FPGA_EEM0_3_P" I R 6150 1550 50 -F13 "FPGA_EEM0_3_N" I R 6150 1650 50 -F14 "FPGA_EEM0_2_P" I R 6150 1350 50 -F15 "FPGA_EEM0_2_N" I R 6150 1450 50 -F16 "FPGA_EEM0_1_P" I R 6150 1150 50 -F17 "FPGA_EEM0_1_N" I R 6150 1250 50 -F18 "FPGA_EEM1_0_P" I R 6150 2750 50 -F19 "FPGA_EEM1_0_N" I R 6150 2850 50 -F20 "FPGA_EEM1_7_P" I R 6150 4150 50 -F21 "FPGA_EEM1_7_N" I R 6150 4250 50 -F22 "FPGA_EEM1_6_P" I R 6150 3950 50 -F23 "FPGA_EEM1_6_N" I R 6150 4050 50 -F24 "FPGA_EEM1_5_P" I R 6150 3750 50 -F25 "FPGA_EEM1_5_N" I R 6150 3850 50 -F26 "FPGA_EEM1_4_P" I R 6150 3550 50 -F27 "FPGA_EEM1_4_N" I R 6150 3650 50 -F28 "FPGA_EEM1_3_P" I R 6150 3350 50 -F29 "FPGA_EEM1_3_N" I R 6150 3450 50 -F30 "FPGA_EEM1_2_P" I R 6150 3150 50 -F31 "FPGA_EEM1_2_N" I R 6150 3250 50 -F32 "FPGA_EEM1_1_P" I R 6150 2950 50 -F33 "FPGA_EEM1_1_N" I R 6150 3050 50 -F34 "FPGA_EEM2_0_P" I R 6150 4550 50 -F35 "FPGA_EEM2_0_N" I R 6150 4650 50 -F36 "FPGA_EEM2_7_P" I R 6150 5950 50 -F37 "FPGA_EEM2_7_N" I R 6150 6050 50 -F38 "FPGA_EEM2_6_P" I R 6150 5750 50 -F39 "FPGA_EEM2_6_N" I R 6150 5850 50 -F40 "FPGA_EEM2_5_P" I R 6150 5550 50 -F41 "FPGA_EEM2_5_N" I R 6150 5650 50 -F42 "FPGA_EEM2_4_P" I R 6150 5350 50 -F43 "FPGA_EEM2_4_N" I R 6150 5450 50 -F44 "FPGA_EEM2_3_P" I R 6150 5150 50 -F45 "FPGA_EEM2_3_N" I R 6150 5250 50 -F46 "FPGA_EEM2_2_P" I R 6150 4950 50 -F47 "FPGA_EEM2_2_N" I R 6150 5050 50 -F48 "FPGA_EEM2_1_P" I R 6150 4750 50 -F49 "FPGA_EEM2_1_N" I R 6150 4850 50 -F50 "FPGA_FSMC_A0" I L 4650 2550 50 -F51 "FPGA_FSMC_A1" I L 4650 2650 50 -F52 "FPGA_FSMC_A2" I L 4650 2750 50 -F53 "FPGA_FSMC_A3" I L 4650 2850 50 -F54 "FPGA_FSMC_A4" I L 4650 2950 50 -F55 "FPGA_FSMC_A5" I L 4650 3050 50 -F56 "FPGA_FSMC_A6" I L 4650 3150 50 -F57 "FPGA_FSMC_A7" I L 4650 3250 50 -F58 "FPGA_FSMC_D0" I L 4650 950 50 -F59 "FPGA_FSMC_D1" I L 4650 1050 50 -F60 "FPGA_FSMC_D2" I L 4650 1150 50 -F61 "FPGA_FSMC_D3" I L 4650 1250 50 -F62 "FPGA_FSMC_D4" I L 4650 1350 50 -F63 "FPGA_FSMC_D5" I L 4650 1450 50 -F64 "FPGA_FSMC_D6" I L 4650 1550 50 -F65 "FPGA_FSMC_D7" I L 4650 1650 50 -F66 "FPGA_FSMC_D8" I L 4650 1750 50 -F67 "FPGA_FSMC_D9" I L 4650 1850 50 -F68 "FPGA_FSMC_D10" I L 4650 1950 50 -F69 "FPGA_FSMC_D11" I L 4650 2050 50 -F70 "FPGA_FSMC_D12" I L 4650 2150 50 -F71 "FPGA_FSMC_D13" I L 4650 2250 50 -F72 "FPGA_FSMC_D14" I L 4650 2350 50 -F73 "FPGA_FSMC_D15" I L 4650 2450 50 -F74 "FPGA_CSBSEL0" I L 4650 4250 50 -F75 "FPGA_CSBSEL1" I L 4650 4350 50 -F76 "FPGA_SPI_SDO" I L 4650 4450 50 -F77 "FPGA_SPI_SDI" I L 4650 4550 50 -F78 "FPGA_SPI_SS" I L 4650 4650 50 -F79 "FPGA_SPI_SCK" I L 4650 4750 50 -F80 "FPGA_CDONE" I L 4650 4850 50 -F81 "FPGA_CRESET" I L 4650 4950 50 -F82 "FPGA_ADC_D0" I R 6150 6400 50 -F83 "FPGA_ADC_D1" I R 6150 6500 50 -F84 "FPGA_ADC_D2" I R 6150 6600 50 -F85 "FPGA_ADC_D3" I R 6150 6700 50 -F86 "FPGA_ADC_D4" I R 6150 6800 50 -F87 "FPGA_ADC_D5" I R 6150 6900 50 -F88 "FPGA_ADC_D6" I R 6150 7000 50 -F89 "FPGA_ADC_D7" I R 6150 7100 50 -F90 "FPGA_ADC_CLK" I R 6150 7200 50 -F91 "FPGA_FSMC_NWE" I L 4650 3400 50 -F92 "FPGA_FSMC_NOE" I L 4650 3500 50 -F93 "FPGA_FSMC_NE1" I L 4650 3600 50 -F94 "FPGA_FSMC_NBL0" I L 4650 3700 50 -F95 "FPGA_FSMC_NBL1" I L 4650 3800 50 -F96 "FPGA_FSMC_NL" I L 4650 3900 50 -F97 "FPGA_FSMC_CLK" I L 4650 4000 50 -F98 "FPGA_FSMC_NWAIT" I L 4650 4100 50 -F99 "FPGA_IO0" I L 4650 5350 50 -F100 "FPGA_IO1" I L 4650 5450 50 -F101 "FPGA_IO2" I L 4650 5550 50 -F102 "FPGA_IO3" I L 4650 5650 50 -F103 "FPGA_IO4" I L 4650 5750 50 -F104 "FPGA_IO5" I L 4650 5850 50 -F105 "FPGA_IO6" I L 4650 5950 50 -F106 "FPGA_IO7" I L 4650 6050 50 -F107 "FPGA_IO8" I L 4650 6150 50 -F108 "FPGA_IO9" I L 4650 6250 50 -F109 "FPGA_IO10" I L 4650 6350 50 -F110 "FPGA_IO11" I L 4650 6450 50 -F111 "FPGA_IO12" I L 4650 6550 50 -F112 "FPGA_IO13" I L 4650 6650 50 -F113 "FPGA_IO14" I L 4650 6750 50 -F114 "FPGA_IO15" I L 4650 6850 50 -F115 "FPGA_EEM0_IIC_SDA" I R 6150 2550 50 -F116 "FPGA_EEM0_IIC_SCL" I R 6150 2650 50 -F117 "FPGA_EEM1_IIC_SDA" I R 6150 4350 50 -F118 "FPGA_EEM1_IIC_SCL" I R 6150 4450 50 -F119 "FPGA_EEM2_IIC_SDA" I R 6150 6150 50 -F120 "FPGA_EEM2_IIC_SCL" I R 6150 6250 50 -F121 "FPGA_IIC_SDA" I L 4650 5100 50 -F122 "FPGA_IIC_SCL" I L 4650 5200 50 +F2 "FPGA_EEM0_0_P" I R 5950 750 50 +F3 "FPGA_EEM0_0_N" I R 5950 850 50 +F4 "FPGA_EEM0_7_P" I R 5950 2150 50 +F5 "FPGA_EEM0_7_N" I R 5950 2250 50 +F6 "FPGA_EEM0_6_P" I R 5950 1950 50 +F7 "FPGA_EEM0_6_N" I R 5950 2050 50 +F8 "FPGA_EEM0_5_P" I R 5950 1750 50 +F9 "FPGA_EEM0_5_N" I R 5950 1850 50 +F10 "FPGA_EEM0_4_P" I R 5950 1550 50 +F11 "FPGA_EEM0_4_N" I R 5950 1650 50 +F12 "FPGA_EEM0_3_P" I R 5950 1350 50 +F13 "FPGA_EEM0_3_N" I R 5950 1450 50 +F14 "FPGA_EEM0_2_P" I R 5950 1150 50 +F15 "FPGA_EEM0_2_N" I R 5950 1250 50 +F16 "FPGA_EEM0_1_P" I R 5950 950 50 +F17 "FPGA_EEM0_1_N" I R 5950 1050 50 +F18 "FPGA_EEM1_0_P" I R 5950 2550 50 +F19 "FPGA_EEM1_0_N" I R 5950 2650 50 +F20 "FPGA_EEM1_7_P" I R 5950 3950 50 +F21 "FPGA_EEM1_7_N" I R 5950 4050 50 +F22 "FPGA_EEM1_6_P" I R 5950 3750 50 +F23 "FPGA_EEM1_6_N" I R 5950 3850 50 +F24 "FPGA_EEM1_5_P" I R 5950 3550 50 +F25 "FPGA_EEM1_5_N" I R 5950 3650 50 +F26 "FPGA_EEM1_4_P" I R 5950 3350 50 +F27 "FPGA_EEM1_4_N" I R 5950 3450 50 +F28 "FPGA_EEM1_3_P" I R 5950 3150 50 +F29 "FPGA_EEM1_3_N" I R 5950 3250 50 +F30 "FPGA_EEM1_2_P" I R 5950 2950 50 +F31 "FPGA_EEM1_2_N" I R 5950 3050 50 +F32 "FPGA_EEM1_1_P" I R 5950 2750 50 +F33 "FPGA_EEM1_1_N" I R 5950 2850 50 +F34 "FPGA_EEM2_0_P" I R 5950 4350 50 +F35 "FPGA_EEM2_0_N" I R 5950 4450 50 +F36 "FPGA_EEM2_7_P" I R 5950 5750 50 +F37 "FPGA_EEM2_7_N" I R 5950 5850 50 +F38 "FPGA_EEM2_6_P" I R 5950 5550 50 +F39 "FPGA_EEM2_6_N" I R 5950 5650 50 +F40 "FPGA_EEM2_5_P" I R 5950 5350 50 +F41 "FPGA_EEM2_5_N" I R 5950 5450 50 +F42 "FPGA_EEM2_4_P" I R 5950 5150 50 +F43 "FPGA_EEM2_4_N" I R 5950 5250 50 +F44 "FPGA_EEM2_3_P" I R 5950 4950 50 +F45 "FPGA_EEM2_3_N" I R 5950 5050 50 +F46 "FPGA_EEM2_2_P" I R 5950 4750 50 +F47 "FPGA_EEM2_2_N" I R 5950 4850 50 +F48 "FPGA_EEM2_1_P" I R 5950 4550 50 +F49 "FPGA_EEM2_1_N" I R 5950 4650 50 +F50 "FPGA_FSMC_A0" I L 4450 2350 50 +F51 "FPGA_FSMC_A1" I L 4450 2450 50 +F52 "FPGA_FSMC_A2" I L 4450 2550 50 +F53 "FPGA_FSMC_A3" I L 4450 2650 50 +F54 "FPGA_FSMC_A4" I L 4450 2750 50 +F55 "FPGA_FSMC_A5" I L 4450 2850 50 +F56 "FPGA_FSMC_A6" I L 4450 2950 50 +F57 "FPGA_FSMC_A7" I L 4450 3050 50 +F58 "FPGA_FSMC_D0" I L 4450 750 50 +F59 "FPGA_FSMC_D1" I L 4450 850 50 +F60 "FPGA_FSMC_D2" I L 4450 950 50 +F61 "FPGA_FSMC_D3" I L 4450 1050 50 +F62 "FPGA_FSMC_D4" I L 4450 1150 50 +F63 "FPGA_FSMC_D5" I L 4450 1250 50 +F64 "FPGA_FSMC_D6" I L 4450 1350 50 +F65 "FPGA_FSMC_D7" I L 4450 1450 50 +F66 "FPGA_FSMC_D8" I L 4450 1550 50 +F67 "FPGA_FSMC_D9" I L 4450 1650 50 +F68 "FPGA_FSMC_D10" I L 4450 1750 50 +F69 "FPGA_FSMC_D11" I L 4450 1850 50 +F70 "FPGA_FSMC_D12" I L 4450 1950 50 +F71 "FPGA_FSMC_D13" I L 4450 2050 50 +F72 "FPGA_FSMC_D14" I L 4450 2150 50 +F73 "FPGA_FSMC_D15" I L 4450 2250 50 +F74 "FPGA_CSBSEL0" I L 4450 4450 50 +F75 "FPGA_CSBSEL1" I L 4450 4550 50 +F76 "FPGA_SPI_SDO" I L 4450 4050 50 +F77 "FPGA_SPI_SDI" I L 4450 4150 50 +F78 "FPGA_SPI_SS" I L 4450 4350 50 +F79 "FPGA_SPI_SCK" I L 4450 4250 50 +F80 "FPGA_CDONE" I L 4450 4650 50 +F81 "FPGA_CRESET" I L 4450 4750 50 +F82 "FPGA_ADC_D0" I R 5950 6200 50 +F83 "FPGA_ADC_D1" I R 5950 6300 50 +F84 "FPGA_ADC_D2" I R 5950 6400 50 +F85 "FPGA_ADC_D3" I R 5950 6500 50 +F86 "FPGA_ADC_D4" I R 5950 6600 50 +F87 "FPGA_ADC_D5" I R 5950 6700 50 +F88 "FPGA_ADC_D6" I R 5950 6800 50 +F89 "FPGA_ADC_D7" I R 5950 6900 50 +F90 "FPGA_ADC_CLK" I R 5950 7000 50 +F91 "FPGA_FSMC_NWE" I L 4450 3200 50 +F92 "FPGA_FSMC_NOE" I L 4450 3300 50 +F93 "FPGA_FSMC_NE1" I L 4450 3400 50 +F94 "FPGA_FSMC_NBL0" I L 4450 3500 50 +F95 "FPGA_FSMC_NBL1" I L 4450 3600 50 +F96 "FPGA_FSMC_NL" I L 4450 3700 50 +F97 "FPGA_FSMC_CLK" I L 4450 3800 50 +F98 "FPGA_FSMC_NWAIT" I L 4450 3900 50 +F99 "FPGA_IO0" I L 4450 5150 50 +F100 "FPGA_IO1" I L 4450 5250 50 +F101 "FPGA_IO2" I L 4450 5350 50 +F102 "FPGA_IO3" I L 4450 5450 50 +F103 "FPGA_IO4" I L 4450 5550 50 +F104 "FPGA_IO5" I L 4450 5650 50 +F105 "FPGA_IO6" I L 4450 5750 50 +F106 "FPGA_IO7" I L 4450 5850 50 +F107 "FPGA_IO8" I L 4450 5950 50 +F108 "FPGA_IO9" I L 4450 6050 50 +F109 "FPGA_IO10" I L 4450 6150 50 +F110 "FPGA_IO11" I L 4450 6250 50 +F111 "FPGA_IO12" I L 4450 6350 50 +F112 "FPGA_IO13" I L 4450 6450 50 +F113 "FPGA_IO14" I L 4450 6550 50 +F114 "FPGA_IO15" I L 4450 6650 50 +F115 "FPGA_EEM0_IIC_SDA" I R 5950 2350 50 +F116 "FPGA_EEM0_IIC_SCL" I R 5950 2450 50 +F117 "FPGA_EEM1_IIC_SDA" I R 5950 4150 50 +F118 "FPGA_EEM1_IIC_SCL" I R 5950 4250 50 +F119 "FPGA_EEM2_IIC_SDA" I R 5950 5950 50 +F120 "FPGA_EEM2_IIC_SCL" I R 5950 6050 50 +F121 "FPGA_IIC_SDA" I L 4450 4900 50 +F122 "FPGA_IIC_SCL" I L 4450 5000 50 $EndSheet $Sheet -S 7250 850 900 5550 +S 7050 650 1600 5500 U 60CB9D41 -F0 "LVDS" 50 -F1 "LVDS.sch" 50 -F2 "EEM0_0_P" I L 7250 950 50 -F3 "EEM0_0_N" I L 7250 1050 50 -F4 "EEM0_1_P" I L 7250 1150 50 -F5 "EEM0_1_N" I L 7250 1250 50 -F6 "EEM0_2_P" I L 7250 1350 50 -F7 "EEM0_2_N" I L 7250 1450 50 -F8 "EEM0_3_P" I L 7250 1550 50 -F9 "EEM0_3_N" I L 7250 1650 50 -F10 "EEM0_4_P" I L 7250 1750 50 -F11 "EEM0_4_N" I L 7250 1850 50 -F12 "EEM0_5_P" I L 7250 1950 50 -F13 "EEM0_5_N" I L 7250 2050 50 -F14 "EEM0_6_P" I L 7250 2150 50 -F15 "EEM0_6_N" I L 7250 2250 50 -F16 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