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FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing

This commit is contained in:
Jack-Zheng 2021-06-25 16:57:46 +08:00
parent 2a31c8b3f3
commit 0e1120d266
5 changed files with 4793 additions and 3422 deletions
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521
FPGA.sch
View File

@ -158,17 +158,17 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 1160 695
1 1100 6950 1 1100 6950
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
Text Label 3800 900 0 50 ~ 0 Text Label 3850 -400 0 50 ~ 0
I2C_0_SDA I2C_0_SDA
Text Label 3800 1000 0 50 ~ 0 Text Label 3850 -300 0 50 ~ 0
I2C_0_SCL I2C_0_SCL
Text Label 3800 1100 0 50 ~ 0 Text Label 3850 -200 0 50 ~ 0
I2C_1_SDA I2C_1_SDA
Text Label 3800 1200 0 50 ~ 0 Text Label 3850 -100 0 50 ~ 0
I2C_1_SCL I2C_1_SCL
Text Label 3800 1300 0 50 ~ 0 Text Label 3850 0 0 50 ~ 0
I2C_2_SDA I2C_2_SDA
Text Label 3800 1400 0 50 ~ 0 Text Label 3850 100 0 50 ~ 0
I2C_2_SCL I2C_2_SCL
$Comp $Comp
L Power_Protection:PRTR5V0U2X D2 L Power_Protection:PRTR5V0U2X D2
@ -200,30 +200,30 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 3360 695
1 3300 6950 1 3300 6950
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
Text HLabel 3850 900 2 50 Input ~ 0 Text HLabel 3900 -400 2 50 Input ~ 0
FPGA_EEM0_IIC_SDA FPGA_EEM0_IIC_SDA
Text HLabel 3850 1000 2 50 Input ~ 0 Text HLabel 3900 -300 2 50 Input ~ 0
FPGA_EEM0_IIC_SCL FPGA_EEM0_IIC_SCL
Text HLabel 3850 1100 2 50 Input ~ 0 Text HLabel 3900 -200 2 50 Input ~ 0
FPGA_EEM1_IIC_SDA FPGA_EEM1_IIC_SDA
Text HLabel 3850 1200 2 50 Input ~ 0 Text HLabel 3900 -100 2 50 Input ~ 0
FPGA_EEM1_IIC_SCL FPGA_EEM1_IIC_SCL
Text HLabel 3850 1300 2 50 Input ~ 0 Text HLabel 3900 0 2 50 Input ~ 0
FPGA_EEM2_IIC_SDA FPGA_EEM2_IIC_SDA
Text HLabel 3850 1400 2 50 Input ~ 0 Text HLabel 3900 100 2 50 Input ~ 0
FPGA_EEM2_IIC_SCL FPGA_EEM2_IIC_SCL
Wire Wire Line Wire Wire Line
3750 900 3850 900 3800 -400 3900 -400
Wire Wire Line Wire Wire Line
3750 1000 3850 1000 3800 -300 3900 -300
Wire Wire Line Wire Wire Line
3750 1100 3850 1100 3800 -200 3900 -200
Wire Wire Line Wire Wire Line
3750 1200 3850 1200 3800 -100 3900 -100
Wire Wire Line Wire Wire Line
3750 1300 3850 1300 3800 0 3900 0
Wire Wire Line Wire Wire Line
3750 1400 3850 1400 3800 100 3900 100
Wire Wire Line Wire Wire Line
1100 6400 1100 6450 1100 6400 1100 6450
Wire Wire Line Wire Wire Line
@ -258,102 +258,86 @@ Wire Wire Line
1600 7050 1600 6950 1600 7050 1600 6950
Wire Wire Line Wire Wire Line
600 7050 600 6950 600 7050 600 6950
Text HLabel 1850 900 2 50 Input ~ 0
FPGA_FSMC_A0
Text HLabel 1850 1000 2 50 Input ~ 0
FPGA_FSMC_A1
Text HLabel 1850 1100 2 50 Input ~ 0
FPGA_FSMC_A2
Text HLabel 1850 1200 2 50 Input ~ 0
FPGA_FSMC_A3
Text HLabel 1850 1300 2 50 Input ~ 0
FPGA_FSMC_A4
Text HLabel 1850 1400 2 50 Input ~ 0
FPGA_FSMC_A5
Text HLabel 1850 1500 2 50 Input ~ 0
FPGA_FSMC_A6
Text HLabel 1850 1600 2 50 Input ~ 0
FPGA_FSMC_A7
Text HLabel 1850 1700 2 50 Input ~ 0
FPGA_FSMC_D0
Text HLabel 1850 1800 2 50 Input ~ 0
FPGA_FSMC_D1
Text HLabel 1850 1900 2 50 Input ~ 0
FPGA_FSMC_D2
Text HLabel 1850 2000 2 50 Input ~ 0
FPGA_FSMC_D3
Text HLabel 1850 2100 2 50 Input ~ 0
FPGA_FSMC_D4
Text HLabel 1850 2200 2 50 Input ~ 0
FPGA_FSMC_D5
Text HLabel 1850 2300 2 50 Input ~ 0
FPGA_FSMC_D6
Text HLabel 1850 2400 2 50 Input ~ 0
FPGA_FSMC_D7
Text HLabel 1850 2500 2 50 Input ~ 0
FPGA_FSMC_D8
Text HLabel 1850 2600 2 50 Input ~ 0
FPGA_FSMC_D9
Text HLabel 1850 2700 2 50 Input ~ 0
FPGA_FSMC_D10
Text HLabel 1850 2800 2 50 Input ~ 0
FPGA_FSMC_D11
Text HLabel 1850 2900 2 50 Input ~ 0
FPGA_FSMC_D12
Text HLabel 1850 3000 2 50 Input ~ 0
FPGA_FSMC_D13
Text HLabel 1850 3100 2 50 Input ~ 0
FPGA_FSMC_D14
Text HLabel 1850 3200 2 50 Input ~ 0 Text HLabel 1850 3200 2 50 Input ~ 0
FPGA_FSMC_A0
Text HLabel 1850 2500 2 50 Input ~ 0
FPGA_FSMC_A3
Text HLabel 1850 2900 2 50 Input ~ 0
FPGA_FSMC_A4
Text HLabel 1850 3400 2 50 Input ~ 0
FPGA_FSMC_A5
Text HLabel 1850 4000 2 50 Input ~ 0
FPGA_FSMC_A6
Text HLabel 1850 2300 2 50 Input ~ 0
FPGA_FSMC_D0
Text HLabel 1850 2700 2 50 Input ~ 0
FPGA_FSMC_D1
Text HLabel 1850 2400 2 50 Input ~ 0
FPGA_FSMC_D2
Text HLabel 1850 2200 2 50 Input ~ 0
FPGA_FSMC_D3
Text HLabel 1850 5300 2 50 Input ~ 0
FPGA_FSMC_D4
Text HLabel 1850 5100 2 50 Input ~ 0
FPGA_FSMC_D5
Text HLabel 1850 6000 2 50 Input ~ 0
FPGA_FSMC_D6
Text HLabel 1850 5600 2 50 Input ~ 0
FPGA_FSMC_D7
Text HLabel 1850 4700 2 50 Input ~ 0
FPGA_FSMC_D9
Text HLabel 1850 4800 2 50 Input ~ 0
FPGA_FSMC_D10
Text HLabel 1850 4500 2 50 Input ~ 0
FPGA_FSMC_D11
Text HLabel 1850 4200 2 50 Input ~ 0
FPGA_FSMC_D12
Text HLabel 1850 3900 2 50 Input ~ 0
FPGA_FSMC_D13
Text HLabel 1850 4100 2 50 Input ~ 0
FPGA_FSMC_D14
Text HLabel 1850 3800 2 50 Input ~ 0
FPGA_FSMC_D15 FPGA_FSMC_D15
Wire Wire Line Wire Wire Line
1850 900 1800 900 1850 3200 1800 3200
Wire Wire Line
1850 1000 1800 1000
Wire Wire Line
1850 1100 1800 1100
Wire Wire Line
1850 1200 1800 1200
Wire Wire Line
1850 1300 1800 1300
Wire Wire Line
1850 1400 1800 1400
Wire Wire Line
1850 1500 1800 1500
Wire Wire Line
1850 1600 1800 1600
Wire Wire Line
1850 1700 1800 1700
Wire Wire Line
1850 1800 1800 1800
Wire Wire Line
1850 1900 1800 1900
Wire Wire Line
1850 2000 1800 2000
Wire Wire Line
1850 2100 1800 2100
Wire Wire Line
1850 2200 1800 2200
Wire Wire Line
1850 2300 1800 2300
Wire Wire Line
1850 2400 1800 2400
Wire Wire Line Wire Wire Line
1850 2500 1800 2500 1850 2500 1800 2500
Wire Wire Line Wire Wire Line
1850 2600 1800 2600 1850 2900 1800 2900
Wire Wire Line
1850 3400 1800 3400
Wire Wire Line
1850 4000 1800 4000
Wire Wire Line
1850 2300 1800 2300
Wire Wire Line Wire Wire Line
1850 2700 1800 2700 1850 2700 1800 2700
Wire Wire Line Wire Wire Line
1850 2800 1800 2800 1850 2400 1800 2400
Wire Wire Line Wire Wire Line
1850 2900 1800 2900 1850 2200 1800 2200
Wire Wire Line Wire Wire Line
1850 3000 1800 3000 1850 5300 1800 5300
Wire Wire Line Wire Wire Line
1850 3100 1800 3100 1850 5100 1800 5100
Wire Wire Line Wire Wire Line
1850 3200 1800 3200 1850 6000 1800 6000
Wire Wire Line
1850 5600 1800 5600
Wire Wire Line
1850 4700 1800 4700
Wire Wire Line
1850 4800 1800 4800
Wire Wire Line
1850 4500 1800 4500
Wire Wire Line
1850 4200 1800 4200
Wire Wire Line
1850 3900 1800 3900
Wire Wire Line
1850 4100 1800 4100
Wire Wire Line
1850 3800 1800 3800
$Comp $Comp
L Memory_Flash:AT25SF081-SSHD-X U4 L Memory_Flash:AT25SF081-SSHD-X U4
U 1 1 6211163A U 1 1 6211163A
@ -565,146 +549,134 @@ F 3 "~" H 8700 6800 50 0001 C CNN
1 8700 6800 1 8700 6800
0 1 1 0 0 1 1 0
$EndComp $EndComp
Text HLabel 3850 1500 2 50 Input ~ 0 Text HLabel 3900 200 2 50 Input ~ 0
FPGA_IIC_SDA FPGA_IIC_SDA
Text HLabel 3850 1600 2 50 Input ~ 0 Text HLabel 3900 300 2 50 Input ~ 0
FPGA_IIC_SCL FPGA_IIC_SCL
Wire Wire Line Wire Wire Line
3750 1500 3850 1500 3800 200 3900 200
Wire Wire Line Wire Wire Line
3750 1600 3850 1600 3800 300 3900 300
Text HLabel 3850 1900 2 50 Input ~ 0
FPGA_ADC_D0
Text HLabel 3850 2000 2 50 Input ~ 0
FPGA_ADC_D1
Text HLabel 3850 2100 2 50 Input ~ 0
FPGA_ADC_D2
Text HLabel 3850 2200 2 50 Input ~ 0
FPGA_ADC_D3
Text HLabel 3850 2300 2 50 Input ~ 0
FPGA_ADC_D4
Text HLabel 3850 2400 2 50 Input ~ 0
FPGA_ADC_D5
Text HLabel 3850 2500 2 50 Input ~ 0
FPGA_ADC_D6
Text HLabel 3850 2600 2 50 Input ~ 0
FPGA_ADC_D7
Text HLabel 3850 2700 2 50 Input ~ 0
FPGA_ADC_CLK
Wire Wire Line
3850 1900 3750 1900
Wire Wire Line
3850 2000 3750 2000
Wire Wire Line
3850 2100 3750 2100
Wire Wire Line
3850 2200 3750 2200
Wire Wire Line
3850 2300 3750 2300
Wire Wire Line
3850 2400 3750 2400
Wire Wire Line
3850 2500 3750 2500
Wire Wire Line
3850 2600 3750 2600
Wire Wire Line
3850 2700 3750 2700
Text HLabel 1850 3300 2 50 Input ~ 0
FPGA_FSMC_NWE
Text HLabel 1850 3400 2 50 Input ~ 0
FPGA_FSMC_NOE
Text HLabel 1850 3500 2 50 Input ~ 0
FPGA_FSMC_NE1
Text HLabel 1850 3600 2 50 Input ~ 0
FPGA_FSMC_NBL0
Text HLabel 1850 3700 2 50 Input ~ 0
FPGA_FSMC_NBL1
Text HLabel 1850 3800 2 50 Input ~ 0
FPGA_FSMC_NL
Text HLabel 1850 3900 2 50 Input ~ 0
FPGA_FSMC_CLK
Text HLabel 1850 4000 2 50 Input ~ 0
FPGA_FSMC_NWAIT
Wire Wire Line
1850 3300 1800 3300
Wire Wire Line
1800 3400 1850 3400
Wire Wire Line
1800 3500 1850 3500
Wire Wire Line
1850 3600 1800 3600
Wire Wire Line
1800 3700 1850 3700
Wire Wire Line
1850 3800 1800 3800
Wire Wire Line
1800 3900 1850 3900
Wire Wire Line
1850 4000 1800 4000
Text HLabel 3850 3000 2 50 Input ~ 0 Text HLabel 3850 3000 2 50 Input ~ 0
FPGA_IO0 FPGA_ADC_D1
Text HLabel 3850 3100 2 50 Input ~ 0 Text HLabel 3850 2900 2 50 Input ~ 0
FPGA_IO1 FPGA_ADC_D2
Text HLabel 3850 3200 2 50 Input ~ 0 Text HLabel 3850 2500 2 50 Input ~ 0
FPGA_IO2 FPGA_ADC_D3
Text HLabel 3850 3300 2 50 Input ~ 0 Text HLabel 3850 2100 2 50 Input ~ 0
FPGA_IO3 FPGA_ADC_D4
Text HLabel 3850 3400 2 50 Input ~ 0 Text HLabel 3850 2300 2 50 Input ~ 0
FPGA_IO4 FPGA_ADC_D5
Text HLabel 3850 3500 2 50 Input ~ 0 Text HLabel 3850 1700 2 50 Input ~ 0
FPGA_IO5 FPGA_ADC_D6
Text HLabel 3850 3600 2 50 Input ~ 0 Text HLabel 3850 1300 2 50 Input ~ 0
FPGA_IO6 FPGA_ADC_D7
Text HLabel 3850 3700 2 50 Input ~ 0 Text HLabel 3850 1200 2 50 Input ~ 0
FPGA_IO7 FPGA_ADC_CLK
Text HLabel 3850 3800 2 50 Input ~ 0
FPGA_IO8
Text HLabel 3850 3900 2 50 Input ~ 0
FPGA_IO9
Text HLabel 3850 4000 2 50 Input ~ 0
FPGA_IO10
Text HLabel 3850 4100 2 50 Input ~ 0
FPGA_IO11
Text HLabel 3850 4200 2 50 Input ~ 0
FPGA_IO12
Text HLabel 3850 4300 2 50 Input ~ 0
FPGA_IO13
Text HLabel 3850 4400 2 50 Input ~ 0
FPGA_IO14
Text HLabel 3850 4500 2 50 Input ~ 0
FPGA_IO15
Wire Wire Line Wire Wire Line
3850 3000 3750 3000 3850 3000 3750 3000
Wire Wire Line Wire Wire Line
3750 3100 3850 3100 3850 2900 3750 2900
Wire Wire Line Wire Wire Line
3850 3200 3750 3200 3850 2500 3750 2500
Wire Wire Line Wire Wire Line
3750 3300 3850 3300 3850 2100 3750 2100
Wire Wire Line Wire Wire Line
3850 3400 3750 3400 3850 2300 3750 2300
Wire Wire Line Wire Wire Line
3850 3500 3750 3500 3850 1700 3750 1700
Wire Wire Line Wire Wire Line
3850 3600 3750 3600 3850 1300 3750 1300
Wire Wire Line Wire Wire Line
3850 3700 3750 3700 3850 1200 3750 1200
Text HLabel 1850 1600 2 50 Input ~ 0
FPGA_FSMC_NWE
Text HLabel 1850 1700 2 50 Input ~ 0
FPGA_FSMC_NOE
Text HLabel 1850 1000 2 50 Input ~ 0
FPGA_FSMC_NE1
Text HLabel 1850 1500 2 50 Input ~ 0
FPGA_FSMC_NBL0
Text HLabel 1850 1300 2 50 Input ~ 0
FPGA_FSMC_NBL1
Text HLabel 1850 900 2 50 Input ~ 0
FPGA_FSMC_NL
Text HLabel 1850 1800 2 50 Input ~ 0
FPGA_FSMC_CLK
Text HLabel 1850 1200 2 50 Input ~ 0
FPGA_FSMC_NWAIT
Wire Wire Line Wire Wire Line
3850 3800 3750 3800 1850 1600 1800 1600
Wire Wire Line Wire Wire Line
3850 3900 3750 3900 1800 1700 1850 1700
Wire Wire Line Wire Wire Line
3850 4000 3750 4000 1800 1000 1850 1000
Wire Wire Line Wire Wire Line
3850 4100 3750 4100 1850 1500 1800 1500
Wire Wire Line Wire Wire Line
3850 4200 3750 4200 1800 1300 1850 1300
Wire Wire Line Wire Wire Line
3850 4300 3750 4300 1850 900 1800 900
Wire Wire Line Wire Wire Line
3750 4400 3850 4400 1800 1800 1850 1800
Wire Wire Line Wire Wire Line
3750 4500 3850 4500 1850 1200 1800 1200
Text HLabel 5850 2400 2 50 Input ~ 0
FPGA_IO2
Text HLabel 5850 3500 2 50 Input ~ 0
FPGA_IO3
Text HLabel 5850 1700 2 50 Input ~ 0
FPGA_IO4
Text HLabel 5850 3300 2 50 Input ~ 0
FPGA_IO5
Text HLabel 5850 1800 2 50 Input ~ 0
FPGA_IO6
Text HLabel 5850 3800 2 50 Input ~ 0
FPGA_IO7
Text HLabel 5850 1600 2 50 Input ~ 0
FPGA_IO8
Text HLabel 5850 4200 2 50 Input ~ 0
FPGA_IO9
Text HLabel 5850 1400 2 50 Input ~ 0
FPGA_IO10
Text HLabel 5850 4300 2 50 Input ~ 0
FPGA_IO11
Text HLabel 5850 1200 2 50 Input ~ 0
FPGA_IO12
Text HLabel 5850 4700 2 50 Input ~ 0
FPGA_IO13
Text HLabel 5850 1000 2 50 Input ~ 0
FPGA_IO14
Text HLabel 5850 4500 2 50 Input ~ 0
FPGA_IO15
Wire Wire Line
5850 2400 5750 2400
Wire Wire Line
5750 3500 5850 3500
Wire Wire Line
5850 1700 5750 1700
Wire Wire Line
5850 3300 5750 3300
Wire Wire Line
5850 1800 5750 1800
Wire Wire Line
5850 3800 5750 3800
Wire Wire Line
5850 1600 5750 1600
Wire Wire Line
5850 4200 5750 4200
Wire Wire Line
5850 1400 5750 1400
Wire Wire Line
5850 4300 5750 4300
Wire Wire Line
5850 1200 5750 1200
Wire Wire Line
5850 4700 5750 4700
Wire Wire Line
5750 1000 5850 1000
Wire Wire Line
5750 4500 5850 4500
Text GLabel 2200 6350 1 50 Input ~ 0 Text GLabel 2200 6350 1 50 Input ~ 0
+3V3MP +3V3MP
$Comp $Comp
@ -848,12 +820,8 @@ Wire Wire Line
Connection ~ 4350 6000 Connection ~ 4350 6000
Wire Wire Line Wire Wire Line
3900 6000 4350 6000 3900 6000 4350 6000
Wire Wire Line
4050 4600 3750 4600
Wire Wire Line Wire Wire Line
2200 7500 2200 7550 2200 7500 2200 7550
Wire Wire Line
3750 4700 3900 4700
$Comp $Comp
L Switch:SW_Push SW? L Switch:SW_Push SW?
U 1 1 6100CA18 U 1 1 6100CA18
@ -2644,50 +2612,6 @@ Text Label 12050 6050 0 50 ~ 0
LVDS3_2_P LVDS3_2_P
Text Label 12050 6150 0 50 ~ 0 Text Label 12050 6150 0 50 ~ 0
LVDS3_2_N LVDS3_2_N
NoConn ~ 5750 900
NoConn ~ 5750 1000
NoConn ~ 5750 1100
NoConn ~ 5750 1200
NoConn ~ 5750 1300
NoConn ~ 5750 1400
NoConn ~ 5750 1500
NoConn ~ 5750 1600
NoConn ~ 5750 1700
NoConn ~ 5750 1800
NoConn ~ 5750 1900
NoConn ~ 5750 2000
NoConn ~ 5750 2100
NoConn ~ 5750 2200
NoConn ~ 5750 2300
NoConn ~ 5750 2400
NoConn ~ 5750 2500
NoConn ~ 5750 2600
NoConn ~ 5750 2700
NoConn ~ 5750 2800
NoConn ~ 5750 2900
NoConn ~ 5750 3000
NoConn ~ 5750 3100
NoConn ~ 5750 3200
NoConn ~ 5750 3300
NoConn ~ 5750 3400
NoConn ~ 5750 3500
NoConn ~ 5750 3600
NoConn ~ 5750 3700
NoConn ~ 5750 3800
NoConn ~ 5750 3900
NoConn ~ 5750 4000
NoConn ~ 5750 4100
NoConn ~ 5750 4200
NoConn ~ 5750 4300
NoConn ~ 5750 4400
NoConn ~ 5750 4500
NoConn ~ 5750 4600
NoConn ~ 5750 4700
NoConn ~ 5750 4800
NoConn ~ 5750 4900
NoConn ~ 5750 5000
NoConn ~ 5750 5100
NoConn ~ 5750 5200
NoConn ~ 3750 4800 NoConn ~ 3750 4800
NoConn ~ 3750 4900 NoConn ~ 3750 4900
NoConn ~ 3750 5000 NoConn ~ 3750 5000
@ -2701,30 +2625,7 @@ NoConn ~ 3750 5700
NoConn ~ 3750 5800 NoConn ~ 3750 5800
NoConn ~ 3750 5900 NoConn ~ 3750 5900
NoConn ~ 3750 6000 NoConn ~ 3750 6000
NoConn ~ 1800 4100
NoConn ~ 1800 4200
NoConn ~ 1800 4300
NoConn ~ 1800 4400
NoConn ~ 1800 4500
NoConn ~ 1800 4600
NoConn ~ 1800 4700
NoConn ~ 1800 4800
NoConn ~ 1800 4900
NoConn ~ 1800 5000
NoConn ~ 1800 5100
NoConn ~ 1800 5200
NoConn ~ 1800 5300
NoConn ~ 1800 5400
NoConn ~ 1800 5500
NoConn ~ 1800 5600
NoConn ~ 1800 5700
NoConn ~ 1800 5800
NoConn ~ 1800 5900
NoConn ~ 1800 6000
NoConn ~ 3750 1700
NoConn ~ 3750 1800 NoConn ~ 3750 1800
NoConn ~ 3750 2800
NoConn ~ 3750 2900
NoConn ~ 7750 5300 NoConn ~ 7750 5300
NoConn ~ 7750 5400 NoConn ~ 7750 5400
NoConn ~ 7750 5500 NoConn ~ 7750 5500
@ -2825,4 +2726,44 @@ Text Label 7750 1800 0 50 ~ 0
LVDS1_4_P LVDS1_4_P
Text Label 7750 1700 0 50 ~ 0 Text Label 7750 1700 0 50 ~ 0
LVDS1_4_N LVDS1_4_N
Text HLabel 5850 2500 2 50 Input ~ 0
FPGA_IO0
Wire Wire Line
5850 2500 5750 2500
Text HLabel 5850 3000 2 50 Input ~ 0
FPGA_IO1
Wire Wire Line
5750 3000 5850 3000
Text HLabel 3850 2800 2 50 Input ~ 0
FPGA_ADC_D0
Wire Wire Line
3850 2800 3750 2800
Text Label 5850 4400 0 50 ~ 0
FPGA_LED
Text Label 5850 5000 0 50 ~ 0
FPGA_KEY
Wire Wire Line
5850 4400 5750 4400
Wire Wire Line
5750 5000 5850 5000
Text Label 3900 4700 1 50 ~ 0
FPGA_KEY
Text Label 4050 4600 1 50 ~ 0
FPGA_LED
Text HLabel 1850 2600 2 50 Input ~ 0
FPGA_FSMC_A2
Wire Wire Line
1850 2600 1800 2600
Text HLabel 1850 3600 2 50 Input ~ 0
FPGA_FSMC_A1
Wire Wire Line
1850 3600 1800 3600
Wire Wire Line
1850 5000 1800 5000
Text HLabel 1850 5000 2 50 Input ~ 0
FPGA_FSMC_D8
Wire Wire Line
1850 2000 1800 2000
Text HLabel 1850 2000 2 50 Input ~ 0
FPGA_FSMC_A7
$EndSCHEMATC $EndSCHEMATC

2
LVDS&IO.sch
View File

@ -972,7 +972,7 @@ L Connector_Generic:Conn_02x05_Odd_Even J4
U 1 1 61EC2C7C U 1 1 61EC2C7C
P 9150 4400 P 9150 4400
F 0 "J4" H 9200 4817 50 0000 C CNN F 0 "J4" H 9200 4817 50 0000 C CNN
F 1 "FPGA_Config_Flash" H 9200 4726 50 0000 C CNN F 1 "FPGA_Flash" H 9200 4726 50 0000 C CNN
F 2 "Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical_SMD" H 9150 4400 50 0001 C CNN F 2 "Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical_SMD" H 9150 4400 50 0001 C CNN
F 3 "~" H 9150 4400 50 0001 C CNN F 3 "~" H 9150 4400 50 0001 C CNN
1 9150 4400 1 9150 4400

4
Power.sch
View File

@ -224,7 +224,7 @@ U 1 1 6101472D
P 4000 2550 P 4000 2550
F 0 "L3" V 4190 2550 50 0000 C CNN F 0 "L3" V 4190 2550 50 0000 C CNN
F 1 "10uH" V 4099 2550 50 0000 C CNN F 1 "10uH" V 4099 2550 50 0000 C CNN
F 2 "Inductor_SMD:L_0603_1608Metric" H 4000 2550 50 0001 C CNN F 2 "Inductor_SMD:L_Coilcraft_XxL4040" H 4000 2550 50 0001 C CNN
F 3 "~" H 4000 2550 50 0001 C CNN F 3 "~" H 4000 2550 50 0001 C CNN
1 4000 2550 1 4000 2550
0 -1 -1 0 0 -1 -1 0
@ -865,7 +865,7 @@ U 1 1 60E74209
P 5050 5200 P 5050 5200
F 0 "L4" V 5240 5200 50 0000 C CNN F 0 "L4" V 5240 5200 50 0000 C CNN
F 1 "3.3uH" V 5149 5200 50 0000 C CNN F 1 "3.3uH" V 5149 5200 50 0000 C CNN
F 2 "Inductor_SMD:L_0603_1608Metric" H 5050 5200 50 0001 C CNN F 2 "Inductor_SMD:L_Coilcraft_XxL4040" H 5050 5200 50 0001 C CNN
F 3 "~" H 5050 5200 50 0001 C CNN F 3 "~" H 5050 5200 50 0001 C CNN
1 5050 5200 1 5050 5200
0 -1 -1 0 0 -1 -1 0

7678
TestAutomation.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

10
TestAutomation.pro
View File

@ -1,4 +1,4 @@
update=Thu Jun 24 15:33:38 2021 update=Fri Jun 25 11:54:49 2021
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
@ -42,7 +42,11 @@ TrackWidth1=0.25
TrackWidth2=0.0889 TrackWidth2=0.0889
TrackWidth3=0.1016 TrackWidth3=0.1016
TrackWidth4=0.127 TrackWidth4=0.127
TrackWidth5=0.1524 TrackWidth5=0.254
TrackWidth6=0.508
TrackWidth7=0.762
TrackWidth8=1.016
TrackWidth9=1.27
ViaDiameter1=0.8 ViaDiameter1=0.8
ViaDrill1=0.4 ViaDrill1=0.4
ViaDiameter2=0.4 ViaDiameter2=0.4
@ -93,7 +97,7 @@ Type=0
Enabled=1 Enabled=1
[pcbnew/Layer.In2.Cu] [pcbnew/Layer.In2.Cu]
Name=In2.Cu Name=In2.Cu
Type=0 Type=1
Enabled=1 Enabled=1
[pcbnew/Layer.In3.Cu] [pcbnew/Layer.In3.Cu]
Name=In3.Cu Name=In3.Cu