LVDS: add LVDS ports; all: add LEDs

This commit is contained in:
Jack-Zheng 2021-06-18 11:30:16 +08:00
parent 74f4fc201a
commit 0cebd6ed2b
8 changed files with 2348 additions and 1137 deletions

View File

@ -1,16 +0,0 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 6 8
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$EndSCHEMATC

View File

@ -438,17 +438,14 @@ Connection ~ 6300 4750
Connection ~ 5900 4750
Text HLabel 8650 4100 2 50 Input ~ 0
12V_CURRENT
$Comp
L Connector_Generic:Conn_01x02 J8
U 1 1 61786D79
P 6200 5100
F 0 "J8" H 6280 5092 50 0000 L CNN
F 1 "12V_OUT" H 6280 5001 50 0000 L CNN
F 2 "" H 6200 5100 50 0001 C CNN
F 3 "~" H 6200 5100 50 0001 C CNN
1 6200 5100
1 0 0 -1
$EndComp
Wire Wire Line
5900 4750 5900 5100
Wire Wire Line
6000 5100 5900 5100
Wire Wire Line
5900 5200 5900 5400
Wire Wire Line
6000 5200 5900 5200
$Comp
L power:GND #PWR086
U 1 1 61787915
@ -460,12 +457,62 @@ F 3 "" H 5900 5400 50 0001 C CNN
1 5900 5400
1 0 0 -1
$EndComp
$Comp
L Connector_Generic:Conn_01x02 J8
U 1 1 61786D79
P 6200 5100
F 0 "J8" H 6280 5092 50 0000 L CNN
F 1 "12V_OUT" H 6280 5001 50 0000 L CNN
F 2 "" H 6200 5100 50 0001 C CNN
F 3 "~" H 6200 5100 50 0001 C CNN
1 6200 5100
1 0 0 -1
$EndComp
Text HLabel 5800 5100 0 50 Input ~ 0
12V_OUT
Wire Wire Line
6000 5100 5900 5100
5800 5100 5900 5100
Connection ~ 5900 5100
$Comp
L Device:R R131
U 1 1 628EB7FE
P 6600 3100
F 0 "R131" H 6670 3146 50 0000 L CNN
F 1 "10k" H 6670 3055 50 0000 L CNN
F 2 "" V 6530 3100 50 0001 C CNN
F 3 "~" H 6600 3100 50 0001 C CNN
1 6600 3100
0 -1 -1 0
$EndComp
$Comp
L Device:LED D21
U 1 1 628EC8B3
P 6200 3100
F 0 "D21" V 6239 2982 50 0000 R CNN
F 1 "LED_12V_OUT" V 6148 2982 50 0000 R CNN
F 2 "" H 6200 3100 50 0001 C CNN
F 3 "~" H 6200 3100 50 0001 C CNN
1 6200 3100
-1 0 0 1
$EndComp
$Comp
L power:GND #PWR0125
U 1 1 628F2CF4
P 6900 3250
F 0 "#PWR0125" H 6900 3000 50 0001 C CNN
F 1 "GND" H 6905 3077 50 0000 C CNN
F 2 "" H 6900 3250 50 0001 C CNN
F 3 "" H 6900 3250 50 0001 C CNN
1 6900 3250
1 0 0 -1
$EndComp
Wire Wire Line
5900 4750 5900 5100
5900 3100 6050 3100
Connection ~ 5900 3100
Wire Wire Line
6000 5200 5900 5200
6350 3100 6450 3100
Wire Wire Line
5900 5200 5900 5400
6750 3100 6900 3100
Wire Wire Line
6900 3100 6900 3250
$EndSCHEMATC

View File

@ -3,7 +3,7 @@ EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 4 8
Sheet 3 8
Title ""
Date ""
Rev ""

153
FPGA.sch
View File

@ -3,7 +3,7 @@ EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 8 8
Sheet 7 8
Title ""
Date ""
Rev ""
@ -1792,17 +1792,17 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 3360 695
1 0 0 -1
$EndComp
Text HLabel 3850 900 2 50 Input ~ 0
FPGA_IIC0_SDA
FPGA_EEM0_IIC_SDA
Text HLabel 3850 1000 2 50 Input ~ 0
FPGA_IIC0_SCL
FPGA_EEM0_IIC_SCL
Text HLabel 3850 1100 2 50 Input ~ 0
FPGA_IIC1_SDA
FPGA_EEM1_IIC_SDA
Text HLabel 3850 1200 2 50 Input ~ 0
FPGA_IIC1_SCL
FPGA_EEM1_IIC_SCL
Text HLabel 3850 1300 2 50 Input ~ 0
FPGA_IIC2_SDA
FPGA_EEM2_IIC_SDA
Text HLabel 3850 1400 2 50 Input ~ 0
FPGA_IIC2_SCL
FPGA_EEM2_IIC_SCL
Wire Wire Line
3750 900 3850 900
Wire Wire Line
@ -1979,32 +1979,6 @@ F 3 "" H 2200 7550 50 0001 C CNN
1 2200 7550
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR067
U 1 1 6230BD7E
P 2200 6000
F 0 "#PWR067" H 2200 5850 50 0001 C CNN
F 1 "+3V3" H 2215 6173 50 0000 C CNN
F 2 "" H 2200 6000 50 0001 C CNN
F 3 "" H 2200 6000 50 0001 C CNN
1 2200 6000
1 0 0 -1
$EndComp
$Comp
L Device:D_Schottky D?
U 1 1 6231DCDB
P 2200 6200
AR Path="/60E4702B/6231DCDB" Ref="D?" Part="1"
AR Path="/60C0E996/6231DCDB" Ref="D14" Part="1"
F 0 "D14" V 2154 6280 50 0000 L CNN
F 1 "SS16" V 2245 6280 50 0000 L CNN
F 2 "Diode_SMD:D_SMA" H 2200 6200 50 0001 C CNN
F 3 "~" H 2200 6200 50 0001 C CNN
1 2200 6200
0 -1 -1 0
$EndComp
Wire Wire Line
2200 6050 2200 6000
Wire Wire Line
2200 6350 2200 6400
Text HLabel 5800 5300 2 50 Input ~ 0
@ -2183,9 +2157,9 @@ F 3 "~" H 8700 6800 50 0001 C CNN
0 1 1 0
$EndComp
Text HLabel 3850 1500 2 50 Input ~ 0
FPGA_IIC3_SDA
FPGA_IIC_SDA
Text HLabel 3850 1600 2 50 Input ~ 0
FPGA_IIC3_SCL
FPGA_IIC_SCL
Wire Wire Line
3750 1500 3850 1500
Wire Wire Line
@ -2323,10 +2297,10 @@ Wire Wire Line
Wire Wire Line
3750 4500 3850 4500
$Comp
L Connector:TestPoint TP?
L Connector:TestPoint TP1
U 1 1 617CC5CE
P 10500 1700
F 0 "TP?" V 10454 1888 50 0000 L CNN
F 0 "TP1" V 10454 1888 50 0000 L CNN
F 1 "FPGA_VPP_FAST" V 10545 1888 50 0000 L CNN
F 2 "" H 10700 1700 50 0001 C CNN
F 3 "~" H 10700 1700 50 0001 C CNN
@ -2335,4 +2309,109 @@ F 3 "~" H 10700 1700 50 0001 C CNN
$EndComp
Wire Wire Line
10450 1700 10500 1700
Text GLabel 2200 6350 1 50 Input ~ 0
+3V3MP
Wire Wire Line
4150 5450 4150 5500
Wire Wire Line
4150 5100 4150 5150
Wire Wire Line
4150 4900 4150 4850
$Comp
L Device:Q_NPN_BEC Q?
U 1 1 61C9A1CC
P 4050 5700
AR Path="/60E3407A/61C9A1CC" Ref="Q?" Part="1"
AR Path="/60C0E996/61C9A1CC" Ref="Q9" Part="1"
F 0 "Q9" H 4240 5746 50 0000 L CNN
F 1 "PMBT3904" H 4240 5655 50 0000 L CNN
F 2 "" H 4250 5800 50 0001 C CNN
F 3 "~" H 4050 5700 50 0001 C CNN
1 4050 5700
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0128
U 1 1 61C1A434
P 4150 6050
F 0 "#PWR0128" H 4150 5800 50 0001 C CNN
F 1 "GND" H 4155 5877 50 0000 C CNN
F 2 "" H 4150 6050 50 0001 C CNN
F 3 "" H 4150 6050 50 0001 C CNN
1 4150 6050
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR0127
U 1 1 61B96C01
P 4150 4850
F 0 "#PWR0127" H 4150 4700 50 0001 C CNN
F 1 "+3V3" H 4165 5023 50 0000 C CNN
F 2 "" H 4150 4850 50 0001 C CNN
F 3 "" H 4150 4850 50 0001 C CNN
1 4150 4850
1 0 0 -1
$EndComp
$Comp
L Device:LED D23
U 1 1 61B7C071
P 4150 5300
F 0 "D23" V 4189 5182 50 0000 R CNN
F 1 "LED_FPGA" V 4098 5182 50 0000 R CNN
F 2 "" H 4150 5300 50 0001 C CNN
F 3 "~" H 4150 5300 50 0001 C CNN
1 4150 5300
0 -1 -1 0
$EndComp
$Comp
L Device:R_Small R134
U 1 1 61E99DA6
P 3850 5850
F 0 "R134" H 3909 5896 50 0000 L CNN
F 1 "10k" H 3909 5805 50 0000 L CNN
F 2 "" H 3850 5850 50 0001 C CNN
F 3 "~" H 3850 5850 50 0001 C CNN
1 3850 5850
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R135
U 1 1 61ED30A4
P 4150 5000
F 0 "R135" H 4209 5046 50 0000 L CNN
F 1 "220" H 4209 4955 50 0000 L CNN
F 2 "" H 4150 5000 50 0001 C CNN
F 3 "~" H 4150 5000 50 0001 C CNN
1 4150 5000
1 0 0 -1
$EndComp
Wire Wire Line
3850 6000 4150 6000
Wire Wire Line
4150 6050 4150 6000
Connection ~ 4150 6000
Wire Wire Line
3850 5750 3850 5700
Wire Wire Line
3850 4600 3750 4600
Wire Wire Line
3850 6000 3850 5950
Wire Wire Line
4150 5900 4150 6000
$Comp
L Device:R_Small R133
U 1 1 623C0DC2
P 3850 5500
F 0 "R133" H 3909 5546 50 0000 L CNN
F 1 "1k" H 3909 5455 50 0000 L CNN
F 2 "" H 3850 5500 50 0001 C CNN
F 3 "~" H 3850 5500 50 0001 C CNN
1 3850 5500
1 0 0 -1
$EndComp
Wire Wire Line
3850 5600 3850 5700
Connection ~ 3850 5700
Wire Wire Line
3850 5400 3850 4600
$EndSCHEMATC

687
LVDS.sch Normal file
View File

@ -0,0 +1,687 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 8 8
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_01x30 J9
U 1 1 6182545F
P 3500 3400
F 0 "J9" H 3580 3392 50 0000 L CNN
F 1 "EEM0" H 3580 3301 50 0000 L CNN
F 2 "" H 3500 3400 50 0001 C CNN
F 3 "~" H 3500 3400 50 0001 C CNN
1 3500 3400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR021
U 1 1 6182D6D6
P 2650 2000
F 0 "#PWR021" H 2650 1750 50 0001 C CNN
F 1 "GND" V 2655 1872 50 0000 R CNN
F 2 "" H 2650 2000 50 0001 C CNN
F 3 "" H 2650 2000 50 0001 C CNN
1 2650 2000
0 1 1 0
$EndComp
$Comp
L power:GND #PWR026
U 1 1 6182E7D3
P 2650 2300
F 0 "#PWR026" H 2650 2050 50 0001 C CNN
F 1 "GND" V 2655 2172 50 0000 R CNN
F 2 "" H 2650 2300 50 0001 C CNN
F 3 "" H 2650 2300 50 0001 C CNN
1 2650 2300
0 1 1 0
$EndComp
$Comp
L power:GND #PWR030
U 1 1 6182EB3C
P 2650 2600
F 0 "#PWR030" H 2650 2350 50 0001 C CNN
F 1 "GND" V 2655 2472 50 0000 R CNN
F 2 "" H 2650 2600 50 0001 C CNN
F 3 "" H 2650 2600 50 0001 C CNN
1 2650 2600
0 1 1 0
$EndComp
$Comp
L power:GND #PWR033
U 1 1 6182F404
P 2650 2900
F 0 "#PWR033" H 2650 2650 50 0001 C CNN
F 1 "GND" V 2655 2772 50 0000 R CNN
F 2 "" H 2650 2900 50 0001 C CNN
F 3 "" H 2650 2900 50 0001 C CNN
1 2650 2900
0 1 1 0
$EndComp
$Comp
L power:GND #PWR034
U 1 1 6182FA4D
P 2650 3200
F 0 "#PWR034" H 2650 2950 50 0001 C CNN
F 1 "GND" V 2655 3072 50 0000 R CNN
F 2 "" H 2650 3200 50 0001 C CNN
F 3 "" H 2650 3200 50 0001 C CNN
1 2650 3200
0 1 1 0
$EndComp
$Comp
L power:GND #PWR037
U 1 1 6182FCDE
P 2650 3500
F 0 "#PWR037" H 2650 3250 50 0001 C CNN
F 1 "GND" V 2655 3372 50 0000 R CNN
F 2 "" H 2650 3500 50 0001 C CNN
F 3 "" H 2650 3500 50 0001 C CNN
1 2650 3500
0 1 1 0
$EndComp
$Comp
L power:GND #PWR067
U 1 1 61830555
P 2650 3800
F 0 "#PWR067" H 2650 3550 50 0001 C CNN
F 1 "GND" V 2655 3672 50 0000 R CNN
F 2 "" H 2650 3800 50 0001 C CNN
F 3 "" H 2650 3800 50 0001 C CNN
1 2650 3800
0 1 1 0
$EndComp
$Comp
L power:GND #PWR087
U 1 1 61830D1E
P 2650 4100
F 0 "#PWR087" H 2650 3850 50 0001 C CNN
F 1 "GND" V 2655 3972 50 0000 R CNN
F 2 "" H 2650 4100 50 0001 C CNN
F 3 "" H 2650 4100 50 0001 C CNN
1 2650 4100
0 1 1 0
$EndComp
$Comp
L power:GND #PWR088
U 1 1 61831030
P 2650 4400
F 0 "#PWR088" H 2650 4150 50 0001 C CNN
F 1 "GND" V 2655 4272 50 0000 R CNN
F 2 "" H 2650 4400 50 0001 C CNN
F 3 "" H 2650 4400 50 0001 C CNN
1 2650 4400
0 1 1 0
$EndComp
Text HLabel 3150 2100 0 50 Input ~ 0
EEM0_0_P
Text HLabel 3150 2200 0 50 Input ~ 0
EEM0_0_N
Text HLabel 3150 2400 0 50 Input ~ 0
EEM0_1_P
Text HLabel 3150 2500 0 50 Input ~ 0
EEM0_1_N
Text HLabel 3150 2700 0 50 Input ~ 0
EEM0_2_P
Text HLabel 3150 2800 0 50 Input ~ 0
EEM0_2_N
Text HLabel 3150 3000 0 50 Input ~ 0
EEM0_3_P
Text HLabel 3150 3100 0 50 Input ~ 0
EEM0_3_N
Text HLabel 3150 3300 0 50 Input ~ 0
EEM0_4_P
Text HLabel 3150 3400 0 50 Input ~ 0
EEM0_4_N
Text HLabel 3150 3600 0 50 Input ~ 0
EEM0_5_P
Text HLabel 3150 3700 0 50 Input ~ 0
EEM0_5_N
Text HLabel 3150 3900 0 50 Input ~ 0
EEM0_6_P
Text HLabel 3150 4000 0 50 Input ~ 0
EEM0_6_N
Text HLabel 3150 4200 0 50 Input ~ 0
EEM0_7_P
Text HLabel 3150 4300 0 50 Input ~ 0
EEM0_7_N
Text HLabel 3150 4500 0 50 Input ~ 0
EEM0_IIC_SDA
Text HLabel 3150 4600 0 50 Input ~ 0
EEM0_IIC_SCL
Text Label 3050 4750 2 50 ~ 0
EEM_12V
Wire Wire Line
2650 2000 3300 2000
Wire Wire Line
3150 2100 3300 2100
Wire Wire Line
3150 2200 3300 2200
Wire Wire Line
2650 2300 3300 2300
Wire Wire Line
3150 2400 3300 2400
Wire Wire Line
3150 2500 3300 2500
Wire Wire Line
2650 2600 3300 2600
Wire Wire Line
3150 2700 3300 2700
Wire Wire Line
3150 2800 3300 2800
Wire Wire Line
2650 2900 3300 2900
Wire Wire Line
3150 3000 3300 3000
Wire Wire Line
3150 3100 3300 3100
Wire Wire Line
2650 3200 3300 3200
Wire Wire Line
3150 3300 3300 3300
Wire Wire Line
3150 3400 3300 3400
Wire Wire Line
2650 3500 3300 3500
Wire Wire Line
3150 3600 3300 3600
Wire Wire Line
3150 3700 3300 3700
Wire Wire Line
2650 3800 3300 3800
Wire Wire Line
3150 3900 3300 3900
Wire Wire Line
3150 4000 3300 4000
Wire Wire Line
2650 4100 3300 4100
Wire Wire Line
3150 4200 3300 4200
Wire Wire Line
3150 4300 3300 4300
Wire Wire Line
2650 4400 3300 4400
Wire Wire Line
3150 4500 3300 4500
Wire Wire Line
3150 4600 3300 4600
Wire Wire Line
3300 4700 3200 4700
Wire Wire Line
3200 4700 3200 4750
Wire Wire Line
3200 4800 3300 4800
Wire Wire Line
3200 4750 3050 4750
Connection ~ 3200 4750
Wire Wire Line
3200 4750 3200 4800
Text GLabel 3150 4900 0 50 Input ~ 0
+3V3MP
Wire Wire Line
3300 4900 3150 4900
$Comp
L Connector_Generic:Conn_01x30 J10
U 1 1 61B237C0
P 5500 3400
F 0 "J10" H 5580 3392 50 0000 L CNN
F 1 "EEM1" H 5580 3301 50 0000 L CNN
F 2 "" H 5500 3400 50 0001 C CNN
F 3 "~" H 5500 3400 50 0001 C CNN
1 5500 3400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR089
U 1 1 61B237C6
P 4650 2000
F 0 "#PWR089" H 4650 1750 50 0001 C CNN
F 1 "GND" V 4655 1872 50 0000 R CNN
F 2 "" H 4650 2000 50 0001 C CNN
F 3 "" H 4650 2000 50 0001 C CNN
1 4650 2000
0 1 1 0
$EndComp
$Comp
L power:GND #PWR090
U 1 1 61B237CC
P 4650 2300
F 0 "#PWR090" H 4650 2050 50 0001 C CNN
F 1 "GND" V 4655 2172 50 0000 R CNN
F 2 "" H 4650 2300 50 0001 C CNN
F 3 "" H 4650 2300 50 0001 C CNN
1 4650 2300
0 1 1 0
$EndComp
$Comp
L power:GND #PWR091
U 1 1 61B237D2
P 4650 2600
F 0 "#PWR091" H 4650 2350 50 0001 C CNN
F 1 "GND" V 4655 2472 50 0000 R CNN
F 2 "" H 4650 2600 50 0001 C CNN
F 3 "" H 4650 2600 50 0001 C CNN
1 4650 2600
0 1 1 0
$EndComp
$Comp
L power:GND #PWR092
U 1 1 61B237D8
P 4650 2900
F 0 "#PWR092" H 4650 2650 50 0001 C CNN
F 1 "GND" V 4655 2772 50 0000 R CNN
F 2 "" H 4650 2900 50 0001 C CNN
F 3 "" H 4650 2900 50 0001 C CNN
1 4650 2900
0 1 1 0
$EndComp
$Comp
L power:GND #PWR093
U 1 1 61B237DE
P 4650 3200
F 0 "#PWR093" H 4650 2950 50 0001 C CNN
F 1 "GND" V 4655 3072 50 0000 R CNN
F 2 "" H 4650 3200 50 0001 C CNN
F 3 "" H 4650 3200 50 0001 C CNN
1 4650 3200
0 1 1 0
$EndComp
$Comp
L power:GND #PWR094
U 1 1 61B237E4
P 4650 3500
F 0 "#PWR094" H 4650 3250 50 0001 C CNN
F 1 "GND" V 4655 3372 50 0000 R CNN
F 2 "" H 4650 3500 50 0001 C CNN
F 3 "" H 4650 3500 50 0001 C CNN
1 4650 3500
0 1 1 0
$EndComp
$Comp
L power:GND #PWR095
U 1 1 61B237EA
P 4650 3800
F 0 "#PWR095" H 4650 3550 50 0001 C CNN
F 1 "GND" V 4655 3672 50 0000 R CNN
F 2 "" H 4650 3800 50 0001 C CNN
F 3 "" H 4650 3800 50 0001 C CNN
1 4650 3800
0 1 1 0
$EndComp
$Comp
L power:GND #PWR096
U 1 1 61B237F0
P 4650 4100
F 0 "#PWR096" H 4650 3850 50 0001 C CNN
F 1 "GND" V 4655 3972 50 0000 R CNN
F 2 "" H 4650 4100 50 0001 C CNN
F 3 "" H 4650 4100 50 0001 C CNN
1 4650 4100
0 1 1 0
$EndComp
$Comp
L power:GND #PWR097
U 1 1 61B237F6
P 4650 4400
F 0 "#PWR097" H 4650 4150 50 0001 C CNN
F 1 "GND" V 4655 4272 50 0000 R CNN
F 2 "" H 4650 4400 50 0001 C CNN
F 3 "" H 4650 4400 50 0001 C CNN
1 4650 4400
0 1 1 0
$EndComp
Text HLabel 5150 2100 0 50 Input ~ 0
EEM1_0_P
Text HLabel 5150 2200 0 50 Input ~ 0
EEM1_0_N
Text HLabel 5150 2400 0 50 Input ~ 0
EEM1_1_P
Text HLabel 5150 2500 0 50 Input ~ 0
EEM1_1_N
Text HLabel 5150 2700 0 50 Input ~ 0
EEM1_2_P
Text HLabel 5150 2800 0 50 Input ~ 0
EEM1_2_N
Text HLabel 5150 3000 0 50 Input ~ 0
EEM1_3_P
Text HLabel 5150 3100 0 50 Input ~ 0
EEM1_3_N
Text HLabel 5150 3300 0 50 Input ~ 0
EEM1_4_P
Text HLabel 5150 3400 0 50 Input ~ 0
EEM1_4_N
Text HLabel 5150 3600 0 50 Input ~ 0
EEM1_5_P
Text HLabel 5150 3700 0 50 Input ~ 0
EEM1_5_N
Text HLabel 5150 3900 0 50 Input ~ 0
EEM1_6_P
Text HLabel 5150 4000 0 50 Input ~ 0
EEM1_6_N
Text HLabel 5150 4200 0 50 Input ~ 0
EEM1_7_P
Text HLabel 5150 4300 0 50 Input ~ 0
EEM1_7_N
Text HLabel 5150 4500 0 50 Input ~ 0
EEM1_IIC_SDA
Text HLabel 5150 4600 0 50 Input ~ 0
EEM1_IIC_SCL
Text Label 5050 4750 2 50 ~ 0
EEM_12V
Wire Wire Line
4650 2000 5300 2000
Wire Wire Line
5150 2100 5300 2100
Wire Wire Line
5150 2200 5300 2200
Wire Wire Line
4650 2300 5300 2300
Wire Wire Line
5150 2400 5300 2400
Wire Wire Line
5150 2500 5300 2500
Wire Wire Line
4650 2600 5300 2600
Wire Wire Line
5150 2700 5300 2700
Wire Wire Line
5150 2800 5300 2800
Wire Wire Line
4650 2900 5300 2900
Wire Wire Line
5150 3000 5300 3000
Wire Wire Line
5150 3100 5300 3100
Wire Wire Line
4650 3200 5300 3200
Wire Wire Line
5150 3300 5300 3300
Wire Wire Line
5150 3400 5300 3400
Wire Wire Line
4650 3500 5300 3500
Wire Wire Line
5150 3600 5300 3600
Wire Wire Line
5150 3700 5300 3700
Wire Wire Line
4650 3800 5300 3800
Wire Wire Line
5150 3900 5300 3900
Wire Wire Line
5150 4000 5300 4000
Wire Wire Line
4650 4100 5300 4100
Wire Wire Line
5150 4200 5300 4200
Wire Wire Line
5150 4300 5300 4300
Wire Wire Line
4650 4400 5300 4400
Wire Wire Line
5150 4500 5300 4500
Wire Wire Line
5150 4600 5300 4600
Wire Wire Line
5300 4700 5200 4700
Wire Wire Line
5200 4700 5200 4750
Wire Wire Line
5200 4800 5300 4800
Wire Wire Line
5200 4750 5050 4750
Connection ~ 5200 4750
Wire Wire Line
5200 4750 5200 4800
Text GLabel 5150 4900 0 50 Input ~ 0
+3V3MP
Wire Wire Line
5300 4900 5150 4900
$Comp
L Connector_Generic:Conn_01x30 J11
U 1 1 61B2D756
P 7400 3400
AR Path="/60CB9D41/61B2D756" Ref="J11" Part="1"
AR Path="/60FB17F2/61B2D756" Ref="J?" Part="1"
F 0 "J11" H 7480 3392 50 0000 L CNN
F 1 "EEM2" H 7480 3301 50 0000 L CNN
F 2 "" H 7400 3400 50 0001 C CNN
F 3 "~" H 7400 3400 50 0001 C CNN
1 7400 3400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR098
U 1 1 61B2D75C
P 6550 2000
AR Path="/60CB9D41/61B2D75C" Ref="#PWR098" Part="1"
AR Path="/60FB17F2/61B2D75C" Ref="#PWR?" Part="1"
F 0 "#PWR098" H 6550 1750 50 0001 C CNN
F 1 "GND" V 6555 1872 50 0000 R CNN
F 2 "" H 6550 2000 50 0001 C CNN
F 3 "" H 6550 2000 50 0001 C CNN
1 6550 2000
0 1 1 0
$EndComp
$Comp
L power:GND #PWR099
U 1 1 61B2D762
P 6550 2300
AR Path="/60CB9D41/61B2D762" Ref="#PWR099" Part="1"
AR Path="/60FB17F2/61B2D762" Ref="#PWR?" Part="1"
F 0 "#PWR099" H 6550 2050 50 0001 C CNN
F 1 "GND" V 6555 2172 50 0000 R CNN
F 2 "" H 6550 2300 50 0001 C CNN
F 3 "" H 6550 2300 50 0001 C CNN
1 6550 2300
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0100
U 1 1 61B2D768
P 6550 2600
AR Path="/60CB9D41/61B2D768" Ref="#PWR0100" Part="1"
AR Path="/60FB17F2/61B2D768" Ref="#PWR?" Part="1"
F 0 "#PWR0100" H 6550 2350 50 0001 C CNN
F 1 "GND" V 6555 2472 50 0000 R CNN
F 2 "" H 6550 2600 50 0001 C CNN
F 3 "" H 6550 2600 50 0001 C CNN
1 6550 2600
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0103
U 1 1 61B2D76E
P 6550 2900
AR Path="/60CB9D41/61B2D76E" Ref="#PWR0103" Part="1"
AR Path="/60FB17F2/61B2D76E" Ref="#PWR?" Part="1"
F 0 "#PWR0103" H 6550 2650 50 0001 C CNN
F 1 "GND" V 6555 2772 50 0000 R CNN
F 2 "" H 6550 2900 50 0001 C CNN
F 3 "" H 6550 2900 50 0001 C CNN
1 6550 2900
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0105
U 1 1 61B2D774
P 6550 3200
AR Path="/60CB9D41/61B2D774" Ref="#PWR0105" Part="1"
AR Path="/60FB17F2/61B2D774" Ref="#PWR?" Part="1"
F 0 "#PWR0105" H 6550 2950 50 0001 C CNN
F 1 "GND" V 6555 3072 50 0000 R CNN
F 2 "" H 6550 3200 50 0001 C CNN
F 3 "" H 6550 3200 50 0001 C CNN
1 6550 3200
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0107
U 1 1 61B2D77A
P 6550 3500
AR Path="/60CB9D41/61B2D77A" Ref="#PWR0107" Part="1"
AR Path="/60FB17F2/61B2D77A" Ref="#PWR?" Part="1"
F 0 "#PWR0107" H 6550 3250 50 0001 C CNN
F 1 "GND" V 6555 3372 50 0000 R CNN
F 2 "" H 6550 3500 50 0001 C CNN
F 3 "" H 6550 3500 50 0001 C CNN
1 6550 3500
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0108
U 1 1 61B2D780
P 6550 3800
AR Path="/60CB9D41/61B2D780" Ref="#PWR0108" Part="1"
AR Path="/60FB17F2/61B2D780" Ref="#PWR?" Part="1"
F 0 "#PWR0108" H 6550 3550 50 0001 C CNN
F 1 "GND" V 6555 3672 50 0000 R CNN
F 2 "" H 6550 3800 50 0001 C CNN
F 3 "" H 6550 3800 50 0001 C CNN
1 6550 3800
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0115
U 1 1 61B2D786
P 6550 4100
AR Path="/60CB9D41/61B2D786" Ref="#PWR0115" Part="1"
AR Path="/60FB17F2/61B2D786" Ref="#PWR?" Part="1"
F 0 "#PWR0115" H 6550 3850 50 0001 C CNN
F 1 "GND" V 6555 3972 50 0000 R CNN
F 2 "" H 6550 4100 50 0001 C CNN
F 3 "" H 6550 4100 50 0001 C CNN
1 6550 4100
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0116
U 1 1 61B2D78C
P 6550 4400
AR Path="/60CB9D41/61B2D78C" Ref="#PWR0116" Part="1"
AR Path="/60FB17F2/61B2D78C" Ref="#PWR?" Part="1"
F 0 "#PWR0116" H 6550 4150 50 0001 C CNN
F 1 "GND" V 6555 4272 50 0000 R CNN
F 2 "" H 6550 4400 50 0001 C CNN
F 3 "" H 6550 4400 50 0001 C CNN
1 6550 4400
0 1 1 0
$EndComp
Text HLabel 7050 2100 0 50 Input ~ 0
EEM2_0_P
Text HLabel 7050 2200 0 50 Input ~ 0
EEM2_0_N
Text HLabel 7050 2400 0 50 Input ~ 0
EEM2_1_P
Text HLabel 7050 2500 0 50 Input ~ 0
EEM2_1_N
Text HLabel 7050 2700 0 50 Input ~ 0
EEM2_2_P
Text HLabel 7050 2800 0 50 Input ~ 0
EEM2_2_N
Text HLabel 7050 3000 0 50 Input ~ 0
EEM2_3_P
Text HLabel 7050 3100 0 50 Input ~ 0
EEM2_3_N
Text HLabel 7050 3300 0 50 Input ~ 0
EEM2_4_P
Text HLabel 7050 3400 0 50 Input ~ 0
EEM2_4_N
Text HLabel 7050 3600 0 50 Input ~ 0
EEM2_5_P
Text HLabel 7050 3700 0 50 Input ~ 0
EEM2_5_N
Text HLabel 7050 3900 0 50 Input ~ 0
EEM2_6_P
Text HLabel 7050 4000 0 50 Input ~ 0
EEM2_6_N
Text HLabel 7050 4200 0 50 Input ~ 0
EEM2_7_P
Text HLabel 7050 4300 0 50 Input ~ 0
EEM2_7_N
Text HLabel 7050 4500 0 50 Input ~ 0
EEM2_IIC_SDA
Text Label 6950 4750 2 50 ~ 0
EEM_12V
Wire Wire Line
6550 2000 7200 2000
Wire Wire Line
7050 2100 7200 2100
Wire Wire Line
7050 2200 7200 2200
Wire Wire Line
6550 2300 7200 2300
Wire Wire Line
7050 2400 7200 2400
Wire Wire Line
7050 2500 7200 2500
Wire Wire Line
6550 2600 7200 2600
Wire Wire Line
7050 2700 7200 2700
Wire Wire Line
7050 2800 7200 2800
Wire Wire Line
6550 2900 7200 2900
Wire Wire Line
7050 3000 7200 3000
Wire Wire Line
7050 3100 7200 3100
Wire Wire Line
6550 3200 7200 3200
Wire Wire Line
7050 3300 7200 3300
Wire Wire Line
7050 3400 7200 3400
Wire Wire Line
6550 3500 7200 3500
Wire Wire Line
7050 3600 7200 3600
Wire Wire Line
7050 3700 7200 3700
Wire Wire Line
6550 3800 7200 3800
Wire Wire Line
7050 3900 7200 3900
Wire Wire Line
7050 4000 7200 4000
Wire Wire Line
6550 4100 7200 4100
Wire Wire Line
7050 4200 7200 4200
Wire Wire Line
7050 4300 7200 4300
Wire Wire Line
6550 4400 7200 4400
Wire Wire Line
7050 4500 7200 4500
Wire Wire Line
7050 4600 7200 4600
Wire Wire Line
7200 4700 7100 4700
Wire Wire Line
7100 4700 7100 4750
Wire Wire Line
7100 4800 7200 4800
Wire Wire Line
7100 4750 6950 4750
Connection ~ 7100 4750
Wire Wire Line
7100 4750 7100 4800
Text GLabel 7050 4900 0 50 Input ~ 0
+3V3MP
Wire Wire Line
7200 4900 7050 4900
Text HLabel 7050 4600 0 50 Input ~ 0
EEM2_IIC_SCL
$EndSCHEMATC

43
MCU.sch
View File

@ -3,7 +3,7 @@ EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 7 8
Sheet 6 8
Title ""
Date ""
Rev ""
@ -1032,4 +1032,45 @@ F 3 "~" H 8200 3500 50 0001 C CNN
1 8200 3500
1 0 0 -1
$EndComp
$Comp
L Device:LED D22
U 1 1 62108C04
P 6450 5150
F 0 "D22" H 6443 4895 50 0000 C CNN
F 1 "LED_CPU" H 6443 4986 50 0000 C CNN
F 2 "" H 6450 5150 50 0001 C CNN
F 3 "~" H 6450 5150 50 0001 C CNN
1 6450 5150
-1 0 0 1
$EndComp
$Comp
L Device:R R132
U 1 1 6210A0E7
P 6850 5150
F 0 "R132" V 6643 5150 50 0000 C CNN
F 1 "100" V 6734 5150 50 0000 C CNN
F 2 "" V 6780 5150 50 0001 C CNN
F 3 "~" H 6850 5150 50 0001 C CNN
1 6850 5150
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0126
U 1 1 6210B2EE
P 7100 5250
F 0 "#PWR0126" H 7100 5000 50 0001 C CNN
F 1 "GND" H 7105 5077 50 0000 C CNN
F 2 "" H 7100 5250 50 0001 C CNN
F 3 "" H 7100 5250 50 0001 C CNN
1 7100 5250
1 0 0 -1
$EndComp
Wire Wire Line
7100 5250 7100 5150
Wire Wire Line
7100 5150 7000 5150
Wire Wire Line
6700 5150 6600 5150
Wire Wire Line
6300 5150 5000 5150
$EndSCHEMATC

2266
Power.sch

File diff suppressed because it is too large Load Diff

View File

@ -14,20 +14,20 @@ Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 7450 1050 600 1200
S 9150 5100 600 1200
U 60FB17F2
F0 "HighSpeedADC" 50
F1 "HighSpeedADC.sch" 50
F2 "ADC_CLK" I L 7450 1300 50
F3 "ADC_DATA1" I L 7450 1450 50
F4 "ADC_DATA2" I L 7450 1550 50
F5 "ADC_DATA3" I L 7450 1650 50
F6 "ADC_DATA4" I L 7450 1750 50
F7 "ADC_DATA5" I L 7450 1850 50
F8 "ADC_DATA6" I L 7450 1950 50
F9 "ADC_DATA7" I L 7450 2050 50
F10 "ADC_DATA8" I L 7450 2150 50
F11 "ADC_IN" I L 7450 1150 50
F2 "ADC_CLK" I L 9150 5350 50
F3 "ADC_DATA1" I L 9150 5500 50
F4 "ADC_DATA2" I L 9150 5600 50
F5 "ADC_DATA3" I L 9150 5700 50
F6 "ADC_DATA4" I L 9150 5800 50
F7 "ADC_DATA5" I L 9150 5900 50
F8 "ADC_DATA6" I L 9150 6000 50
F9 "ADC_DATA7" I L 9150 6100 50
F10 "ADC_DATA8" I L 9150 6200 50
F11 "ADC_IN" I L 9150 5200 50
$EndSheet
$Sheet
S 2900 5300 650 1000
@ -54,18 +54,13 @@ F5 "POE_SRC_Status" I L 1650 5900 50
F6 "POE_CPU_RESET" I L 1650 6000 50
$EndSheet
$Sheet
S 1650 6600 650 300
S 1650 6600 650 450
U 60E3407A
F0 "CurrentSenser" 50
F1 "CurrentSenser.sch" 50
F3 "12V_SW" I L 1650 6700 50
F4 "12V_CURRENT" I L 1650 6800 50
$EndSheet
$Sheet
S 7500 3050 750 1150
U 60CB9D41
F0 "Connectors" 50
F1 "Connectors.sch" 50
F2 "12V_SW" I L 1650 6700 50
F3 "12V_CURRENT" I L 1650 6800 50
F4 "12V_OUT" I L 1650 6950 50
$EndSheet
Wire Wire Line
2400 5500 2550 5500
@ -230,78 +225,138 @@ F46 "FPGA_EEM2_2_P" I R 6150 4950 50
F47 "FPGA_EEM2_2_N" I R 6150 5050 50
F48 "FPGA_EEM2_1_P" I R 6150 4750 50
F49 "FPGA_EEM2_1_N" I R 6150 4850 50
F50 "FPGA_IIC0_SDA" I R 6150 2650 50
F51 "FPGA_IIC0_SCL" I R 6150 2550 50
F52 "FPGA_IIC1_SDA" I R 6150 4450 50
F53 "FPGA_IIC1_SCL" I R 6150 4350 50
F54 "FPGA_IIC2_SDA" I R 6150 6250 50
F55 "FPGA_IIC2_SCL" I R 6150 6150 50
F56 "FPGA_FSMC_A0" I L 4650 950 50
F57 "FPGA_FSMC_A1" I L 4650 1050 50
F58 "FPGA_FSMC_A2" I L 4650 1150 50
F59 "FPGA_FSMC_A3" I L 4650 1250 50
F60 "FPGA_FSMC_A4" I L 4650 1350 50
F61 "FPGA_FSMC_A5" I L 4650 1450 50
F62 "FPGA_FSMC_A6" I L 4650 1550 50
F63 "FPGA_FSMC_A7" I L 4650 1650 50
F64 "FPGA_FSMC_D0" I L 4650 1750 50
F65 "FPGA_FSMC_D1" I L 4650 1850 50
F66 "FPGA_FSMC_D2" I L 4650 1950 50
F67 "FPGA_FSMC_D3" I L 4650 2050 50
F68 "FPGA_FSMC_D4" I L 4650 2150 50
F69 "FPGA_FSMC_D5" I L 4650 2250 50
F70 "FPGA_FSMC_D6" I L 4650 2350 50
F71 "FPGA_FSMC_D7" I L 4650 2450 50
F72 "FPGA_FSMC_D8" I L 4650 2550 50
F73 "FPGA_FSMC_D9" I L 4650 2650 50
F74 "FPGA_FSMC_D10" I L 4650 2750 50
F75 "FPGA_FSMC_D11" I L 4650 2850 50
F76 "FPGA_FSMC_D12" I L 4650 2950 50
F77 "FPGA_FSMC_D13" I L 4650 3050 50
F78 "FPGA_FSMC_D14" I L 4650 3150 50
F79 "FPGA_FSMC_D15" I L 4650 3250 50
F80 "FPGA_CSBSEL0" I L 4650 4250 50
F81 "FPGA_CSBSEL1" I L 4650 4350 50
F82 "FPGA_SPI_SDO" I L 4650 4450 50
F83 "FPGA_SPI_SDI" I L 4650 4550 50
F84 "FPGA_SPI_SS" I L 4650 4650 50
F85 "FPGA_SPI_SCK" I L 4650 4750 50
F86 "FPGA_CDONE" I L 4650 4850 50
F87 "FPGA_CRESET" I L 4650 4950 50
F88 "FPGA_IIC3_SDA" I L 4650 5200 50
F89 "FPGA_IIC3_SCL" I L 4650 5100 50
F90 "FPGA_ADC_D0" I R 6150 6400 50
F91 "FPGA_ADC_D1" I R 6150 6500 50
F92 "FPGA_ADC_D2" I R 6150 6600 50
F93 "FPGA_ADC_D3" I R 6150 6700 50
F94 "FPGA_ADC_D4" I R 6150 6800 50
F95 "FPGA_ADC_D5" I R 6150 6900 50
F96 "FPGA_ADC_D6" I R 6150 7000 50
F97 "FPGA_ADC_D7" I R 6150 7100 50
F98 "FPGA_ADC_CLK" I R 6150 7200 50
F99 "FPGA_FSMC_NWE" I L 4650 3400 50
F100 "FPGA_FSMC_NOE" I L 4650 3500 50
F101 "FPGA_FSMC_NE1" I L 4650 3600 50
F102 "FPGA_FSMC_NBL0" I L 4650 3700 50
F103 "FPGA_FSMC_NBL1" I L 4650 3800 50
F104 "FPGA_FSMC_NL" I L 4650 3900 50
F105 "FPGA_FSMC_CLK" I L 4650 4000 50
F106 "FPGA_FSMC_NWAIT" I L 4650 4100 50
F107 "FPGA_IO0" I L 4650 5350 50
F108 "FPGA_IO1" I L 4650 5450 50
F109 "FPGA_IO2" I L 4650 5550 50
F110 "FPGA_IO3" I L 4650 5650 50
F111 "FPGA_IO4" I L 4650 5750 50
F112 "FPGA_IO5" I L 4650 5850 50
F113 "FPGA_IO6" I L 4650 5950 50
F114 "FPGA_IO7" I L 4650 6050 50
F115 "FPGA_IO8" I L 4650 6150 50
F116 "FPGA_IO9" I L 4650 6250 50
F117 "FPGA_IO10" I L 4650 6350 50
F118 "FPGA_IO11" I L 4650 6450 50
F119 "FPGA_IO12" I L 4650 6550 50
F120 "FPGA_IO13" I L 4650 6650 50
F121 "FPGA_IO14" I L 4650 6750 50
F122 "FPGA_IO15" I L 4650 6850 50
F50 "FPGA_FSMC_A0" I L 4650 950 50
F51 "FPGA_FSMC_A1" I L 4650 1050 50
F52 "FPGA_FSMC_A2" I L 4650 1150 50
F53 "FPGA_FSMC_A3" I L 4650 1250 50
F54 "FPGA_FSMC_A4" I L 4650 1350 50
F55 "FPGA_FSMC_A5" I L 4650 1450 50
F56 "FPGA_FSMC_A6" I L 4650 1550 50
F57 "FPGA_FSMC_A7" I L 4650 1650 50
F58 "FPGA_FSMC_D0" I L 4650 1750 50
F59 "FPGA_FSMC_D1" I L 4650 1850 50
F60 "FPGA_FSMC_D2" I L 4650 1950 50
F61 "FPGA_FSMC_D3" I L 4650 2050 50
F62 "FPGA_FSMC_D4" I L 4650 2150 50
F63 "FPGA_FSMC_D5" I L 4650 2250 50
F64 "FPGA_FSMC_D6" I L 4650 2350 50
F65 "FPGA_FSMC_D7" I L 4650 2450 50
F66 "FPGA_FSMC_D8" I L 4650 2550 50
F67 "FPGA_FSMC_D9" I L 4650 2650 50
F68 "FPGA_FSMC_D10" I L 4650 2750 50
F69 "FPGA_FSMC_D11" I L 4650 2850 50
F70 "FPGA_FSMC_D12" I L 4650 2950 50
F71 "FPGA_FSMC_D13" I L 4650 3050 50
F72 "FPGA_FSMC_D14" I L 4650 3150 50
F73 "FPGA_FSMC_D15" I L 4650 3250 50
F74 "FPGA_CSBSEL0" I L 4650 4250 50
F75 "FPGA_CSBSEL1" I L 4650 4350 50
F76 "FPGA_SPI_SDO" I L 4650 4450 50
F77 "FPGA_SPI_SDI" I L 4650 4550 50
F78 "FPGA_SPI_SS" I L 4650 4650 50
F79 "FPGA_SPI_SCK" I L 4650 4750 50
F80 "FPGA_CDONE" I L 4650 4850 50
F81 "FPGA_CRESET" I L 4650 4950 50
F82 "FPGA_ADC_D0" I R 6150 6400 50
F83 "FPGA_ADC_D1" I R 6150 6500 50
F84 "FPGA_ADC_D2" I R 6150 6600 50
F85 "FPGA_ADC_D3" I R 6150 6700 50
F86 "FPGA_ADC_D4" I R 6150 6800 50
F87 "FPGA_ADC_D5" I R 6150 6900 50
F88 "FPGA_ADC_D6" I R 6150 7000 50
F89 "FPGA_ADC_D7" I R 6150 7100 50
F90 "FPGA_ADC_CLK" I R 6150 7200 50
F91 "FPGA_FSMC_NWE" I L 4650 3400 50
F92 "FPGA_FSMC_NOE" I L 4650 3500 50
F93 "FPGA_FSMC_NE1" I L 4650 3600 50
F94 "FPGA_FSMC_NBL0" I L 4650 3700 50
F95 "FPGA_FSMC_NBL1" I L 4650 3800 50
F96 "FPGA_FSMC_NL" I L 4650 3900 50
F97 "FPGA_FSMC_CLK" I L 4650 4000 50
F98 "FPGA_FSMC_NWAIT" I L 4650 4100 50
F99 "FPGA_IO0" I L 4650 5350 50
F100 "FPGA_IO1" I L 4650 5450 50
F101 "FPGA_IO2" I L 4650 5550 50
F102 "FPGA_IO3" I L 4650 5650 50
F103 "FPGA_IO4" I L 4650 5750 50
F104 "FPGA_IO5" I L 4650 5850 50
F105 "FPGA_IO6" I L 4650 5950 50
F106 "FPGA_IO7" I L 4650 6050 50
F107 "FPGA_IO8" I L 4650 6150 50
F108 "FPGA_IO9" I L 4650 6250 50
F109 "FPGA_IO10" I L 4650 6350 50
F110 "FPGA_IO11" I L 4650 6450 50
F111 "FPGA_IO12" I L 4650 6550 50
F112 "FPGA_IO13" I L 4650 6650 50
F113 "FPGA_IO14" I L 4650 6750 50
F114 "FPGA_IO15" I L 4650 6850 50
F115 "FPGA_EEM0_IIC_SDA" I R 6150 2550 50
F116 "FPGA_EEM0_IIC_SCL" I R 6150 2650 50
F117 "FPGA_EEM1_IIC_SDA" I R 6150 4350 50
F118 "FPGA_EEM1_IIC_SCL" I R 6150 4450 50
F119 "FPGA_EEM2_IIC_SDA" I R 6150 6150 50
F120 "FPGA_EEM2_IIC_SCL" I R 6150 6250 50
F121 "FPGA_IIC_SDA" I L 4650 5100 50
F122 "FPGA_IIC_SCL" I L 4650 5200 50
$EndSheet
$Sheet
S 7250 850 900 5550
U 60CB9D41
F0 "LVDS" 50
F1 "LVDS.sch" 50
F2 "EEM0_0_P" I L 7250 950 50
F3 "EEM0_0_N" I L 7250 1050 50
F4 "EEM0_1_P" I L 7250 1150 50
F5 "EEM0_1_N" I L 7250 1250 50
F6 "EEM0_2_P" I L 7250 1350 50
F7 "EEM0_2_N" I L 7250 1450 50
F8 "EEM0_3_P" I L 7250 1550 50
F9 "EEM0_3_N" I L 7250 1650 50
F10 "EEM0_4_P" I L 7250 1750 50
F11 "EEM0_4_N" I L 7250 1850 50
F12 "EEM0_5_P" I L 7250 1950 50
F13 "EEM0_5_N" I L 7250 2050 50
F14 "EEM0_6_P" I L 7250 2150 50
F15 "EEM0_6_N" I L 7250 2250 50
F16 "EEM0_7_P" I L 7250 2350 50
F17 "EEM0_7_N" I L 7250 2450 50
F18 "EEM0_IIC_SDA" I L 7250 2550 50
F19 "EEM0_IIC_SCL" I L 7250 2650 50
F20 "EEM1_0_P" I L 7250 2750 50
F21 "EEM1_0_N" I L 7250 2850 50
F22 "EEM1_1_P" I L 7250 2950 50
F23 "EEM1_1_N" I L 7250 3050 50
F24 "EEM1_2_P" I L 7250 3150 50
F25 "EEM1_2_N" I L 7250 3250 50
F26 "EEM1_3_P" I L 7250 3350 50
F27 "EEM1_3_N" I L 7250 3450 50
F28 "EEM1_4_P" I L 7250 3550 50
F29 "EEM1_4_N" I L 7250 3650 50
F30 "EEM1_5_P" I L 7250 3750 50
F31 "EEM1_5_N" I L 7250 3850 50
F32 "EEM1_6_P" I L 7250 3950 50
F33 "EEM1_6_N" I L 7250 4050 50
F34 "EEM1_7_P" I L 7250 4150 50
F35 "EEM1_7_N" I L 7250 4250 50
F36 "EEM1_IIC_SDA" I L 7250 4350 50
F37 "EEM1_IIC_SCL" I L 7250 4450 50
F38 "EEM2_0_P" I L 7250 4550 50
F39 "EEM2_0_N" I L 7250 4650 50
F40 "EEM2_1_P" I L 7250 4750 50
F41 "EEM2_1_N" I L 7250 4850 50
F42 "EEM2_2_P" I L 7250 4950 50
F43 "EEM2_2_N" I L 7250 5050 50
F44 "EEM2_3_P" I L 7250 5150 50
F45 "EEM2_3_N" I L 7250 5250 50
F46 "EEM2_4_P" I L 7250 5350 50
F47 "EEM2_4_N" I L 7250 5450 50
F48 "EEM2_5_P" I L 7250 5550 50
F49 "EEM2_5_N" I L 7250 5650 50
F50 "EEM2_6_P" I L 7250 5750 50
F51 "EEM2_6_N" I L 7250 5850 50
F52 "EEM2_7_P" I L 7250 5950 50
F53 "EEM2_7_N" I L 7250 6050 50
F54 "EEM2_IIC_SDA" I L 7250 6150 50
F55 "EEM2_IIC_SCL" I L 7250 6250 50
$EndSheet
$EndSCHEMATC