2021-07-23 17:31:28 +08:00
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#![no_std]
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#![no_main]
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2021-08-12 11:09:58 +08:00
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// use cortex_m::{asm, singleton};
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pub mod serial;
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use core::str;
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use core::fmt::Write;
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// use nb::block;
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2021-07-29 15:57:52 +08:00
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extern crate panic_itm;
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2021-08-12 11:09:58 +08:00
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// use cortex_m::{iprintln, iprint};
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use cortex_m_rt::entry;
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2021-07-29 15:57:52 +08:00
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use embedded_hal::{
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digital::v2::OutputPin,
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// blocking::delay::DelayMs
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};
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// use stm32f1xx_hal::spi::SpiRegisterBlock;
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use stm32f1xx_hal::{
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afio::AfioExt,
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rcc::RccExt,
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flash::FlashExt,
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gpio::GpioExt,
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time::U32Ext,
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2021-08-12 11:09:58 +08:00
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// stm32::ITM,
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2021-07-29 15:57:52 +08:00
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delay::Delay,
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spi::Spi,
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2021-08-12 11:09:58 +08:00
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pac,
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// adc,
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prelude::*
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2021-07-29 15:57:52 +08:00
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// time::Hertz
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};
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use enc424j600::smoltcp_phy;
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use smoltcp::wire::{
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EthernetAddress, IpAddress, IpCidr, Ipv6Cidr
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};
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2021-08-12 11:09:58 +08:00
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use smoltcp::iface::{
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NeighborCache,
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EthernetInterfaceBuilder,
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// EthernetInterface
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};
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2021-07-29 15:57:52 +08:00
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use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
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/// Timer
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use core::cell::RefCell;
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use cortex_m::interrupt::Mutex;
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use cortex_m_rt::exception;
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use stm32f1xx_hal::{
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rcc::Clocks,
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time::MilliSeconds,
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timer::{Timer, Event as TimerEvent},
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2021-08-12 11:09:58 +08:00
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stm32::SYST,
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serial::{
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Config,
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Serial,
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// Tx
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},
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// dma::*,
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// dma::dma1::*,
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// pac::*
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// dma::Half
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2021-07-29 15:57:52 +08:00
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};
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use smoltcp::time::Instant;
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/// Rate in Hz
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const TIMER_RATE: u32 = 20;
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/// Interval duration in milliseconds
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const TIMER_DELTA: u32 = 1000 / TIMER_RATE;
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/// Elapsed time in milliseconds
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static TIMER_MS: Mutex<RefCell<u32>> = Mutex::new(RefCell::new(0));
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/// Setup SysTick exception
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fn timer_setup(syst: SYST, clocks: Clocks) {
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let timer = Timer::syst(syst, &clocks);
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timer.start_count_down(TIMER_RATE.hz()).listen(TimerEvent::Update);
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}
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/// SysTick exception (Timer)
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#[exception]
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fn SysTick() {
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cortex_m::interrupt::free(|cs| {
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*TIMER_MS.borrow(cs)
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.borrow_mut() += TIMER_DELTA;
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});
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}
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/// Obtain current time in milliseconds
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pub fn timer_now() -> MilliSeconds {
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let ms = cortex_m::interrupt::free(|cs| {
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*TIMER_MS.borrow(cs)
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.borrow()
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});
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ms.ms()
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}
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///spi
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use stm32f1xx_hal::{
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stm32::SPI1,
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spi::Spi1Remap,
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gpio::{
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gpiob::{PB3, PB4, PB5},
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gpioc::PC13,
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Alternate, Output, PushPull, Input, Floating
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2021-07-23 17:31:28 +08:00
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}
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2021-07-29 15:57:52 +08:00
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};
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type SpiEth = enc424j600::Enc424j600<
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Spi<SPI1, Spi1Remap, (PB3<Alternate<PushPull>>, PB4<Input<Floating>>, PB5<Alternate<PushPull>>)>,
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PC13<Output<PushPull>>
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>;
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pub struct NetStorage {
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ip_addrs: [IpCidr; 1],
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neighbor_cache: [Option<(IpAddress, smoltcp::iface::Neighbor)>; 8],
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2021-07-23 17:31:28 +08:00
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}
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2021-07-29 15:57:52 +08:00
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static mut NET_STORE: NetStorage = NetStorage {
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// Placeholder for the real IP address, which is initialized at runtime.
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ip_addrs: [IpCidr::Ipv6(
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Ipv6Cidr::SOLICITED_NODE_PREFIX,
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)],
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neighbor_cache: [None; 8],
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};
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2021-08-12 11:09:58 +08:00
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#[entry()]
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fn main() -> ! {
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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cp.SCB.enable_icache();
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cp.SCB.enable_dcache(&mut cp.CPUID);
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// Enable monotonic timer CYCCNT
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cp.DWT.enable_cycle_counter();
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cp.DCB.enable_trace();
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let mut flash = dp.FLASH.constrain();
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let mut rcc = dp.RCC.constrain();
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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let dma1_chs = dp.DMA1.split(&mut rcc.ahb);
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let clocks = rcc
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.cfgr
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.use_hse(8.mhz())
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.sysclk(72.mhz())
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.hclk(72.mhz())
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.pclk1(36.mhz())
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.pclk2(72.mhz())
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.adcclk(2.mhz())
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.freeze(&mut flash.acr);
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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let mut delay = Delay::new(cp.SYST, clocks);
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let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
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let mut gpiob = dp.GPIOB.split(&mut rcc.apb2);
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let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
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let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
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// USART1
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let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
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let rx = gpioa.pa10;
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// Set up the usart device. Taks ownership over the USART register and tx/rx pins. The rest of
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// the registers are used to enable and configure the device.
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let serial = Serial::usart1(
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dp.USART1,
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(tx, rx),
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&mut afio.mapr,
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Config::default().baudrate(9600.bps()),
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clocks,
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&mut rcc.apb2,
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);
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// let mut serial_tx = serial.split().0.with_dma(dma1_chs.4);
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let mut serial_tx = serial.split().0;
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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// let dma_ch1 = dma1_chs.1;
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// // Setup ADC
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// let adc1 = adc::Adc::adc1(dp.ADC1, &mut rcc.apb2, clocks);
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// // Setup GPIOA
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// // Configure pa0 as an analog input
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// let adc_ch15 = gpioc.pc5.into_analog(&mut gpioc.crl);
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// let adc_dma = adc1.with_dma(adc_ch15, dma_ch1);
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// let buf = singleton!(: [u16; 8] = [0; 8]).unwrap();
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// let (_buf, adc_dma) = adc_dma.read(buf).wait();
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// let (_adc1, _adc_ch15, _dma_ch1) = adc_dma.split();
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// // let buf = singleton!(: [[u16; 8]; 2] = [[0; 8]; 2]).unwrap();
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// // let mut circ_buffer = adc_dma.circ_read(buf);
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// // while circ_buffer.readable_half().unwrap() != Half::First {}
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// // let _first_half = circ_buffer.peek(|half, _| *half).unwrap();
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// // while circ_buffer.readable_half().unwrap() != Half::Second {}
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// // let _second_half = circ_buffer.peek(|half, _| *half).unwrap();
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// // let (_buf, adc_dma) = circ_buffer.stop();
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// // let (_adc1, _adc_ch15, _dma_ch1) = adc_dma.split();
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// Init ITM
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// let mut itm = cp.ITM;
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// let stim0 = &mut itm.stim[0];
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// iprintln!(stim0,
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// "Eth TCP Server on STM32-F103 via NIC100/ENC424J600");
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// NIC100 / ENC424J600 Set-up
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let spi1 = dp.SPI1;
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let (_pa15, pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4);
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let spi1_sck = pb3.into_alternate_push_pull(&mut gpiob.crl);
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let spi1_miso = pb4;//.into_floating_input(&mut gpiob.crl);
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let spi1_mosi = gpiob.pb5.into_alternate_push_pull(&mut gpiob.crl);
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let spi1_nss = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
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// Create SPI1 for HAL
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let eth_iface = {
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let mut spi_eth = {
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let spi_eth_port = Spi::spi1(
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spi1,
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(spi1_sck, spi1_miso, spi1_mosi),
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&mut afio.mapr,
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enc424j600::spi::interfaces::SPI_MODE,
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// Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
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9.mhz(),
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clocks,
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&mut rcc.apb2,);
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SpiEth::new(spi_eth_port, spi1_nss)
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.cpu_freq_mhz(72)
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};
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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// Init controller
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match spi_eth.reset(&mut delay) {
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Ok(_) => {
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// iprintln!(stim0, "Initializing Ethernet...")
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serial_tx.write_fmt(format_args!("Initializing Ethernet...\n")).unwrap();
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2021-07-29 15:57:52 +08:00
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}
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2021-08-12 11:09:58 +08:00
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Err(_) => {
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panic!("Ethernet initialization failed!")
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2021-07-29 15:57:52 +08:00
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}
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2021-08-12 11:09:58 +08:00
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}
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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// Read MAC
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let mut eth_mac_addr: [u8; 6] = [0; 6];
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spi_eth.read_mac_addr(&mut eth_mac_addr).unwrap();
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for i in 0..6 {
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let byte = eth_mac_addr[i];
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match i {
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// 0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
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// 1..=4 => iprint!(stim0, "{:02x}-", byte),
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// 5 => iprint!(stim0, "{:02x}\n", byte),
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0 => {
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serial_tx.write_fmt(format_args!("MAC Address = {:02x}-", byte)).unwrap();
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},
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1..=4 => {
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serial_tx.write_fmt(format_args!("{:02x}-", byte)).unwrap();
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},
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5 => {
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serial_tx.write_fmt(format_args!("{:02x}\n", byte)).unwrap();
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},
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_ => ()
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};
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}
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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// Init Rx/Tx buffers
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spi_eth.init_rxbuf().unwrap();
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spi_eth.init_txbuf().unwrap();
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// iprintln!(stim0, "Ethernet controller initialized");
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serial_tx.write_fmt(format_args!("Ethernet controller initialized\n")).unwrap();
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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// Init smoltcp interface
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let eth_iface = {
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let device = smoltcp_phy::SmoltcpDevice::new(spi_eth);
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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let store = unsafe { &mut NET_STORE };
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store.ip_addrs[0] = IpCidr::new(IpAddress::v4(192, 168, 1, 88), 24);
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let neighbor_cache = NeighborCache::new(&mut store.neighbor_cache[..]);
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EthernetInterfaceBuilder::new(device)
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.ethernet_addr(EthernetAddress(eth_mac_addr))
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.neighbor_cache(neighbor_cache)
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.ip_addrs(&mut store.ip_addrs[..])
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.finalize()
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2021-07-29 15:57:52 +08:00
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};
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2021-08-12 11:09:58 +08:00
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// iprintln!(stim0, "Ethernet interface initialized");
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serial_tx.write_fmt(format_args!("Ethernet interface initialized\n")).unwrap();
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eth_iface
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};
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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// Setup SysTick after releasing SYST from Delay
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// Reference to stm32-eth:examples/ip.rs
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timer_setup(delay.free(), clocks);
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// iprintln!(stim0, "Timer initialized");
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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let mut led = gpioc.pc0.into_push_pull_output(&mut gpioc.crl);
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led.set_high().unwrap();
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2021-07-29 15:57:52 +08:00
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2021-08-12 11:09:58 +08:00
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loop {
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// let stim0 = &mut c.resources.itm.stim[0];
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let mut iface = eth_iface;
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2021-07-29 15:57:52 +08:00
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// Copied / modified from smoltcp:
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// examples/loopback.rs
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let echo_socket = {
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static mut TCP_SERVER_RX_DATA: [u8; 1024] = [0; 1024];
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static mut TCP_SERVER_TX_DATA: [u8; 1024] = [0; 1024];
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let tcp_rx_buffer = TcpSocketBuffer::new(unsafe { &mut TCP_SERVER_RX_DATA[..] });
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let tcp_tx_buffer = TcpSocketBuffer::new(unsafe { &mut TCP_SERVER_TX_DATA[..] });
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TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer)
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};
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let greet_socket = {
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static mut TCP_SERVER_RX_DATA: [u8; 256] = [0; 256];
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static mut TCP_SERVER_TX_DATA: [u8; 256] = [0; 256];
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let tcp_rx_buffer = TcpSocketBuffer::new(unsafe { &mut TCP_SERVER_RX_DATA[..] });
|
|
|
|
let tcp_tx_buffer = TcpSocketBuffer::new(unsafe { &mut TCP_SERVER_TX_DATA[..] });
|
|
|
|
TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer)
|
|
|
|
};
|
|
|
|
let mut socket_set_entries = [None, None];
|
|
|
|
let mut socket_set = SocketSet::new(&mut socket_set_entries[..]);
|
|
|
|
let greet_handle = socket_set.add(greet_socket);
|
|
|
|
{
|
|
|
|
let store = unsafe { &mut NET_STORE };
|
2021-08-12 11:09:58 +08:00
|
|
|
// iprintln!(stim0,
|
|
|
|
// "TCP sockets will listen at {}", store.ip_addrs[0].address());
|
|
|
|
serial_tx.write_fmt(format_args!("TCP sockets will listen at {}\n", store.ip_addrs[0].address())).unwrap();
|
2021-07-29 15:57:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Copied / modified from:
|
|
|
|
// smoltcp:examples/loopback.rs, examples/server.rs;
|
|
|
|
// stm32-eth:examples/ip.rs,
|
|
|
|
// git.m-labs.hk/M-Labs/tnetplug
|
|
|
|
loop {
|
|
|
|
// Poll
|
|
|
|
let now = timer_now().0;
|
|
|
|
let instant = Instant::from_millis(now as i64);
|
|
|
|
match iface.poll(&mut socket_set, instant) {
|
|
|
|
Ok(_) => {
|
|
|
|
},
|
|
|
|
Err(e) => {
|
2021-08-12 11:09:58 +08:00
|
|
|
// iprintln!(stim0, "[{}] Poll error: {:?}", instant, e)
|
|
|
|
serial_tx.write_fmt(format_args!("[{}] Poll error: {:?}\n", instant, e)).unwrap();
|
2021-07-29 15:57:52 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
// Control the "greeting" socket (:4321)
|
|
|
|
{
|
|
|
|
let mut socket = socket_set.get::<TcpSocket>(greet_handle);
|
|
|
|
if !socket.is_open() {
|
2021-08-12 11:09:58 +08:00
|
|
|
// iprintln!(stim0,
|
|
|
|
// "[{}] Listening to port 4321 for greeting, \
|
|
|
|
// please connect to the port", instant);
|
|
|
|
serial_tx.write_fmt(format_args!("[{}] Listening to port 4321 for greeting, please connect to the port\n", instant)).unwrap();
|
2021-07-29 15:57:52 +08:00
|
|
|
socket.listen(4321).unwrap();
|
2021-08-12 11:09:58 +08:00
|
|
|
// socket.set_timeout(Some(smoltcp::time::Duration::from_millis(10000)));
|
2021-07-29 15:57:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if socket.can_send() {
|
|
|
|
let greeting = "Welcome to the server demo for STM32F103!";
|
|
|
|
write!(socket, "{}\n", greeting).unwrap();
|
2021-08-12 11:09:58 +08:00
|
|
|
// iprintln!(stim0,
|
|
|
|
// "[{}] Greeting sent, socket closed", instant);
|
|
|
|
serial_tx.write_fmt(format_args!("[{}] Greeting sent, socket closed\n", instant)).unwrap();
|
2021-07-29 15:57:52 +08:00
|
|
|
socket.close();
|
|
|
|
}
|
2021-08-12 11:09:58 +08:00
|
|
|
|
|
|
|
if socket.can_recv() {
|
|
|
|
// iprintln!(stim0,
|
|
|
|
// "[{}] Received packet: {:?}", instant, socket.recv(|buffer| {
|
|
|
|
// (buffer.len(), str::from_utf8(buffer).unwrap())
|
|
|
|
// }));
|
|
|
|
serial_tx.write_fmt(format_args!("[{}] Received packet: {:?}\n",
|
|
|
|
instant, socket.recv(|buffer| {(buffer.len(), str::from_utf8(buffer).unwrap())}))).unwrap();
|
|
|
|
}
|
2021-07-29 15:57:52 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2021-08-12 11:09:58 +08:00
|
|
|
}
|