642 lines
25 KiB
Plaintext
642 lines
25 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.9 (git sha1 1979e0b)
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-- Executing script file `top.ys' --
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1. Executing Verilog-2005 frontend: top.v
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Parsing Verilog input from `top.v' to AST representation.
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Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.
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Yosys does support them but it is recommended to use `ifdef constructs instead!
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Generating RTLIL representation for module `\top'.
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Successfully finished Verilog frontend.
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2. Executing ATTRMAP pass (move or copy attributes).
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3. Executing SYNTH_ICE40 pass.
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3.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
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Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\SB_IO'.
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Generating RTLIL representation for module `\SB_GB_IO'.
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Generating RTLIL representation for module `\SB_GB'.
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Generating RTLIL representation for module `\SB_LUT4'.
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Generating RTLIL representation for module `\SB_CARRY'.
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Generating RTLIL representation for module `\SB_DFF'.
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Generating RTLIL representation for module `\SB_DFFE'.
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Generating RTLIL representation for module `\SB_DFFSR'.
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Generating RTLIL representation for module `\SB_DFFR'.
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Generating RTLIL representation for module `\SB_DFFSS'.
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Generating RTLIL representation for module `\SB_DFFS'.
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Generating RTLIL representation for module `\SB_DFFESR'.
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Generating RTLIL representation for module `\SB_DFFER'.
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Generating RTLIL representation for module `\SB_DFFESS'.
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Generating RTLIL representation for module `\SB_DFFES'.
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Generating RTLIL representation for module `\SB_DFFN'.
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Generating RTLIL representation for module `\SB_DFFNE'.
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Generating RTLIL representation for module `\SB_DFFNSR'.
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Generating RTLIL representation for module `\SB_DFFNR'.
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Generating RTLIL representation for module `\SB_DFFNSS'.
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Generating RTLIL representation for module `\SB_DFFNS'.
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Generating RTLIL representation for module `\SB_DFFNESR'.
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Generating RTLIL representation for module `\SB_DFFNER'.
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Generating RTLIL representation for module `\SB_DFFNESS'.
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Generating RTLIL representation for module `\SB_DFFNES'.
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Generating RTLIL representation for module `\SB_RAM40_4K'.
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Generating RTLIL representation for module `\SB_RAM40_4KNR'.
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Generating RTLIL representation for module `\SB_RAM40_4KNW'.
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Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
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Generating RTLIL representation for module `\ICESTORM_LC'.
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Generating RTLIL representation for module `\SB_PLL40_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
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Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
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Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
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Generating RTLIL representation for module `\SB_WARMBOOT'.
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Generating RTLIL representation for module `\SB_SPRAM256KA'.
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Generating RTLIL representation for module `\SB_HFOSC'.
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Generating RTLIL representation for module `\SB_LFOSC'.
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Generating RTLIL representation for module `\SB_RGBA_DRV'.
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Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
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Generating RTLIL representation for module `\SB_RGB_DRV'.
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Generating RTLIL representation for module `\SB_I2C'.
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Generating RTLIL representation for module `\SB_SPI'.
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Generating RTLIL representation for module `\SB_LEDDA_IP'.
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Generating RTLIL representation for module `\SB_FILTER_50NS'.
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Generating RTLIL representation for module `\SB_IO_I3C'.
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Generating RTLIL representation for module `\SB_IO_OD'.
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Generating RTLIL representation for module `\SB_MAC16'.
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Successfully finished Verilog frontend.
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3.2. Executing HIERARCHY pass (managing design hierarchy).
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3.2.1. Analyzing design hierarchy..
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Top module: \top
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3.2.2. Analyzing design hierarchy..
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Top module: \top
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Removed 0 unused modules.
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3.3. Executing PROC pass (convert processes to netlists).
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3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Removed a total of 0 dead cases.
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3.3.3. Executing PROC_INIT pass (extract init attributes).
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Found init rule in `\top.$proc$top.v:31$9'.
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Set init value: \int_rst = 1'1
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3.3.4. Executing PROC_ARST pass (detect async resets in processes).
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3.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\top.$proc$top.v:31$9'.
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1/1: $1\int_rst[0:0]
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Creating decoders for process `\top.$proc$top.v:56$8'.
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1/1: $0\int_rst[0:0]
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3.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).
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3.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\top.\int_rst' using process `\top.$proc$top.v:56$8'.
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created $dff cell `$procdff$10' with positive edge clock.
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3.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `top.$proc$top.v:31$9'.
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Removing empty process `top.$proc$top.v:56$8'.
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Cleaned up 0 empty switches.
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3.4. Executing FLATTEN pass (flatten design).
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No more expansions possible.
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3.5. Executing TRIBUF pass.
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3.6. Executing DEMINOUT pass (demote inout ports to input or output).
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3.7. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.8. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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Removed 1 unused cells and 9 unused wires.
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<suppressed ~2 debug messages>
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3.9. Executing CHECK pass (checking for obvious problems).
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checking module top..
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found and reported 0 problems.
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3.10. Executing OPT pass (performing simple optimizations).
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3.10.1. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.10.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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Running muxtree optimizer on module \top..
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Creating internal representation of mux trees.
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No muxes found in this module.
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Removed 0 multiplexer ports.
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3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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Optimizing cells in module \top.
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Performed a total of 0 changes.
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3.10.5. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
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Promoting init spec \int_rst = 1'1 to constant driver in module top.
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Promoted 1 init specs to constant drivers.
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3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.10.8. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.10.9. Rerunning OPT passes. (Maybe there is more to do..)
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3.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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Running muxtree optimizer on module \top..
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Creating internal representation of mux trees.
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No muxes found in this module.
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Removed 0 multiplexer ports.
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3.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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Optimizing cells in module \top.
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Performed a total of 0 changes.
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3.10.12. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.10.13. Executing OPT_RMDFF pass (remove dff with constant values).
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3.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.10.15. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.10.16. Finished OPT passes. (There is nothing left to do.)
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3.11. Executing WREDUCE pass (reducing word size of cells).
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3.12. Executing PEEPOPT pass (run peephole optimizers).
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3.13. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.14. Executing SHARE pass (SAT-based resource sharing).
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3.15. Executing TECHMAP pass (map to technology primitives).
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3.15.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
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Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
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Generating RTLIL representation for module `\_90_lut_cmp_'.
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Successfully finished Verilog frontend.
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3.15.2. Continuing TECHMAP pass.
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No more expansions possible.
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3.16. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.17. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.18. Executing ALUMACC pass (create $alu and $macc cells).
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Extracting $alu and $macc cells in module top:
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created 0 $alu and 0 $macc cells.
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3.19. Executing OPT pass (performing simple optimizations).
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3.19.1. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.19.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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Running muxtree optimizer on module \top..
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Creating internal representation of mux trees.
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No muxes found in this module.
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Removed 0 multiplexer ports.
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3.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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Optimizing cells in module \top.
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Performed a total of 0 changes.
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3.19.5. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.19.6. Executing OPT_RMDFF pass (remove dff with constant values).
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3.19.7. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.19.8. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.19.9. Finished OPT passes. (There is nothing left to do.)
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3.20. Executing FSM pass (extract and optimize FSM).
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3.20.1. Executing FSM_DETECT pass (finding FSMs in design).
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3.20.2. Executing FSM_EXTRACT pass (extracting FSM from design).
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3.20.3. Executing FSM_OPT pass (simple optimizations of FSMs).
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3.20.4. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.20.5. Executing FSM_OPT pass (simple optimizations of FSMs).
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3.20.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
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3.20.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
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3.20.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
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3.21. Executing OPT pass (performing simple optimizations).
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3.21.1. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.21.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.21.3. Executing OPT_RMDFF pass (remove dff with constant values).
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3.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.21.5. Finished fast OPT passes.
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3.22. Executing MEMORY pass.
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3.22.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
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3.22.2. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.22.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
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3.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.22.5. Executing MEMORY_COLLECT pass (generating $mem cells).
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3.23. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
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3.25. Executing TECHMAP pass (map to technology primitives).
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3.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
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Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
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Generating RTLIL representation for module `\$__ICE40_RAM4K'.
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Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
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Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
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Successfully finished Verilog frontend.
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3.25.2. Continuing TECHMAP pass.
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No more expansions possible.
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3.26. Executing ICE40_BRAMINIT pass.
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3.27. Executing OPT pass (performing simple optimizations).
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3.27.1. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.27.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.27.3. Executing OPT_RMDFF pass (remove dff with constant values).
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3.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.27.5. Finished fast OPT passes.
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3.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
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3.29. Executing OPT pass (performing simple optimizations).
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3.29.1. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.29.2. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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Running muxtree optimizer on module \top..
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Creating internal representation of mux trees.
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No muxes found in this module.
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Removed 0 multiplexer ports.
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3.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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Optimizing cells in module \top.
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Performed a total of 0 changes.
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3.29.5. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.29.6. Executing OPT_RMDFF pass (remove dff with constant values).
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3.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \top..
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3.29.8. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.29.9. Finished OPT passes. (There is nothing left to do.)
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3.30. Executing TECHMAP pass (map to technology primitives).
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3.30.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
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Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
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Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
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Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
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Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
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Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
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Generating RTLIL representation for module `\_90_simplemap_various'.
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Generating RTLIL representation for module `\_90_simplemap_registers'.
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Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
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Generating RTLIL representation for module `\_90_shift_shiftx'.
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Generating RTLIL representation for module `\_90_fa'.
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Generating RTLIL representation for module `\_90_lcu'.
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Generating RTLIL representation for module `\_90_alu'.
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Generating RTLIL representation for module `\_90_macc'.
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Generating RTLIL representation for module `\_90_alumacc'.
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Generating RTLIL representation for module `\$__div_mod_u'.
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Generating RTLIL representation for module `\$__div_mod'.
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Generating RTLIL representation for module `\_90_div'.
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Generating RTLIL representation for module `\_90_mod'.
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Generating RTLIL representation for module `\_90_pow'.
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Generating RTLIL representation for module `\_90_pmux'.
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Generating RTLIL representation for module `\_90_lut'.
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Successfully finished Verilog frontend.
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3.30.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
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Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
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Generating RTLIL representation for module `\_80_ice40_alu'.
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Successfully finished Verilog frontend.
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3.30.3. Continuing TECHMAP pass.
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Using extmapper simplemap for cells of type $not.
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No more expansions possible.
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<suppressed ~7 debug messages>
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3.31. Executing ICE40_OPT pass (performing simple optimizations).
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3.31.1. Running ICE40 specific optimizations.
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3.31.2. Executing OPT_EXPR pass (perform const folding).
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Optimizing module top.
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3.31.3. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\top'.
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Removed a total of 0 cells.
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3.31.4. Executing OPT_RMDFF pass (remove dff with constant values).
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3.31.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.31.6. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
3.32. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).
|
|
|
|
3.33. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
|
|
Selected cell types for direct conversion:
|
|
$_DFF_PP1_ -> $__DFFE_PP1
|
|
$_DFF_PP0_ -> $__DFFE_PP0
|
|
$_DFF_PN1_ -> $__DFFE_PN1
|
|
$_DFF_PN0_ -> $__DFFE_PN0
|
|
$_DFF_NP1_ -> $__DFFE_NP1
|
|
$_DFF_NP0_ -> $__DFFE_NP0
|
|
$_DFF_NN1_ -> $__DFFE_NN1
|
|
$_DFF_NN0_ -> $__DFFE_NN0
|
|
$_DFF_N_ -> $_DFFE_NP_
|
|
$_DFF_P_ -> $_DFFE_PP_
|
|
Transforming FF to FF+Enable cells in module top:
|
|
|
|
3.34. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.34.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
|
|
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP1'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.34.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
|
|
3.35. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.36. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
3.37. Executing ICE40_FFINIT pass (implement FF init values).
|
|
Handling FF init values in top.
|
|
|
|
3.38. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
|
|
Merging set/reset $_MUX_ cells into SB_FFs in top.
|
|
|
|
3.39. Executing ICE40_OPT pass (performing simple optimizations).
|
|
|
|
3.39.1. Running ICE40 specific optimizations.
|
|
|
|
3.39.2. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.39.3. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.39.4. Executing OPT_RMDFF pass (remove dff with constant values).
|
|
|
|
3.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.39.6. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
3.40. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
|
|
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.40.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
|
|
3.41. Executing ABC pass (technology mapping using ABC).
|
|
|
|
3.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 7 gates and 14 wires to a netlist network with 7 inputs and 7 outputs.
|
|
|
|
3.41.1.1. Executing ABC.
|
|
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
|
|
ABC:
|
|
ABC: + read_blif <abc-temp-dir>/input.blif
|
|
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
|
|
ABC: + strash
|
|
ABC: + ifraig
|
|
ABC: + scorr
|
|
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
|
ABC: + dc2
|
|
ABC: + dretime
|
|
ABC: + retime
|
|
ABC: + strash
|
|
ABC: + dch -f
|
|
ABC: + if
|
|
ABC: + mfs2
|
|
ABC: + lutpack -S 1
|
|
ABC: + dress
|
|
ABC: Total number of equiv classes = 8.
|
|
ABC: Participating nodes from both networks = 14.
|
|
ABC: Participating nodes from the first network = 7. ( 87.50 % of nodes)
|
|
ABC: Participating nodes from the second network = 7. ( 87.50 % of nodes)
|
|
ABC: Node pairs (any polarity) = 7. ( 87.50 % of names can be moved)
|
|
ABC: Node pairs (same polarity) = 7. ( 87.50 % of names can be moved)
|
|
ABC: Total runtime = 0.00 sec
|
|
ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
|
3.41.1.2. Re-integrating ABC results.
|
|
ABC RESULTS: $lut cells: 14
|
|
ABC RESULTS: internal signals: 0
|
|
ABC RESULTS: input signals: 7
|
|
ABC RESULTS: output signals: 7
|
|
Removing temp directory.
|
|
Removed 0 unused cells and 14 unused wires.
|
|
|
|
3.42. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
|
|
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PN1_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PN1'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_NP1'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP0'.
|
|
Generating RTLIL representation for module `\$__DFFE_PP1'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.42.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~18 debug messages>
|
|
Removed 0 unused cells and 14 unused wires.
|
|
|
|
3.43. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
3.43.1. Analyzing design hierarchy..
|
|
Top module: \top
|
|
|
|
3.43.2. Analyzing design hierarchy..
|
|
Top module: \top
|
|
Removed 0 unused modules.
|
|
|
|
3.44. Printing statistics.
|
|
|
|
=== top ===
|
|
|
|
Number of wires: 27
|
|
Number of wire bits: 29
|
|
Number of public wires: 27
|
|
Number of public wire bits: 29
|
|
Number of memories: 0
|
|
Number of memory bits: 0
|
|
Number of processes: 0
|
|
Number of cells: 8
|
|
SB_IO 1
|
|
SB_LUT4 7
|
|
|
|
3.45. Executing CHECK pass (checking for obvious problems).
|
|
checking module top..
|
|
found and reported 0 problems.
|
|
|
|
3.46. Executing JSON backend.
|
|
|
|
Warnings: 1 unique messages, 1 total
|
|
End of script. Logfile hash: f800107203
|
|
CPU: user 0.26s system 0.01s, MEM: 30.72 MB total, 25.27 MB resident
|
|
Yosys 0.9 (git sha1 1979e0b)
|
|
Time spent: 51% 11x read_verilog (0 sec), 15% 1x share (0 sec), ...
|