/* Machine-generated using Migen */
module top(
	output eem0_n,
	output eem0_p,
	output eem0_n_1,
	output eem0_p_1,
	inout eem0_n_2,
	output eem0_n_3,
	output eem0_p_2,
	output eem0_n_4,
	output eem0_p_3,
	output eem0_n_5,
	output eem0_p_4,
	output eem0_n_6,
	output eem0_p_5,
	input spi_cs_n,
	output spi_miso,
	input spi_mosi,
	input spi_clk,
	input spi_mosi_1,
	input [2:0] spi_cs,
	output user_led,
	input io_update,
	input clk25
);

wire miso_n;
wire sys_clk;
wire sys_rst;
wire por_clk;
reg int_rst = 1'd1;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on

assign eem0_p = spi_clk;		//ch0
assign eem0_n = (~spi_clk);
assign eem0_p_1 = spi_mosi_1;	//ch1
assign eem0_n_1 = (~spi_mosi_1);
assign spi_miso = (~miso_n);
assign eem0_p_2 = spi_cs[0];	//ch3
assign eem0_n_3 = (~spi_cs[0]);
assign eem0_p_3 = spi_cs[1];	//ch4
assign eem0_n_4 = (~spi_cs[1]);
assign eem0_p_4 = spi_cs[2];	//ch5
assign eem0_n_5 = (~spi_cs[2]);
assign eem0_p_5 = io_update;	//ch6
assign eem0_n_6 = (~io_update);
assign user_led = 1'd1;
assign sys_clk = clk25;
assign por_clk = clk25;
assign sys_rst = int_rst;

always @(posedge por_clk) begin
	int_rst <= 1'd0;
end

SB_IO #(
	.IO_STANDARD("SB_LVDS_INPUT"),
	.PIN_TYPE(6'd1)
) SB_IO (
	.PACKAGE_PIN(eem0_n_2),
	.D_IN_0(miso_n)
);

endmodule