/** ****************************************************************************** * File Name : FSMC.c * Description : This file provides code for the configuration * of the FSMC peripheral. ****************************************************************************** * @attention * *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "fsmc.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ SRAM_HandleTypeDef hsram1; /* FSMC initialization function */ void MX_FSMC_Init(void) { /* USER CODE BEGIN FSMC_Init 0 */ /* USER CODE END FSMC_Init 0 */ FSMC_NORSRAM_TimingTypeDef Timing = {0}; /* USER CODE BEGIN FSMC_Init 1 */ /* USER CODE END FSMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FSMC_NORSRAM_DEVICE; hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; /* hsram1.Init */ hsram1.Init.NSBank = FSMC_NORSRAM_BANK1; hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_ENABLE; hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_PSRAM; hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8; hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; /* Timing */ Timing.AddressSetupTime = 15; Timing.AddressHoldTime = 15; Timing.DataSetupTime = 255; Timing.BusTurnAroundDuration = 15; Timing.CLKDivision = 16; Timing.DataLatency = 17; Timing.AccessMode = FSMC_ACCESS_MODE_A; /* ExtTiming */ if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) { Error_Handler( ); } /** Disconnect NADV */ __HAL_AFIO_FSMCNADV_DISCONNECTED(); /* USER CODE BEGIN FSMC_Init 2 */ /* USER CODE END FSMC_Init 2 */ } static uint32_t FSMC_Initialized = 0; static void HAL_FSMC_MspInit(void){ /* USER CODE BEGIN FSMC_MspInit 0 */ /* USER CODE END FSMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct = {0}; if (FSMC_Initialized) { return; } FSMC_Initialized = 1; /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_ENABLE(); /** FSMC GPIO Configuration PE2 ------> FSMC_A23 PE3 ------> FSMC_A19 PE4 ------> FSMC_A20 PE5 ------> FSMC_A21 PE6 ------> FSMC_A22 PE7 ------> FSMC_DA4 PE8 ------> FSMC_DA5 PE9 ------> FSMC_DA6 PE10 ------> FSMC_DA7 PE11 ------> FSMC_DA8 PE12 ------> FSMC_DA9 PE13 ------> FSMC_DA10 PE14 ------> FSMC_DA11 PE15 ------> FSMC_DA12 PD8 ------> FSMC_DA13 PD9 ------> FSMC_DA14 PD10 ------> FSMC_DA15 PD11 ------> FSMC_A16 PD12 ------> FSMC_A17 PD13 ------> FSMC_A18 PD14 ------> FSMC_DA0 PD15 ------> FSMC_DA1 PD0 ------> FSMC_DA2 PD1 ------> FSMC_DA3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PD7 ------> FSMC_NE1 */ /* GPIO_InitStruct */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9 |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 |GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); /* GPIO_InitStruct */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); /* USER CODE BEGIN FSMC_MspInit 1 */ /* USER CODE END FSMC_MspInit 1 */ } void HAL_SRAM_MspInit(SRAM_HandleTypeDef* sramHandle){ /* USER CODE BEGIN SRAM_MspInit 0 */ /* USER CODE END SRAM_MspInit 0 */ HAL_FSMC_MspInit(); /* USER CODE BEGIN SRAM_MspInit 1 */ /* USER CODE END SRAM_MspInit 1 */ } static uint32_t FSMC_DeInitialized = 0; static void HAL_FSMC_MspDeInit(void){ /* USER CODE BEGIN FSMC_MspDeInit 0 */ /* USER CODE END FSMC_MspDeInit 0 */ if (FSMC_DeInitialized) { return; } FSMC_DeInitialized = 1; /* Peripheral clock enable */ __HAL_RCC_FSMC_CLK_DISABLE(); /** FSMC GPIO Configuration PE2 ------> FSMC_A23 PE3 ------> FSMC_A19 PE4 ------> FSMC_A20 PE5 ------> FSMC_A21 PE6 ------> FSMC_A22 PE7 ------> FSMC_DA4 PE8 ------> FSMC_DA5 PE9 ------> FSMC_DA6 PE10 ------> FSMC_DA7 PE11 ------> FSMC_DA8 PE12 ------> FSMC_DA9 PE13 ------> FSMC_DA10 PE14 ------> FSMC_DA11 PE15 ------> FSMC_DA12 PD8 ------> FSMC_DA13 PD9 ------> FSMC_DA14 PD10 ------> FSMC_DA15 PD11 ------> FSMC_A16 PD12 ------> FSMC_A17 PD13 ------> FSMC_A18 PD14 ------> FSMC_DA0 PD15 ------> FSMC_DA1 PD0 ------> FSMC_DA2 PD1 ------> FSMC_DA3 PD4 ------> FSMC_NOE PD5 ------> FSMC_NWE PD7 ------> FSMC_NE1 */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9 |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13 |GPIO_PIN_14|GPIO_PIN_15); HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 |GPIO_PIN_7); /* USER CODE BEGIN FSMC_MspDeInit 1 */ /* USER CODE END FSMC_MspDeInit 1 */ } void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* sramHandle){ /* USER CODE BEGIN SRAM_MspDeInit 0 */ /* USER CODE END SRAM_MspDeInit 0 */ HAL_FSMC_MspDeInit(); /* USER CODE BEGIN SRAM_MspDeInit 1 */ /* USER CODE END SRAM_MspDeInit 1 */ } /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/