Syrostan-MCU-C/Core/Src/User/ethernet.c

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#include "ethernet.h"
#include "spi.h"
uint8_t enc_mac_address[6];
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void ethernet_spi_1_byte(uint8_t spi_cmd)
{
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi1, &spi_cmd, 1, 100);
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_SET);
}
void ethernet_spi_2_byte(uint8_t spi_cmd, uint8_t *spi_data)
{
ethernet_spi_n_byte_banked(ENC_SPI_READ, spi_cmd, spi_data, 1);
}
void ethernet_spi_3_byte(enc_spi_operate_type_t type, uint8_t spi_cmd, uint8_t *spi_data)
{
ethernet_spi_n_byte_banked(type, spi_cmd, spi_data, 2);
}
void ethernet_spi_n_byte_banked(enc_spi_operate_type_t type, uint8_t spi_cmd, uint8_t *spi_data, uint8_t n)
{
switch (type)
{
case ENC_SPI_WRITE:
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi1, &spi_cmd, 1, 100);
HAL_SPI_Transmit(&hspi1, spi_data, n, 100);
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_SET);
break;
case ENC_SPI_READ:
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi1, &spi_cmd, 1, 100);
HAL_SPI_Receive(&hspi1, spi_data, n, 100);
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_SET);
break;
default:
break;
}
}
void ethernet_spi_n_byte_unbanked(enc_spi_operate_type_t type, uint8_t spi_cmd, uint8_t unbanked_address, uint8_t *spi_data, uint8_t n)
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{
switch (type)
{
case ENC_SPI_WRITE:
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi1, &spi_cmd, 1, 100);
HAL_SPI_Transmit(&hspi1, &unbanked_address, 1, 100);
HAL_SPI_Transmit(&hspi1, spi_data, n, 100);
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_SET);
break;
case ENC_SPI_READ:
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi1, &spi_cmd, 1, 100);
HAL_SPI_Transmit(&hspi1, &unbanked_address, 1, 100);
HAL_SPI_Receive(&hspi1, spi_data, n, 100);
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_SET);
break;
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default:
break;
}
}
void ethernet_init_check()
{
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uint16_t spi_test_data = 0;
spi_test_data = 1234U;
ethernet_spi_n_byte_unbanked(ENC_SPI_WRITE, ENC_CMD_WCRU, 0x16, (uint8_t*)&spi_test_data, sizeof(spi_test_data));
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spi_test_data = 0;
ethernet_spi_n_byte_unbanked(ENC_SPI_READ, ENC_CMD_RCRU, 0x16, (uint8_t*)&spi_test_data, sizeof(spi_test_data));
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while(spi_test_data != 1234U);
do
{
ethernet_spi_n_byte_unbanked(ENC_SPI_READ, ENC_CMD_RCRU, 0x1A, (uint8_t*)&spi_test_data, sizeof(spi_test_data));
HAL_Delay(1);
}
while((spi_test_data & (0x0001 << 12U)) == 0x0000);
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ethernet_spi_1_byte(ENC_CMD_RESET);
HAL_Delay(1);
ethernet_spi_n_byte_banked(ENC_SPI_READ, ENC_CMD_RCR(0x16), (uint8_t*)&spi_test_data, sizeof(spi_test_data));
while(spi_test_data != 0x0000);
HAL_Delay(1);
}
void ethernet_init_config()
{
uint16_t spi_data_buffer = 0;
spi_data_buffer = 0x5000; //4096 bytes rx buffer
ethernet_spi_n_byte_unbanked(ENC_SPI_WRITE, ENC_CMD_WCRU, 0x04, (uint8_t*)&spi_data_buffer, sizeof(spi_data_buffer));
spi_data_buffer = 1522U; //rx package max 1522 bytes
ethernet_spi_n_byte_unbanked(ENC_SPI_WRITE, ENC_CMD_WCRU, 0x4A, (uint8_t*)&spi_data_buffer, sizeof(spi_data_buffer));
spi_data_buffer = 0x0001 << 0U; //Set the RXEN bit (ECON1<0>) to enable packet reception by the MAC
ethernet_spi_n_byte_unbanked(ENC_SPI_WRITE, ENC_CMD_WCRU, 0x3E, (uint8_t*)&spi_data_buffer, sizeof(spi_data_buffer));
}
void ethernet_init()
{
HAL_GPIO_WritePin(SPI_ENC_CS_GPIO_Port, SPI_ENC_CS_Pin, GPIO_PIN_SET);
uint8_t spi_dummy_data = 0x00;
HAL_SPI_Transmit(&hspi1, &spi_dummy_data, 1, 100); //dummy transmition to make the clock low
ethernet_init_check();
// ethernet_init_config();
ethernet_spi_n_byte_unbanked(ENC_SPI_READ, ENC_CMD_RCRU, 0x60, (uint8_t*)&enc_mac_address, sizeof(enc_mac_address));
}